arch/arm/boot/dts/sun7i-a20.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include "skeleton.dtsi"
  46
  47 #include <dt-bindings/interrupt-controller/arm-gic.h>
  48 #include <dt-bindings/thermal/thermal.h>
  49
  50 #include <dt-bindings/clock/sun4i-a10-pll2.h>
  51 #include <dt-bindings/dma/sun4i-a10.h>
  52 #include <dt-bindings/pinctrl/sun4i-a10.h>
  53
  54 / {
  55         interrupt-parent = <&gic>;
  56
  57         aliases {
  58                 ethernet0 = &gmac;
  59         };
  60
  61         chosen {
  62                 #address-cells = <1>;
  63                 #size-cells = <1>;
  64                 ranges;
  65
  66                 framebuffer@0 {
  67                         compatible = "allwinner,simple-framebuffer",
  68                                      "simple-framebuffer";
  69                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  70                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
  71                                  <&ahb_gates 44>, <&dram_gates 26>;
  72                         status = "disabled";
  73                 };
  74
  75                 framebuffer@1 {
  76                         compatible = "allwinner,simple-framebuffer",
  77                                      "simple-framebuffer";
  78                         allwinner,pipeline = "de_be0-lcd0";
  79                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
  80                                  <&dram_gates 26>;
  81                         status = "disabled";
  82                 };
  83
  84                 framebuffer@2 {
  85                         compatible = "allwinner,simple-framebuffer",
  86                                      "simple-framebuffer";
  87                         allwinner,pipeline = "de_be0-lcd0-tve0";
  88                         clocks = <&pll5 1>,
  89                                  <&ahb_gates 34>, <&ahb_gates 36>, <&ahb_gates 44>,
  90                                  <&dram_gates 5>, <&dram_gates 26>;
  91                         status = "disabled";
  92                 };
  93         };
  94
  95         cpus {
  96                 #address-cells = <1>;
  97                 #size-cells = <0>;
  98
  99                 cpu0: cpu@0 {
 100                         compatible = "arm,cortex-a7";
 101                         device_type = "cpu";
 102                         reg = <0>;
 103                         clocks = <&cpu>;
 104                         clock-latency = <244144>; /* 8 32k periods */
 105                         operating-points = <
 106                                 /* kHz    uV */
 107                                 960000  1400000
 108                                 912000  1400000
 109                                 864000  1300000
 110                                 720000  1200000
 111                                 528000  1100000
 112                                 312000  1000000
 113                                 144000  1000000
 114                                 >;
 115                         #cooling-cells = <2>;
 116                         cooling-min-level = <0>;
 117                         cooling-max-level = <6>;
 118                 };
 119
 120                 cpu@1 {
 121                         compatible = "arm,cortex-a7";
 122                         device_type = "cpu";
 123                         reg = <1>;
 124                 };
 125         };
 126
 127         thermal-zones {
 128                 cpu_thermal {
 129                         /* milliseconds */
 130                         polling-delay-passive = <250>;
 131                         polling-delay = <1000>;
 132                         thermal-sensors = <&rtp>;
 133
 134                         cooling-maps {
 135                                 map0 {
 136                                         trip = <&cpu_alert0>;
 137                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 138                                 };
 139                         };
 140
 141                         trips {
 142                                 cpu_alert0: cpu_alert0 {
 143                                         /* milliCelsius */
 144                                         temperature = <75000>;
 145                                         hysteresis = <2000>;
 146                                         type = "passive";
 147                                 };
 148
 149                                 cpu_crit: cpu_crit {
 150                                         /* milliCelsius */
 151                                         temperature = <100000>;
 152                                         hysteresis = <2000>;
 153                                         type = "critical";
 154                                 };
 155                         };
 156                 };
 157         };
 158
 159         memory {
 160                 reg = <0x40000000 0x80000000>;
 161         };
 162
 163         timer {
 164                 compatible = "arm,armv7-timer";
 165                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 166                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 167                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 168                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 169         };
 170
 171         pmu {
 172                 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
 173                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 174                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 175         };
 176
 177         clocks {
 178                 #address-cells = <1>;
 179                 #size-cells = <1>;
 180                 ranges;
 181
 182                 osc24M: clk@01c20050 {
 183                         #clock-cells = <0>;
 184                         compatible = "allwinner,sun4i-a10-osc-clk";
 185                         reg = <0x01c20050 0x4>;
 186                         clock-frequency = <24000000>;
 187                         clock-output-names = "osc24M";
 188                 };
 189
 190                 osc32k: clk@0 {
 191                         #clock-cells = <0>;
 192                         compatible = "fixed-clock";
 193                         clock-frequency = <32768>;
 194                         clock-output-names = "osc32k";
 195                 };
 196
 197                 pll1: clk@01c20000 {
 198                         #clock-cells = <0>;
 199                         compatible = "allwinner,sun4i-a10-pll1-clk";
 200                         reg = <0x01c20000 0x4>;
 201                         clocks = <&osc24M>;
 202                         clock-output-names = "pll1";
 203                 };
 204
 205                 pll2: clk@01c20008 {
 206                         #clock-cells = <1>;
 207                         compatible = "allwinner,sun4i-a10-pll2-clk";
 208                         reg = <0x01c20008 0x8>;
 209                         clocks = <&osc24M>;
 210                         clock-output-names = "pll2-1x", "pll2-2x",
 211                                              "pll2-4x", "pll2-8x";
 212                 };
 213
 214                 pll4: clk@01c20018 {
 215                         #clock-cells = <0>;
 216                         compatible = "allwinner,sun7i-a20-pll4-clk";
 217                         reg = <0x01c20018 0x4>;
 218                         clocks = <&osc24M>;
 219                         clock-output-names = "pll4";
 220                 };
 221
 222                 pll5: clk@01c20020 {
 223                         #clock-cells = <1>;
 224                         compatible = "allwinner,sun4i-a10-pll5-clk";
 225                         reg = <0x01c20020 0x4>;
 226                         clocks = <&osc24M>;
 227                         clock-output-names = "pll5_ddr", "pll5_other";
 228                 };
 229
 230                 pll6: clk@01c20028 {
 231                         #clock-cells = <1>;
 232                         compatible = "allwinner,sun4i-a10-pll6-clk";
 233                         reg = <0x01c20028 0x4>;
 234                         clocks = <&osc24M>;
 235                         clock-output-names = "pll6_sata", "pll6_other", "pll6",
 236                                              "pll6_div_4";
 237                 };
 238
 239                 pll8: clk@01c20040 {
 240                         #clock-cells = <0>;
 241                         compatible = "allwinner,sun7i-a20-pll4-clk";
 242                         reg = <0x01c20040 0x4>;
 243                         clocks = <&osc24M>;
 244                         clock-output-names = "pll8";
 245                 };
 246
 247                 cpu: cpu@01c20054 {
 248                         #clock-cells = <0>;
 249                         compatible = "allwinner,sun4i-a10-cpu-clk";
 250                         reg = <0x01c20054 0x4>;
 251                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
 252                         clock-output-names = "cpu";
 253                 };
 254
 255                 axi: axi@01c20054 {
 256                         #clock-cells = <0>;
 257                         compatible = "allwinner,sun4i-a10-axi-clk";
 258                         reg = <0x01c20054 0x4>;
 259                         clocks = <&cpu>;
 260                         clock-output-names = "axi";
 261                 };
 262
 263                 ahb: ahb@01c20054 {
 264                         #clock-cells = <0>;
 265                         compatible = "allwinner,sun5i-a13-ahb-clk";
 266                         reg = <0x01c20054 0x4>;
 267                         clocks = <&axi>, <&pll6 3>, <&pll6 1>;
 268                         clock-output-names = "ahb";
 269                         /*
 270                          * Use PLL6 as parent, instead of CPU/AXI
 271                          * which has rate changes due to cpufreq
 272                          */
 273                         assigned-clocks = <&ahb>;
 274                         assigned-clock-parents = <&pll6 3>;
 275                 };
 276
 277                 ahb_gates: clk@01c20060 {
 278                         #clock-cells = <1>;
 279                         compatible = "allwinner,sun7i-a20-ahb-gates-clk";
 280                         reg = <0x01c20060 0x8>;
 281                         clocks = <&ahb>;
 282                         clock-indices = <0>, <1>,
 283                                         <2>, <3>, <4>,
 284                                         <5>, <6>, <7>, <8>,
 285                                         <9>, <10>, <11>, <12>,
 286                                         <13>, <14>, <16>,
 287                                         <17>, <18>, <20>, <21>,
 288                                         <22>, <23>, <25>,
 289                                         <28>, <32>, <33>, <34>,
 290                                         <35>, <36>, <37>, <40>,
 291                                         <41>, <42>, <43>,
 292                                         <44>, <45>, <46>,
 293                                         <47>, <49>, <50>,
 294                                         <52>;
 295                         clock-output-names = "ahb_usb0", "ahb_ehci0",
 296                                 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
 297                                 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
 298                                 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
 299                                 "ahb_nand", "ahb_sdram", "ahb_ace",
 300                                 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
 301                                 "ahb_spi2", "ahb_spi3", "ahb_sata",
 302                                 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
 303                                 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
 304                                 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
 305                                 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
 306                                 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
 307                                 "ahb_mali";
 308                 };
 309
 310                 apb0: apb0@01c20054 {
 311                         #clock-cells = <0>;
 312                         compatible = "allwinner,sun4i-a10-apb0-clk";
 313                         reg = <0x01c20054 0x4>;
 314                         clocks = <&ahb>;
 315                         clock-output-names = "apb0";
 316                 };
 317
 318                 apb0_gates: clk@01c20068 {
 319                         #clock-cells = <1>;
 320                         compatible = "allwinner,sun7i-a20-apb0-gates-clk";
 321                         reg = <0x01c20068 0x4>;
 322                         clocks = <&apb0>;
 323                         clock-indices = <0>, <1>,
 324                                         <2>, <3>, <4>,
 325                                         <5>, <6>, <7>,
 326                                         <8>, <10>;
 327                         clock-output-names = "apb0_codec", "apb0_spdif",
 328                                 "apb0_ac97", "apb0_iis0", "apb0_iis1",
 329                                 "apb0_pio", "apb0_ir0", "apb0_ir1",
 330                                 "apb0_iis2", "apb0_keypad";
 331                 };
 332
 333                 apb1: clk@01c20058 {
 334                         #clock-cells = <0>;
 335                         compatible = "allwinner,sun4i-a10-apb1-clk";
 336                         reg = <0x01c20058 0x4>;
 337                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 338                         clock-output-names = "apb1";
 339                 };
 340
 341                 apb1_gates: clk@01c2006c {
 342                         #clock-cells = <1>;
 343                         compatible = "allwinner,sun7i-a20-apb1-gates-clk";
 344                         reg = <0x01c2006c 0x4>;
 345                         clocks = <&apb1>;
 346                         clock-indices = <0>, <1>,
 347                                         <2>, <3>, <4>,
 348                                         <5>, <6>, <7>,
 349                                         <15>, <16>, <17>,
 350                                         <18>, <19>, <20>,
 351                                         <21>, <22>, <23>;
 352                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 353                                 "apb1_i2c2", "apb1_i2c3", "apb1_can",
 354                                 "apb1_scr", "apb1_ps20", "apb1_ps21",
 355                                 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
 356                                 "apb1_uart2", "apb1_uart3", "apb1_uart4",
 357                                 "apb1_uart5", "apb1_uart6", "apb1_uart7";
 358                 };
 359
 360                 nand_clk: clk@01c20080 {
 361                         #clock-cells = <0>;
 362                         compatible = "allwinner,sun4i-a10-mod0-clk";
 363                         reg = <0x01c20080 0x4>;
 364                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 365                         clock-output-names = "nand";
 366                 };
 367
 368                 ms_clk: clk@01c20084 {
 369                         #clock-cells = <0>;
 370                         compatible = "allwinner,sun4i-a10-mod0-clk";
 371                         reg = <0x01c20084 0x4>;
 372                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 373                         clock-output-names = "ms";
 374                 };
 375
 376                 mmc0_clk: clk@01c20088 {
 377                         #clock-cells = <1>;
 378                         compatible = "allwinner,sun4i-a10-mmc-clk";
 379                         reg = <0x01c20088 0x4>;
 380                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 381                         clock-output-names = "mmc0",
 382                                              "mmc0_output",
 383                                              "mmc0_sample";
 384                 };
 385
 386                 mmc1_clk: clk@01c2008c {
 387                         #clock-cells = <1>;
 388                         compatible = "allwinner,sun4i-a10-mmc-clk";
 389                         reg = <0x01c2008c 0x4>;
 390                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 391                         clock-output-names = "mmc1",
 392                                              "mmc1_output",
 393                                              "mmc1_sample";
 394                 };
 395
 396                 mmc2_clk: clk@01c20090 {
 397                         #clock-cells = <1>;
 398                         compatible = "allwinner,sun4i-a10-mmc-clk";
 399                         reg = <0x01c20090 0x4>;
 400                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 401                         clock-output-names = "mmc2",
 402                                              "mmc2_output",
 403                                              "mmc2_sample";
 404                 };
 405
 406                 mmc3_clk: clk@01c20094 {
 407                         #clock-cells = <1>;
 408                         compatible = "allwinner,sun4i-a10-mmc-clk";
 409                         reg = <0x01c20094 0x4>;
 410                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 411                         clock-output-names = "mmc3",
 412                                              "mmc3_output",
 413                                              "mmc3_sample";
 414                 };
 415
 416                 ts_clk: clk@01c20098 {
 417                         #clock-cells = <0>;
 418                         compatible = "allwinner,sun4i-a10-mod0-clk";
 419                         reg = <0x01c20098 0x4>;
 420                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 421                         clock-output-names = "ts";
 422                 };
 423
 424                 ss_clk: clk@01c2009c {
 425                         #clock-cells = <0>;
 426                         compatible = "allwinner,sun4i-a10-mod0-clk";
 427                         reg = <0x01c2009c 0x4>;
 428                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 429                         clock-output-names = "ss";
 430                 };
 431
 432                 spi0_clk: clk@01c200a0 {
 433                         #clock-cells = <0>;
 434                         compatible = "allwinner,sun4i-a10-mod0-clk";
 435                         reg = <0x01c200a0 0x4>;
 436                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 437                         clock-output-names = "spi0";
 438                 };
 439
 440                 spi1_clk: clk@01c200a4 {
 441                         #clock-cells = <0>;
 442                         compatible = "allwinner,sun4i-a10-mod0-clk";
 443                         reg = <0x01c200a4 0x4>;
 444                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 445                         clock-output-names = "spi1";
 446                 };
 447
 448                 spi2_clk: clk@01c200a8 {
 449                         #clock-cells = <0>;
 450                         compatible = "allwinner,sun4i-a10-mod0-clk";
 451                         reg = <0x01c200a8 0x4>;
 452                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 453                         clock-output-names = "spi2";
 454                 };
 455
 456                 pata_clk: clk@01c200ac {
 457                         #clock-cells = <0>;
 458                         compatible = "allwinner,sun4i-a10-mod0-clk";
 459                         reg = <0x01c200ac 0x4>;
 460                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 461                         clock-output-names = "pata";
 462                 };
 463
 464                 ir0_clk: clk@01c200b0 {
 465                         #clock-cells = <0>;
 466                         compatible = "allwinner,sun4i-a10-mod0-clk";
 467                         reg = <0x01c200b0 0x4>;
 468                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 469                         clock-output-names = "ir0";
 470                 };
 471
 472                 ir1_clk: clk@01c200b4 {
 473                         #clock-cells = <0>;
 474                         compatible = "allwinner,sun4i-a10-mod0-clk";
 475                         reg = <0x01c200b4 0x4>;
 476                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 477                         clock-output-names = "ir1";
 478                 };
 479
 480                 spdif_clk: clk@01c200c0 {
 481                         #clock-cells = <0>;
 482                         compatible = "allwinner,sun4i-a10-mod1-clk";
 483                         reg = <0x01c200c0 0x4>;
 484                         clocks = <&pll2 SUN4I_A10_PLL2_8X>,
 485                                  <&pll2 SUN4I_A10_PLL2_4X>,
 486                                  <&pll2 SUN4I_A10_PLL2_2X>,
 487                                  <&pll2 SUN4I_A10_PLL2_1X>;
 488                         clock-output-names = "spdif";
 489                 };
 490
 491                 keypad_clk: clk@01c200c4 {
 492                         #clock-cells = <0>;
 493                         compatible = "allwinner,sun4i-a10-mod0-clk";
 494                         reg = <0x01c200c4 0x4>;
 495                         clocks = <&osc24M>;
 496                         clock-output-names = "keypad";
 497                 };
 498
 499                 usb_clk: clk@01c200cc {
 500                         #clock-cells = <1>;
 501                         #reset-cells = <1>;
 502                         compatible = "allwinner,sun4i-a10-usb-clk";
 503                         reg = <0x01c200cc 0x4>;
 504                         clocks = <&pll6 1>;
 505                         clock-output-names = "usb_ohci0", "usb_ohci1",
 506                                              "usb_phy";
 507                 };
 508
 509                 spi3_clk: clk@01c200d4 {
 510                         #clock-cells = <0>;
 511                         compatible = "allwinner,sun4i-a10-mod0-clk";
 512                         reg = <0x01c200d4 0x4>;
 513                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 514                         clock-output-names = "spi3";
 515                 };
 516
 517                 dram_gates: clk@01c20100 {
 518                         #clock-cells = <1>;
 519                         compatible = "allwinner,sun4i-a10-dram-gates-clk";
 520                         reg = <0x01c20100 0x4>;
 521                         clocks = <&pll5 0>;
 522                         clock-indices = <0>,
 523                                         <1>, <2>,
 524                                         <3>,
 525                                         <4>,
 526                                         <5>, <6>,
 527                                         <15>,
 528                                         <24>, <25>,
 529                                         <26>, <27>,
 530                                         <28>, <29>;
 531                         clock-output-names = "dram_ve",
 532                                              "dram_csi0", "dram_csi1",
 533                                              "dram_ts",
 534                                              "dram_tvd",
 535                                              "dram_tve0", "dram_tve1",
 536                                              "dram_output",
 537                                              "dram_de_fe1", "dram_de_fe0",
 538                                              "dram_de_be0", "dram_de_be1",
 539                                              "dram_de_mp", "dram_ace";
 540                 };
 541
 542                 ve_clk: clk@01c2013c {
 543                         #clock-cells = <0>;
 544                         #reset-cells = <0>;
 545                         compatible = "allwinner,sun4i-a10-ve-clk";
 546                         reg = <0x01c2013c 0x4>;
 547                         clocks = <&pll4>;
 548                         clock-output-names = "ve";
 549                 };
 550
 551                 codec_clk: clk@01c20140 {
 552                         #clock-cells = <0>;
 553                         compatible = "allwinner,sun4i-a10-codec-clk";
 554                         reg = <0x01c20140 0x4>;
 555                         clocks = <&pll2 SUN4I_A10_PLL2_1X>;
 556                         clock-output-names = "codec";
 557                 };
 558
 559                 mbus_clk: clk@01c2015c {
 560                         #clock-cells = <0>;
 561                         compatible = "allwinner,sun5i-a13-mbus-clk";
 562                         reg = <0x01c2015c 0x4>;
 563                         clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
 564                         clock-output-names = "mbus";
 565                 };
 566
 567                 /*
 568                  * The following two are dummy clocks, placeholders
 569                  * used in the gmac_tx clock. The gmac driver will
 570                  * choose one parent depending on the PHY interface
 571                  * mode, using clk_set_rate auto-reparenting.
 572                  *
 573                  * The actual TX clock rate is not controlled by the
 574                  * gmac_tx clock.
 575                  */
 576                 mii_phy_tx_clk: clk@2 {
 577                         #clock-cells = <0>;
 578                         compatible = "fixed-clock";
 579                         clock-frequency = <25000000>;
 580                         clock-output-names = "mii_phy_tx";
 581                 };
 582
 583                 gmac_int_tx_clk: clk@3 {
 584                         #clock-cells = <0>;
 585                         compatible = "fixed-clock";
 586                         clock-frequency = <125000000>;
 587                         clock-output-names = "gmac_int_tx";
 588                 };
 589
 590                 gmac_tx_clk: clk@01c20164 {
 591                         #clock-cells = <0>;
 592                         compatible = "allwinner,sun7i-a20-gmac-clk";
 593                         reg = <0x01c20164 0x4>;
 594                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 595                         clock-output-names = "gmac_tx";
 596                 };
 597
 598                 /*
 599                  * Dummy clock used by output clocks
 600                  */
 601                 osc24M_32k: clk@1 {
 602                         #clock-cells = <0>;
 603                         compatible = "fixed-factor-clock";
 604                         clock-div = <750>;
 605                         clock-mult = <1>;
 606                         clocks = <&osc24M>;
 607                         clock-output-names = "osc24M_32k";
 608                 };
 609
 610                 clk_out_a: clk@01c201f0 {
 611                         #clock-cells = <0>;
 612                         compatible = "allwinner,sun7i-a20-out-clk";
 613                         reg = <0x01c201f0 0x4>;
 614                         clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
 615                         clock-output-names = "clk_out_a";
 616                 };
 617
 618                 clk_out_b: clk@01c201f4 {
 619                         #clock-cells = <0>;
 620                         compatible = "allwinner,sun7i-a20-out-clk";
 621                         reg = <0x01c201f4 0x4>;
 622                         clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
 623                         clock-output-names = "clk_out_b";
 624                 };
 625         };
 626
 627         soc@01c00000 {
 628                 compatible = "simple-bus";
 629                 #address-cells = <1>;
 630                 #size-cells = <1>;
 631                 ranges;
 632
 633                 sram-controller@01c00000 {
 634                         compatible = "allwinner,sun4i-a10-sram-controller";
 635                         reg = <0x01c00000 0x30>;
 636                         #address-cells = <1>;
 637                         #size-cells = <1>;
 638                         ranges;
 639
 640                         sram_a: sram@00000000 {
 641                                 compatible = "mmio-sram";
 642                                 reg = <0x00000000 0xc000>;
 643                                 #address-cells = <1>;
 644                                 #size-cells = <1>;
 645                                 ranges = <0 0x00000000 0xc000>;
 646
 647                                 emac_sram: sram-section@8000 {
 648                                         compatible = "allwinner,sun4i-a10-sram-a3-a4";
 649                                         reg = <0x8000 0x4000>;
 650                                         status = "disabled";
 651                                 };
 652                         };
 653
 654                         sram_d: sram@00010000 {
 655                                 compatible = "mmio-sram";
 656                                 reg = <0x00010000 0x1000>;
 657                                 #address-cells = <1>;
 658                                 #size-cells = <1>;
 659                                 ranges = <0 0x00010000 0x1000>;
 660
 661                                 otg_sram: sram-section@0000 {
 662                                         compatible = "allwinner,sun4i-a10-sram-d";
 663                                         reg = <0x0000 0x1000>;
 664                                         status = "disabled";
 665                                 };
 666                         };
 667                 };
 668
 669                 nmi_intc: interrupt-controller@01c00030 {
 670                         compatible = "allwinner,sun7i-a20-sc-nmi";
 671                         interrupt-controller;
 672                         #interrupt-cells = <2>;
 673                         reg = <0x01c00030 0x0c>;
 674                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 675                 };
 676
 677                 dma: dma-controller@01c02000 {
 678                         compatible = "allwinner,sun4i-a10-dma";
 679                         reg = <0x01c02000 0x1000>;
 680                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 681                         clocks = <&ahb_gates 6>;
 682                         #dma-cells = <2>;
 683                 };
 684
 685                 spi0: spi@01c05000 {
 686                         compatible = "allwinner,sun4i-a10-spi";
 687                         reg = <0x01c05000 0x1000>;
 688                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 689                         clocks = <&ahb_gates 20>, <&spi0_clk>;
 690                         clock-names = "ahb", "mod";
 691                         dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 692                                <&dma SUN4I_DMA_DEDICATED 26>;
 693                         dma-names = "rx", "tx";
 694                         status = "disabled";
 695                         #address-cells = <1>;
 696                         #size-cells = <0>;
 697                 };
 698
 699                 spi1: spi@01c06000 {
 700                         compatible = "allwinner,sun4i-a10-spi";
 701                         reg = <0x01c06000 0x1000>;
 702                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 703                         clocks = <&ahb_gates 21>, <&spi1_clk>;
 704                         clock-names = "ahb", "mod";
 705                         dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 706                                <&dma SUN4I_DMA_DEDICATED 8>;
 707                         dma-names = "rx", "tx";
 708                         status = "disabled";
 709                         #address-cells = <1>;
 710                         #size-cells = <0>;
 711                 };
 712
 713                 emac: ethernet@01c0b000 {
 714                         compatible = "allwinner,sun4i-a10-emac";
 715                         reg = <0x01c0b000 0x1000>;
 716                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 717                         clocks = <&ahb_gates 17>;
 718                         allwinner,sram = <&emac_sram 1>;
 719                         status = "disabled";
 720                 };
 721
 722                 mdio: mdio@01c0b080 {
 723                         compatible = "allwinner,sun4i-a10-mdio";
 724                         reg = <0x01c0b080 0x14>;
 725                         status = "disabled";
 726                         #address-cells = <1>;
 727                         #size-cells = <0>;
 728                 };
 729
 730                 mmc0: mmc@01c0f000 {
 731                         compatible = "allwinner,sun5i-a13-mmc";
 732                         reg = <0x01c0f000 0x1000>;
 733                         clocks = <&ahb_gates 8>,
 734                                  <&mmc0_clk 0>,
 735                                  <&mmc0_clk 1>,
 736                                  <&mmc0_clk 2>;
 737                         clock-names = "ahb",
 738                                       "mmc",
 739                                       "output",
 740                                       "sample";
 741                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 742                         status = "disabled";
 743                         #address-cells = <1>;
 744                         #size-cells = <0>;
 745                 };
 746
 747                 mmc1: mmc@01c10000 {
 748                         compatible = "allwinner,sun5i-a13-mmc";
 749                         reg = <0x01c10000 0x1000>;
 750                         clocks = <&ahb_gates 9>,
 751                                  <&mmc1_clk 0>,
 752                                  <&mmc1_clk 1>,
 753                                  <&mmc1_clk 2>;
 754                         clock-names = "ahb",
 755                                       "mmc",
 756                                       "output",
 757                                       "sample";
 758                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 759                         status = "disabled";
 760                         #address-cells = <1>;
 761                         #size-cells = <0>;
 762                 };
 763
 764                 mmc2: mmc@01c11000 {
 765                         compatible = "allwinner,sun5i-a13-mmc";
 766                         reg = <0x01c11000 0x1000>;
 767                         clocks = <&ahb_gates 10>,
 768                                  <&mmc2_clk 0>,
 769                                  <&mmc2_clk 1>,
 770                                  <&mmc2_clk 2>;
 771                         clock-names = "ahb",
 772                                       "mmc",
 773                                       "output",
 774                                       "sample";
 775                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 776                         status = "disabled";
 777                         #address-cells = <1>;
 778                         #size-cells = <0>;
 779                 };
 780
 781                 mmc3: mmc@01c12000 {
 782                         compatible = "allwinner,sun5i-a13-mmc";
 783                         reg = <0x01c12000 0x1000>;
 784                         clocks = <&ahb_gates 11>,
 785                                  <&mmc3_clk 0>,
 786                                  <&mmc3_clk 1>,
 787                                  <&mmc3_clk 2>;
 788                         clock-names = "ahb",
 789                                       "mmc",
 790                                       "output",
 791                                       "sample";
 792                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 793                         status = "disabled";
 794                         #address-cells = <1>;
 795                         #size-cells = <0>;
 796                 };
 797
 798                 usb_otg: usb@01c13000 {
 799                         compatible = "allwinner,sun4i-a10-musb";
 800                         reg = <0x01c13000 0x0400>;
 801                         clocks = <&ahb_gates 0>;
 802                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 803                         interrupt-names = "mc";
 804                         phys = <&usbphy 0>;
 805                         phy-names = "usb";
 806                         extcon = <&usbphy 0>;
 807                         allwinner,sram = <&otg_sram 1>;
 808                         status = "disabled";
 809                 };
 810
 811                 usbphy: phy@01c13400 {
 812                         #phy-cells = <1>;
 813                         compatible = "allwinner,sun7i-a20-usb-phy";
 814                         reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
 815                         reg-names = "phy_ctrl", "pmu1", "pmu2";
 816                         clocks = <&usb_clk 8>;
 817                         clock-names = "usb_phy";
 818                         resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
 819                         reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
 820                         status = "disabled";
 821                 };
 822
 823                 ehci0: usb@01c14000 {
 824                         compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
 825                         reg = <0x01c14000 0x100>;
 826                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 827                         clocks = <&ahb_gates 1>;
 828                         phys = <&usbphy 1>;
 829                         phy-names = "usb";
 830                         status = "disabled";
 831                 };
 832
 833                 ohci0: usb@01c14400 {
 834                         compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
 835                         reg = <0x01c14400 0x100>;
 836                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 837                         clocks = <&usb_clk 6>, <&ahb_gates 2>;
 838                         phys = <&usbphy 1>;
 839                         phy-names = "usb";
 840                         status = "disabled";
 841                 };
 842
 843                 crypto: crypto-engine@01c15000 {
 844                         compatible = "allwinner,sun4i-a10-crypto";
 845                         reg = <0x01c15000 0x1000>;
 846                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 847                         clocks = <&ahb_gates 5>, <&ss_clk>;
 848                         clock-names = "ahb", "mod";
 849                 };
 850
 851                 spi2: spi@01c17000 {
 852                         compatible = "allwinner,sun4i-a10-spi";
 853                         reg = <0x01c17000 0x1000>;
 854                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 855                         clocks = <&ahb_gates 22>, <&spi2_clk>;
 856                         clock-names = "ahb", "mod";
 857                         dmas = <&dma SUN4I_DMA_DEDICATED 29>,
 858                                <&dma SUN4I_DMA_DEDICATED 28>;
 859                         dma-names = "rx", "tx";
 860                         status = "disabled";
 861                         #address-cells = <1>;
 862                         #size-cells = <0>;
 863                 };
 864
 865                 ahci: sata@01c18000 {
 866                         compatible = "allwinner,sun4i-a10-ahci";
 867                         reg = <0x01c18000 0x1000>;
 868                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 869                         clocks = <&pll6 0>, <&ahb_gates 25>;
 870                         status = "disabled";
 871                 };
 872
 873                 ehci1: usb@01c1c000 {
 874                         compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
 875                         reg = <0x01c1c000 0x100>;
 876                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 877                         clocks = <&ahb_gates 3>;
 878                         phys = <&usbphy 2>;
 879                         phy-names = "usb";
 880                         status = "disabled";
 881                 };
 882
 883                 ohci1: usb@01c1c400 {
 884                         compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
 885                         reg = <0x01c1c400 0x100>;
 886                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 887                         clocks = <&usb_clk 7>, <&ahb_gates 4>;
 888                         phys = <&usbphy 2>;
 889                         phy-names = "usb";
 890                         status = "disabled";
 891                 };
 892
 893                 spi3: spi@01c1f000 {
 894                         compatible = "allwinner,sun4i-a10-spi";
 895                         reg = <0x01c1f000 0x1000>;
 896                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 897                         clocks = <&ahb_gates 23>, <&spi3_clk>;
 898                         clock-names = "ahb", "mod";
 899                         dmas = <&dma SUN4I_DMA_DEDICATED 31>,
 900                                <&dma SUN4I_DMA_DEDICATED 30>;
 901                         dma-names = "rx", "tx";
 902                         status = "disabled";
 903                         #address-cells = <1>;
 904                         #size-cells = <0>;
 905                 };
 906
 907                 pio: pinctrl@01c20800 {
 908                         compatible = "allwinner,sun7i-a20-pinctrl";
 909                         reg = <0x01c20800 0x400>;
 910                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 911                         clocks = <&apb0_gates 5>;
 912                         gpio-controller;
 913                         interrupt-controller;
 914                         #interrupt-cells = <3>;
 915                         #gpio-cells = <3>;
 916
 917                         pwm0_pins_a: pwm0@0 {
 918                                 allwinner,pins = "PB2";
 919                                 allwinner,function = "pwm";
 920                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 921                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 922                         };
 923
 924                         pwm1_pins_a: pwm1@0 {
 925                                 allwinner,pins = "PI3";
 926                                 allwinner,function = "pwm";
 927                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 928                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 929                         };
 930
 931                         uart0_pins_a: uart0@0 {
 932                                 allwinner,pins = "PB22", "PB23";
 933                                 allwinner,function = "uart0";
 934                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 935                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 936                         };
 937
 938                         uart2_pins_a: uart2@0 {
 939                                 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
 940                                 allwinner,function = "uart2";
 941                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 942                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 943                         };
 944
 945                         uart3_pins_a: uart3@0 {
 946                                 allwinner,pins = "PG6", "PG7", "PG8", "PG9";
 947                                 allwinner,function = "uart3";
 948                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 949                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 950                         };
 951
 952                         uart3_pins_b: uart3@1 {
 953                                 allwinner,pins = "PH0", "PH1";
 954                                 allwinner,function = "uart3";
 955                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 956                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 957                         };
 958
 959                         uart4_pins_a: uart4@0 {
 960                                 allwinner,pins = "PG10", "PG11";
 961                                 allwinner,function = "uart4";
 962                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 963                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 964                         };
 965
 966                         uart4_pins_b: uart4@1 {
 967                                 allwinner,pins = "PH4", "PH5";
 968                                 allwinner,function = "uart4";
 969                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 970                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 971                         };
 972
 973                         uart5_pins_a: uart5@0 {
 974                                 allwinner,pins = "PI10", "PI11";
 975                                 allwinner,function = "uart5";
 976                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 977                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 978                         };
 979
 980                         uart6_pins_a: uart6@0 {
 981                                 allwinner,pins = "PI12", "PI13";
 982                                 allwinner,function = "uart6";
 983                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 984                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 985                         };
 986
 987                         uart7_pins_a: uart7@0 {
 988                                 allwinner,pins = "PI20", "PI21";
 989                                 allwinner,function = "uart7";
 990                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 991                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 992                         };
 993
 994                         i2c0_pins_a: i2c0@0 {
 995                                 allwinner,pins = "PB0", "PB1";
 996                                 allwinner,function = "i2c0";
 997                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 998                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 999                         };
1000
1001                         i2c1_pins_a: i2c1@0 {
1002                                 allwinner,pins = "PB18", "PB19";
1003                                 allwinner,function = "i2c1";
1004                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1005                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1006                         };
1007
1008                         i2c2_pins_a: i2c2@0 {
1009                                 allwinner,pins = "PB20", "PB21";
1010                                 allwinner,function = "i2c2";
1011                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1012                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1013                         };
1014
1015                         i2c3_pins_a: i2c3@0 {
1016                                 allwinner,pins = "PI0", "PI1";
1017                                 allwinner,function = "i2c3";
1018                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1019                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1020                         };
1021
1022                         emac_pins_a: emac0@0 {
1023                                 allwinner,pins = "PA0", "PA1", "PA2",
1024                                                 "PA3", "PA4", "PA5", "PA6",
1025                                                 "PA7", "PA8", "PA9", "PA10",
1026                                                 "PA11", "PA12", "PA13", "PA14",
1027                                                 "PA15", "PA16";
1028                                 allwinner,function = "emac";
1029                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1030                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1031                         };
1032
1033                         clk_out_a_pins_a: clk_out_a@0 {
1034                                 allwinner,pins = "PI12";
1035                                 allwinner,function = "clk_out_a";
1036                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1037                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1038                         };
1039
1040                         clk_out_b_pins_a: clk_out_b@0 {
1041                                 allwinner,pins = "PI13";
1042                                 allwinner,function = "clk_out_b";
1043                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1044                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1045                         };
1046
1047                         gmac_pins_mii_a: gmac_mii@0 {
1048                                 allwinner,pins = "PA0", "PA1", "PA2",
1049                                                 "PA3", "PA4", "PA5", "PA6",
1050                                                 "PA7", "PA8", "PA9", "PA10",
1051                                                 "PA11", "PA12", "PA13", "PA14",
1052                                                 "PA15", "PA16";
1053                                 allwinner,function = "gmac";
1054                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1055                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1056                         };
1057
1058                         gmac_pins_rgmii_a: gmac_rgmii@0 {
1059                                 allwinner,pins = "PA0", "PA1", "PA2",
1060                                                 "PA3", "PA4", "PA5", "PA6",
1061                                                 "PA7", "PA8", "PA10",
1062                                                 "PA11", "PA12", "PA13",
1063                                                 "PA15", "PA16";
1064                                 allwinner,function = "gmac";
1065                                 /*
1066                                  * data lines in RGMII mode use DDR mode
1067                                  * and need a higher signal drive strength
1068                                  */
1069                                 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
1070                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1071                         };
1072
1073                         spi0_pins_a: spi0@0 {
1074                                 allwinner,pins = "PI11", "PI12", "PI13";
1075                                 allwinner,function = "spi0";
1076                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1077                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1078                         };
1079
1080                         spi0_cs0_pins_a: spi0_cs0@0 {
1081                                 allwinner,pins = "PI10";
1082                                 allwinner,function = "spi0";
1083                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1084                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1085                         };
1086
1087                         spi0_cs1_pins_a: spi0_cs1@0 {
1088                                 allwinner,pins = "PI14";
1089                                 allwinner,function = "spi0";
1090                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1091                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1092                         };
1093
1094                         spi1_pins_a: spi1@0 {
1095                                 allwinner,pins = "PI17", "PI18", "PI19";
1096                                 allwinner,function = "spi1";
1097                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1098                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1099                         };
1100
1101                         spi1_cs0_pins_a: spi1_cs0@0 {
1102                                 allwinner,pins = "PI16";
1103                                 allwinner,function = "spi1";
1104                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1105                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1106                         };
1107
1108                         spi2_pins_a: spi2@0 {
1109                                 allwinner,pins = "PC20", "PC21", "PC22";
1110                                 allwinner,function = "spi2";
1111                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1112                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1113                         };
1114
1115                         spi2_pins_b: spi2@1 {
1116                                 allwinner,pins = "PB15", "PB16", "PB17";
1117                                 allwinner,function = "spi2";
1118                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1119                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1120                         };
1121
1122                         spi2_cs0_pins_a: spi2_cs0@0 {
1123                                 allwinner,pins = "PC19";
1124                                 allwinner,function = "spi2";
1125                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1126                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1127                         };
1128
1129                         spi2_cs0_pins_b: spi2_cs0@1 {
1130                                 allwinner,pins = "PB14";
1131                                 allwinner,function = "spi2";
1132                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1133                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1134                         };
1135
1136                         mmc0_pins_a: mmc0@0 {
1137                                 allwinner,pins = "PF0", "PF1", "PF2",
1138                                                  "PF3", "PF4", "PF5";
1139                                 allwinner,function = "mmc0";
1140                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
1141                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1142                         };
1143
1144                         mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
1145                                 allwinner,pins = "PH1";
1146                                 allwinner,function = "gpio_in";
1147                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1148                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
1149                         };
1150
1151                         mmc2_pins_a: mmc2@0 {
1152                                 allwinner,pins = "PC6", "PC7", "PC8",
1153                                                  "PC9", "PC10", "PC11";
1154                                 allwinner,function = "mmc2";
1155                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
1156                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
1157                         };
1158
1159                         mmc3_pins_a: mmc3@0 {
1160                                 allwinner,pins = "PI4", "PI5", "PI6",
1161                                                  "PI7", "PI8", "PI9";
1162                                 allwinner,function = "mmc3";
1163                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
1164                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1165                         };
1166
1167                         ir0_rx_pins_a: ir0@0 {
1168                                     allwinner,pins = "PB4";
1169                                     allwinner,function = "ir0";
1170                                     allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1171                                     allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1172                         };
1173
1174                         ir0_tx_pins_a: ir0@1 {
1175                                     allwinner,pins = "PB3";
1176                                     allwinner,function = "ir0";
1177                                     allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1178                                     allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1179                         };
1180
1181                         ir1_rx_pins_a: ir1@0 {
1182                                     allwinner,pins = "PB23";
1183                                     allwinner,function = "ir1";
1184                                     allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1185                                     allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1186                         };
1187
1188                         ir1_tx_pins_a: ir1@1 {
1189                                     allwinner,pins = "PB22";
1190                                     allwinner,function = "ir1";
1191                                     allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1192                                     allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1193                         };
1194
1195                         ps20_pins_a: ps20@0 {
1196                                 allwinner,pins = "PI20", "PI21";
1197                                 allwinner,function = "ps2";
1198                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1199                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1200                         };
1201
1202                         ps21_pins_a: ps21@0 {
1203                                 allwinner,pins = "PH12", "PH13";
1204                                 allwinner,function = "ps2";
1205                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1206                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1207                         };
1208
1209                         spdif_tx_pins_a: spdif@0 {
1210                                 allwinner,pins = "PB13";
1211                                 allwinner,function = "spdif";
1212                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1213                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
1214                         };
1215                 };
1216
1217                 timer@01c20c00 {
1218                         compatible = "allwinner,sun4i-a10-timer";
1219                         reg = <0x01c20c00 0x90>;
1220                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
1221                                      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
1222                                      <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1223                                      <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1224                                      <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
1225                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1226                         clocks = <&osc24M>;
1227                 };
1228
1229                 wdt: watchdog@01c20c90 {
1230                         compatible = "allwinner,sun4i-a10-wdt";
1231                         reg = <0x01c20c90 0x10>;
1232                 };
1233
1234                 rtc: rtc@01c20d00 {
1235                         compatible = "allwinner,sun7i-a20-rtc";
1236                         reg = <0x01c20d00 0x20>;
1237                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1238                 };
1239
1240                 pwm: pwm@01c20e00 {
1241                         compatible = "allwinner,sun7i-a20-pwm";
1242                         reg = <0x01c20e00 0xc>;
1243                         clocks = <&osc24M>;
1244                         #pwm-cells = <3>;
1245                         status = "disabled";
1246                 };
1247
1248                 spdif: spdif@01c21000 {
1249                         #sound-dai-cells = <0>;
1250                         compatible = "allwinner,sun4i-a10-spdif";
1251                         reg = <0x01c21000 0x400>;
1252                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1253                         clocks = <&apb0_gates 1>, <&spdif_clk>;
1254                         clock-names = "apb", "spdif";
1255                         dmas = <&dma SUN4I_DMA_NORMAL 2>,
1256                                <&dma SUN4I_DMA_NORMAL 2>;
1257                         dma-names = "rx", "tx";
1258                         status = "disabled";
1259                 };
1260
1261                 ir0: ir@01c21800 {
1262                         compatible = "allwinner,sun4i-a10-ir";
1263                         clocks = <&apb0_gates 6>, <&ir0_clk>;
1264                         clock-names = "apb", "ir";
1265                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1266                         reg = <0x01c21800 0x40>;
1267                         status = "disabled";
1268                 };
1269
1270                 ir1: ir@01c21c00 {
1271                         compatible = "allwinner,sun4i-a10-ir";
1272                         clocks = <&apb0_gates 7>, <&ir1_clk>;
1273                         clock-names = "apb", "ir";
1274                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1275                         reg = <0x01c21c00 0x40>;
1276                         status = "disabled";
1277                 };
1278
1279                 lradc: lradc@01c22800 {
1280                         compatible = "allwinner,sun4i-a10-lradc-keys";
1281                         reg = <0x01c22800 0x100>;
1282                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1283                         status = "disabled";
1284                 };
1285
1286                 codec: codec@01c22c00 {
1287                         #sound-dai-cells = <0>;
1288                         compatible = "allwinner,sun7i-a20-codec";
1289                         reg = <0x01c22c00 0x40>;
1290                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1291                         clocks = <&apb0_gates 0>, <&codec_clk>;
1292                         clock-names = "apb", "codec";
1293                         dmas = <&dma SUN4I_DMA_NORMAL 19>,
1294                                <&dma SUN4I_DMA_NORMAL 19>;
1295                         dma-names = "rx", "tx";
1296                         status = "disabled";
1297                 };
1298
1299                 sid: eeprom@01c23800 {
1300                         compatible = "allwinner,sun7i-a20-sid";
1301                         reg = <0x01c23800 0x200>;
1302                 };
1303
1304                 rtp: rtp@01c25000 {
1305                         compatible = "allwinner,sun5i-a13-ts";
1306                         reg = <0x01c25000 0x100>;
1307                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1308                         #thermal-sensor-cells = <0>;
1309                 };
1310
1311                 uart0: serial@01c28000 {
1312                         compatible = "snps,dw-apb-uart";
1313                         reg = <0x01c28000 0x400>;
1314                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1315                         reg-shift = <2>;
1316                         reg-io-width = <4>;
1317                         clocks = <&apb1_gates 16>;
1318                         status = "disabled";
1319                 };
1320
1321                 uart1: serial@01c28400 {
1322                         compatible = "snps,dw-apb-uart";
1323                         reg = <0x01c28400 0x400>;
1324                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1325                         reg-shift = <2>;
1326                         reg-io-width = <4>;
1327                         clocks = <&apb1_gates 17>;
1328                         status = "disabled";
1329                 };
1330
1331                 uart2: serial@01c28800 {
1332                         compatible = "snps,dw-apb-uart";
1333                         reg = <0x01c28800 0x400>;
1334                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1335                         reg-shift = <2>;
1336                         reg-io-width = <4>;
1337                         clocks = <&apb1_gates 18>;
1338                         status = "disabled";
1339                 };
1340
1341                 uart3: serial@01c28c00 {
1342                         compatible = "snps,dw-apb-uart";
1343                         reg = <0x01c28c00 0x400>;
1344                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1345                         reg-shift = <2>;
1346                         reg-io-width = <4>;
1347                         clocks = <&apb1_gates 19>;
1348                         status = "disabled";
1349                 };
1350
1351                 uart4: serial@01c29000 {
1352                         compatible = "snps,dw-apb-uart";
1353                         reg = <0x01c29000 0x400>;
1354                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1355                         reg-shift = <2>;
1356                         reg-io-width = <4>;
1357                         clocks = <&apb1_gates 20>;
1358                         status = "disabled";
1359                 };
1360
1361                 uart5: serial@01c29400 {
1362                         compatible = "snps,dw-apb-uart";
1363                         reg = <0x01c29400 0x400>;
1364                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1365                         reg-shift = <2>;
1366                         reg-io-width = <4>;
1367                         clocks = <&apb1_gates 21>;
1368                         status = "disabled";
1369                 };
1370
1371                 uart6: serial@01c29800 {
1372                         compatible = "snps,dw-apb-uart";
1373                         reg = <0x01c29800 0x400>;
1374                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1375                         reg-shift = <2>;
1376                         reg-io-width = <4>;
1377                         clocks = <&apb1_gates 22>;
1378                         status = "disabled";
1379                 };
1380
1381                 uart7: serial@01c29c00 {
1382                         compatible = "snps,dw-apb-uart";
1383                         reg = <0x01c29c00 0x400>;
1384                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1385                         reg-shift = <2>;
1386                         reg-io-width = <4>;
1387                         clocks = <&apb1_gates 23>;
1388                         status = "disabled";
1389                 };
1390
1391                 i2c0: i2c@01c2ac00 {
1392                         compatible = "allwinner,sun7i-a20-i2c",
1393                                      "allwinner,sun4i-a10-i2c";
1394                         reg = <0x01c2ac00 0x400>;
1395                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1396                         clocks = <&apb1_gates 0>;
1397                         status = "disabled";
1398                         #address-cells = <1>;
1399                         #size-cells = <0>;
1400                 };
1401
1402                 i2c1: i2c@01c2b000 {
1403                         compatible = "allwinner,sun7i-a20-i2c",
1404                                      "allwinner,sun4i-a10-i2c";
1405                         reg = <0x01c2b000 0x400>;
1406                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1407                         clocks = <&apb1_gates 1>;
1408                         status = "disabled";
1409                         #address-cells = <1>;
1410                         #size-cells = <0>;
1411                 };
1412
1413                 i2c2: i2c@01c2b400 {
1414                         compatible = "allwinner,sun7i-a20-i2c",
1415                                      "allwinner,sun4i-a10-i2c";
1416                         reg = <0x01c2b400 0x400>;
1417                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1418                         clocks = <&apb1_gates 2>;
1419                         status = "disabled";
1420                         #address-cells = <1>;
1421                         #size-cells = <0>;
1422                 };
1423
1424                 i2c3: i2c@01c2b800 {
1425                         compatible = "allwinner,sun7i-a20-i2c",
1426                                      "allwinner,sun4i-a10-i2c";
1427                         reg = <0x01c2b800 0x400>;
1428                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1429                         clocks = <&apb1_gates 3>;
1430                         status = "disabled";
1431                         #address-cells = <1>;
1432                         #size-cells = <0>;
1433                 };
1434
1435                 i2c4: i2c@01c2c000 {
1436                         compatible = "allwinner,sun7i-a20-i2c",
1437                                      "allwinner,sun4i-a10-i2c";
1438                         reg = <0x01c2c000 0x400>;
1439                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1440                         clocks = <&apb1_gates 15>;
1441                         status = "disabled";
1442                         #address-cells = <1>;
1443                         #size-cells = <0>;
1444                 };
1445
1446                 gmac: ethernet@01c50000 {
1447                         compatible = "allwinner,sun7i-a20-gmac";
1448                         reg = <0x01c50000 0x10000>;
1449                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1450                         interrupt-names = "macirq";
1451                         clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
1452                         clock-names = "stmmaceth", "allwinner_gmac_tx";
1453                         snps,pbl = <2>;
1454                         snps,fixed-burst;
1455                         snps,force_sf_dma_mode;
1456                         status = "disabled";
1457                         #address-cells = <1>;
1458                         #size-cells = <0>;
1459                 };
1460
1461                 hstimer@01c60000 {
1462                         compatible = "allwinner,sun7i-a20-hstimer";
1463                         reg = <0x01c60000 0x1000>;
1464                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1465                                      <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1466                                      <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1467                                      <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1468                         clocks = <&ahb_gates 28>;
1469                 };
1470
1471                 gic: interrupt-controller@01c81000 {
1472                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1473                         reg = <0x01c81000 0x1000>,
1474                               <0x01c82000 0x1000>,
1475                               <0x01c84000 0x2000>,
1476                               <0x01c86000 0x2000>;
1477                         interrupt-controller;
1478                         #interrupt-cells = <3>;
1479                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1480                 };
1481
1482                 ps20: ps2@01c2a000 {
1483                         compatible = "allwinner,sun4i-a10-ps2";
1484                         reg = <0x01c2a000 0x400>;
1485                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1486                         clocks = <&apb1_gates 6>;
1487                         status = "disabled";
1488                 };
1489
1490                 ps21: ps2@01c2a400 {
1491                         compatible = "allwinner,sun4i-a10-ps2";
1492                         reg = <0x01c2a400 0x400>;
1493                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1494                         clocks = <&apb1_gates 7>;
1495                         status = "disabled";
1496                 };
1497         };
1498 };