2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 /include/ "skeleton.dtsi"
17 interrupt-parent = <&gic>;
36 compatible = "arm,cortex-a7";
42 compatible = "arm,cortex-a7";
49 reg = <0x40000000 0x80000000>;
53 compatible = "arm,armv7-timer";
54 interrupts = <1 13 0xf08>,
65 osc24M: clk@01c20050 {
67 compatible = "allwinner,sun4i-a10-osc-clk";
68 reg = <0x01c20050 0x4>;
69 clock-frequency = <24000000>;
70 clock-output-names = "osc24M";
75 compatible = "fixed-clock";
76 clock-frequency = <32768>;
77 clock-output-names = "osc32k";
82 compatible = "allwinner,sun4i-a10-pll1-clk";
83 reg = <0x01c20000 0x4>;
85 clock-output-names = "pll1";
90 compatible = "allwinner,sun7i-a20-pll4-clk";
91 reg = <0x01c20018 0x4>;
93 clock-output-names = "pll4";
98 compatible = "allwinner,sun4i-a10-pll5-clk";
99 reg = <0x01c20020 0x4>;
101 clock-output-names = "pll5_ddr", "pll5_other";
106 compatible = "allwinner,sun4i-a10-pll6-clk";
107 reg = <0x01c20028 0x4>;
109 clock-output-names = "pll6_sata", "pll6_other", "pll6";
114 compatible = "allwinner,sun7i-a20-pll4-clk";
115 reg = <0x01c20040 0x4>;
117 clock-output-names = "pll8";
122 compatible = "allwinner,sun4i-a10-cpu-clk";
123 reg = <0x01c20054 0x4>;
124 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
125 clock-output-names = "cpu";
130 compatible = "allwinner,sun4i-a10-axi-clk";
131 reg = <0x01c20054 0x4>;
133 clock-output-names = "axi";
138 compatible = "allwinner,sun4i-a10-ahb-clk";
139 reg = <0x01c20054 0x4>;
141 clock-output-names = "ahb";
144 ahb_gates: clk@01c20060 {
146 compatible = "allwinner,sun7i-a20-ahb-gates-clk";
147 reg = <0x01c20060 0x8>;
149 clock-output-names = "ahb_usb0", "ahb_ehci0",
150 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
151 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
152 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
153 "ahb_nand", "ahb_sdram", "ahb_ace",
154 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
155 "ahb_spi2", "ahb_spi3", "ahb_sata",
156 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
157 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
158 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
159 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
160 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
164 apb0: apb0@01c20054 {
166 compatible = "allwinner,sun4i-a10-apb0-clk";
167 reg = <0x01c20054 0x4>;
169 clock-output-names = "apb0";
172 apb0_gates: clk@01c20068 {
174 compatible = "allwinner,sun7i-a20-apb0-gates-clk";
175 reg = <0x01c20068 0x4>;
177 clock-output-names = "apb0_codec", "apb0_spdif",
178 "apb0_ac97", "apb0_iis0", "apb0_iis1",
179 "apb0_pio", "apb0_ir0", "apb0_ir1",
180 "apb0_iis2", "apb0_keypad";
183 apb1_mux: apb1_mux@01c20058 {
185 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
186 reg = <0x01c20058 0x4>;
187 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
188 clock-output-names = "apb1_mux";
191 apb1: apb1@01c20058 {
193 compatible = "allwinner,sun4i-a10-apb1-clk";
194 reg = <0x01c20058 0x4>;
195 clocks = <&apb1_mux>;
196 clock-output-names = "apb1";
199 apb1_gates: clk@01c2006c {
201 compatible = "allwinner,sun7i-a20-apb1-gates-clk";
202 reg = <0x01c2006c 0x4>;
204 clock-output-names = "apb1_i2c0", "apb1_i2c1",
205 "apb1_i2c2", "apb1_i2c3", "apb1_can",
206 "apb1_scr", "apb1_ps20", "apb1_ps21",
207 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
208 "apb1_uart2", "apb1_uart3", "apb1_uart4",
209 "apb1_uart5", "apb1_uart6", "apb1_uart7";
212 nand_clk: clk@01c20080 {
214 compatible = "allwinner,sun4i-a10-mod0-clk";
215 reg = <0x01c20080 0x4>;
216 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
217 clock-output-names = "nand";
220 ms_clk: clk@01c20084 {
222 compatible = "allwinner,sun4i-a10-mod0-clk";
223 reg = <0x01c20084 0x4>;
224 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
225 clock-output-names = "ms";
228 mmc0_clk: clk@01c20088 {
230 compatible = "allwinner,sun4i-a10-mod0-clk";
231 reg = <0x01c20088 0x4>;
232 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
233 clock-output-names = "mmc0";
236 mmc1_clk: clk@01c2008c {
238 compatible = "allwinner,sun4i-a10-mod0-clk";
239 reg = <0x01c2008c 0x4>;
240 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
241 clock-output-names = "mmc1";
244 mmc2_clk: clk@01c20090 {
246 compatible = "allwinner,sun4i-a10-mod0-clk";
247 reg = <0x01c20090 0x4>;
248 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
249 clock-output-names = "mmc2";
252 mmc3_clk: clk@01c20094 {
254 compatible = "allwinner,sun4i-a10-mod0-clk";
255 reg = <0x01c20094 0x4>;
256 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
257 clock-output-names = "mmc3";
260 ts_clk: clk@01c20098 {
262 compatible = "allwinner,sun4i-a10-mod0-clk";
263 reg = <0x01c20098 0x4>;
264 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
265 clock-output-names = "ts";
268 ss_clk: clk@01c2009c {
270 compatible = "allwinner,sun4i-a10-mod0-clk";
271 reg = <0x01c2009c 0x4>;
272 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
273 clock-output-names = "ss";
276 spi0_clk: clk@01c200a0 {
278 compatible = "allwinner,sun4i-a10-mod0-clk";
279 reg = <0x01c200a0 0x4>;
280 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
281 clock-output-names = "spi0";
284 spi1_clk: clk@01c200a4 {
286 compatible = "allwinner,sun4i-a10-mod0-clk";
287 reg = <0x01c200a4 0x4>;
288 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
289 clock-output-names = "spi1";
292 spi2_clk: clk@01c200a8 {
294 compatible = "allwinner,sun4i-a10-mod0-clk";
295 reg = <0x01c200a8 0x4>;
296 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
297 clock-output-names = "spi2";
300 pata_clk: clk@01c200ac {
302 compatible = "allwinner,sun4i-a10-mod0-clk";
303 reg = <0x01c200ac 0x4>;
304 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
305 clock-output-names = "pata";
308 ir0_clk: clk@01c200b0 {
310 compatible = "allwinner,sun4i-a10-mod0-clk";
311 reg = <0x01c200b0 0x4>;
312 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
313 clock-output-names = "ir0";
316 ir1_clk: clk@01c200b4 {
318 compatible = "allwinner,sun4i-a10-mod0-clk";
319 reg = <0x01c200b4 0x4>;
320 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
321 clock-output-names = "ir1";
324 usb_clk: clk@01c200cc {
327 compatible = "allwinner,sun4i-a10-usb-clk";
328 reg = <0x01c200cc 0x4>;
330 clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
333 spi3_clk: clk@01c200d4 {
335 compatible = "allwinner,sun4i-a10-mod0-clk";
336 reg = <0x01c200d4 0x4>;
337 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
338 clock-output-names = "spi3";
341 mbus_clk: clk@01c2015c {
343 compatible = "allwinner,sun4i-a10-mod0-clk";
344 reg = <0x01c2015c 0x4>;
345 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
346 clock-output-names = "mbus";
350 * The following two are dummy clocks, placeholders used in the gmac_tx
351 * clock. The gmac driver will choose one parent depending on the PHY
352 * interface mode, using clk_set_rate auto-reparenting.
353 * The actual TX clock rate is not controlled by the gmac_tx clock.
355 mii_phy_tx_clk: clk@2 {
357 compatible = "fixed-clock";
358 clock-frequency = <25000000>;
359 clock-output-names = "mii_phy_tx";
362 gmac_int_tx_clk: clk@3 {
364 compatible = "fixed-clock";
365 clock-frequency = <125000000>;
366 clock-output-names = "gmac_int_tx";
369 gmac_tx_clk: clk@01c20164 {
371 compatible = "allwinner,sun7i-a20-gmac-clk";
372 reg = <0x01c20164 0x4>;
373 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
374 clock-output-names = "gmac_tx";
378 * Dummy clock used by output clocks
382 compatible = "fixed-factor-clock";
386 clock-output-names = "osc24M_32k";
389 clk_out_a: clk@01c201f0 {
391 compatible = "allwinner,sun7i-a20-out-clk";
392 reg = <0x01c201f0 0x4>;
393 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
394 clock-output-names = "clk_out_a";
397 clk_out_b: clk@01c201f4 {
399 compatible = "allwinner,sun7i-a20-out-clk";
400 reg = <0x01c201f4 0x4>;
401 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
402 clock-output-names = "clk_out_b";
407 compatible = "simple-bus";
408 #address-cells = <1>;
412 nmi_intc: interrupt-controller@01c00030 {
413 compatible = "allwinner,sun7i-a20-sc-nmi";
414 interrupt-controller;
415 #interrupt-cells = <2>;
416 reg = <0x01c00030 0x0c>;
417 interrupts = <0 0 4>;
421 compatible = "allwinner,sun4i-a10-spi";
422 reg = <0x01c05000 0x1000>;
423 interrupts = <0 10 4>;
424 clocks = <&ahb_gates 20>, <&spi0_clk>;
425 clock-names = "ahb", "mod";
427 #address-cells = <1>;
432 compatible = "allwinner,sun4i-a10-spi";
433 reg = <0x01c06000 0x1000>;
434 interrupts = <0 11 4>;
435 clocks = <&ahb_gates 21>, <&spi1_clk>;
436 clock-names = "ahb", "mod";
438 #address-cells = <1>;
442 emac: ethernet@01c0b000 {
443 compatible = "allwinner,sun4i-a10-emac";
444 reg = <0x01c0b000 0x1000>;
445 interrupts = <0 55 4>;
446 clocks = <&ahb_gates 17>;
451 compatible = "allwinner,sun4i-a10-mdio";
452 reg = <0x01c0b080 0x14>;
454 #address-cells = <1>;
458 usbphy: phy@01c13400 {
460 compatible = "allwinner,sun7i-a20-usb-phy";
461 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
462 reg-names = "phy_ctrl", "pmu1", "pmu2";
463 clocks = <&usb_clk 8>;
464 clock-names = "usb_phy";
465 resets = <&usb_clk 1>, <&usb_clk 2>;
466 reset-names = "usb1_reset", "usb2_reset";
470 ehci0: usb@01c14000 {
471 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
472 reg = <0x01c14000 0x100>;
473 interrupts = <0 39 4>;
474 clocks = <&ahb_gates 1>;
480 ohci0: usb@01c14400 {
481 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
482 reg = <0x01c14400 0x100>;
483 interrupts = <0 64 4>;
484 clocks = <&usb_clk 6>, <&ahb_gates 2>;
491 compatible = "allwinner,sun4i-a10-spi";
492 reg = <0x01c17000 0x1000>;
493 interrupts = <0 12 4>;
494 clocks = <&ahb_gates 22>, <&spi2_clk>;
495 clock-names = "ahb", "mod";
497 #address-cells = <1>;
501 ahci: sata@01c18000 {
502 compatible = "allwinner,sun4i-a10-ahci";
503 reg = <0x01c18000 0x1000>;
504 interrupts = <0 56 4>;
505 clocks = <&pll6 0>, <&ahb_gates 25>;
509 ehci1: usb@01c1c000 {
510 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
511 reg = <0x01c1c000 0x100>;
512 interrupts = <0 40 4>;
513 clocks = <&ahb_gates 3>;
519 ohci1: usb@01c1c400 {
520 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
521 reg = <0x01c1c400 0x100>;
522 interrupts = <0 65 4>;
523 clocks = <&usb_clk 7>, <&ahb_gates 4>;
530 compatible = "allwinner,sun4i-a10-spi";
531 reg = <0x01c1f000 0x1000>;
532 interrupts = <0 50 4>;
533 clocks = <&ahb_gates 23>, <&spi3_clk>;
534 clock-names = "ahb", "mod";
536 #address-cells = <1>;
540 pio: pinctrl@01c20800 {
541 compatible = "allwinner,sun7i-a20-pinctrl";
542 reg = <0x01c20800 0x400>;
543 interrupts = <0 28 4>;
544 clocks = <&apb0_gates 5>;
546 interrupt-controller;
547 #address-cells = <1>;
551 uart0_pins_a: uart0@0 {
552 allwinner,pins = "PB22", "PB23";
553 allwinner,function = "uart0";
554 allwinner,drive = <0>;
555 allwinner,pull = <0>;
558 uart2_pins_a: uart2@0 {
559 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
560 allwinner,function = "uart2";
561 allwinner,drive = <0>;
562 allwinner,pull = <0>;
565 uart6_pins_a: uart6@0 {
566 allwinner,pins = "PI12", "PI13";
567 allwinner,function = "uart6";
568 allwinner,drive = <0>;
569 allwinner,pull = <0>;
572 uart7_pins_a: uart7@0 {
573 allwinner,pins = "PI20", "PI21";
574 allwinner,function = "uart7";
575 allwinner,drive = <0>;
576 allwinner,pull = <0>;
579 i2c0_pins_a: i2c0@0 {
580 allwinner,pins = "PB0", "PB1";
581 allwinner,function = "i2c0";
582 allwinner,drive = <0>;
583 allwinner,pull = <0>;
586 i2c1_pins_a: i2c1@0 {
587 allwinner,pins = "PB18", "PB19";
588 allwinner,function = "i2c1";
589 allwinner,drive = <0>;
590 allwinner,pull = <0>;
593 i2c2_pins_a: i2c2@0 {
594 allwinner,pins = "PB20", "PB21";
595 allwinner,function = "i2c2";
596 allwinner,drive = <0>;
597 allwinner,pull = <0>;
600 emac_pins_a: emac0@0 {
601 allwinner,pins = "PA0", "PA1", "PA2",
602 "PA3", "PA4", "PA5", "PA6",
603 "PA7", "PA8", "PA9", "PA10",
604 "PA11", "PA12", "PA13", "PA14",
606 allwinner,function = "emac";
607 allwinner,drive = <0>;
608 allwinner,pull = <0>;
611 clk_out_a_pins_a: clk_out_a@0 {
612 allwinner,pins = "PI12";
613 allwinner,function = "clk_out_a";
614 allwinner,drive = <0>;
615 allwinner,pull = <0>;
618 clk_out_b_pins_a: clk_out_b@0 {
619 allwinner,pins = "PI13";
620 allwinner,function = "clk_out_b";
621 allwinner,drive = <0>;
622 allwinner,pull = <0>;
625 gmac_pins_mii_a: gmac_mii@0 {
626 allwinner,pins = "PA0", "PA1", "PA2",
627 "PA3", "PA4", "PA5", "PA6",
628 "PA7", "PA8", "PA9", "PA10",
629 "PA11", "PA12", "PA13", "PA14",
631 allwinner,function = "gmac";
632 allwinner,drive = <0>;
633 allwinner,pull = <0>;
636 gmac_pins_rgmii_a: gmac_rgmii@0 {
637 allwinner,pins = "PA0", "PA1", "PA2",
638 "PA3", "PA4", "PA5", "PA6",
639 "PA7", "PA8", "PA10",
640 "PA11", "PA12", "PA13",
642 allwinner,function = "gmac";
644 * data lines in RGMII mode use DDR mode
645 * and need a higher signal drive strength
647 allwinner,drive = <3>;
648 allwinner,pull = <0>;
651 spi1_pins_a: spi1@0 {
652 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
653 allwinner,function = "spi1";
654 allwinner,drive = <0>;
655 allwinner,pull = <0>;
658 spi2_pins_a: spi2@0 {
659 allwinner,pins = "PC19", "PC20", "PC21", "PC22";
660 allwinner,function = "spi2";
661 allwinner,drive = <0>;
662 allwinner,pull = <0>;
667 compatible = "allwinner,sun4i-a10-timer";
668 reg = <0x01c20c00 0x90>;
669 interrupts = <0 22 4>,
678 wdt: watchdog@01c20c90 {
679 compatible = "allwinner,sun4i-a10-wdt";
680 reg = <0x01c20c90 0x10>;
684 compatible = "allwinner,sun7i-a20-rtc";
685 reg = <0x01c20d00 0x20>;
686 interrupts = <0 24 4>;
689 sid: eeprom@01c23800 {
690 compatible = "allwinner,sun7i-a20-sid";
691 reg = <0x01c23800 0x200>;
695 compatible = "allwinner,sun4i-a10-ts";
696 reg = <0x01c25000 0x100>;
697 interrupts = <0 29 4>;
700 uart0: serial@01c28000 {
701 compatible = "snps,dw-apb-uart";
702 reg = <0x01c28000 0x400>;
703 interrupts = <0 1 4>;
706 clocks = <&apb1_gates 16>;
710 uart1: serial@01c28400 {
711 compatible = "snps,dw-apb-uart";
712 reg = <0x01c28400 0x400>;
713 interrupts = <0 2 4>;
716 clocks = <&apb1_gates 17>;
720 uart2: serial@01c28800 {
721 compatible = "snps,dw-apb-uart";
722 reg = <0x01c28800 0x400>;
723 interrupts = <0 3 4>;
726 clocks = <&apb1_gates 18>;
730 uart3: serial@01c28c00 {
731 compatible = "snps,dw-apb-uart";
732 reg = <0x01c28c00 0x400>;
733 interrupts = <0 4 4>;
736 clocks = <&apb1_gates 19>;
740 uart4: serial@01c29000 {
741 compatible = "snps,dw-apb-uart";
742 reg = <0x01c29000 0x400>;
743 interrupts = <0 17 4>;
746 clocks = <&apb1_gates 20>;
750 uart5: serial@01c29400 {
751 compatible = "snps,dw-apb-uart";
752 reg = <0x01c29400 0x400>;
753 interrupts = <0 18 4>;
756 clocks = <&apb1_gates 21>;
760 uart6: serial@01c29800 {
761 compatible = "snps,dw-apb-uart";
762 reg = <0x01c29800 0x400>;
763 interrupts = <0 19 4>;
766 clocks = <&apb1_gates 22>;
770 uart7: serial@01c29c00 {
771 compatible = "snps,dw-apb-uart";
772 reg = <0x01c29c00 0x400>;
773 interrupts = <0 20 4>;
776 clocks = <&apb1_gates 23>;
781 compatible = "allwinner,sun4i-i2c";
782 reg = <0x01c2ac00 0x400>;
783 interrupts = <0 7 4>;
784 clocks = <&apb1_gates 0>;
785 clock-frequency = <100000>;
790 compatible = "allwinner,sun4i-i2c";
791 reg = <0x01c2b000 0x400>;
792 interrupts = <0 8 4>;
793 clocks = <&apb1_gates 1>;
794 clock-frequency = <100000>;
799 compatible = "allwinner,sun4i-i2c";
800 reg = <0x01c2b400 0x400>;
801 interrupts = <0 9 4>;
802 clocks = <&apb1_gates 2>;
803 clock-frequency = <100000>;
808 compatible = "allwinner,sun4i-i2c";
809 reg = <0x01c2b800 0x400>;
810 interrupts = <0 88 4>;
811 clocks = <&apb1_gates 3>;
812 clock-frequency = <100000>;
817 compatible = "allwinner,sun4i-i2c";
818 reg = <0x01c2bc00 0x400>;
819 interrupts = <0 89 4>;
820 clocks = <&apb1_gates 15>;
821 clock-frequency = <100000>;
825 gmac: ethernet@01c50000 {
826 compatible = "allwinner,sun7i-a20-gmac";
827 reg = <0x01c50000 0x10000>;
828 interrupts = <0 85 4>;
829 interrupt-names = "macirq";
830 clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
831 clock-names = "stmmaceth", "allwinner_gmac_tx";
834 snps,force_sf_dma_mode;
836 #address-cells = <1>;
841 compatible = "allwinner,sun7i-a20-hstimer";
842 reg = <0x01c60000 0x1000>;
843 interrupts = <0 81 4>,
847 clocks = <&ahb_gates 28>;
850 gic: interrupt-controller@01c81000 {
851 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
852 reg = <0x01c81000 0x1000>,
856 interrupt-controller;
857 #interrupt-cells = <3>;
858 interrupts = <1 9 0xf04>;