2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 /include/ "skeleton.dtsi"
17 interrupt-parent = <&gic>;
36 compatible = "arm,cortex-a7";
42 compatible = "arm,cortex-a7";
49 reg = <0x40000000 0x80000000>;
53 compatible = "arm,armv7-timer";
54 interrupts = <1 13 0xf08>,
61 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
62 interrupts = <0 120 4>,
71 osc24M: clk@01c20050 {
73 compatible = "allwinner,sun4i-a10-osc-clk";
74 reg = <0x01c20050 0x4>;
75 clock-frequency = <24000000>;
76 clock-output-names = "osc24M";
81 compatible = "fixed-clock";
82 clock-frequency = <32768>;
83 clock-output-names = "osc32k";
88 compatible = "allwinner,sun4i-a10-pll1-clk";
89 reg = <0x01c20000 0x4>;
91 clock-output-names = "pll1";
96 compatible = "allwinner,sun7i-a20-pll4-clk";
97 reg = <0x01c20018 0x4>;
99 clock-output-names = "pll4";
104 compatible = "allwinner,sun4i-a10-pll5-clk";
105 reg = <0x01c20020 0x4>;
107 clock-output-names = "pll5_ddr", "pll5_other";
112 compatible = "allwinner,sun4i-a10-pll6-clk";
113 reg = <0x01c20028 0x4>;
115 clock-output-names = "pll6_sata", "pll6_other", "pll6";
120 compatible = "allwinner,sun7i-a20-pll4-clk";
121 reg = <0x01c20040 0x4>;
123 clock-output-names = "pll8";
128 compatible = "allwinner,sun4i-a10-cpu-clk";
129 reg = <0x01c20054 0x4>;
130 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
131 clock-output-names = "cpu";
136 compatible = "allwinner,sun4i-a10-axi-clk";
137 reg = <0x01c20054 0x4>;
139 clock-output-names = "axi";
144 compatible = "allwinner,sun4i-a10-ahb-clk";
145 reg = <0x01c20054 0x4>;
147 clock-output-names = "ahb";
150 ahb_gates: clk@01c20060 {
152 compatible = "allwinner,sun7i-a20-ahb-gates-clk";
153 reg = <0x01c20060 0x8>;
155 clock-output-names = "ahb_usb0", "ahb_ehci0",
156 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
157 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
158 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
159 "ahb_nand", "ahb_sdram", "ahb_ace",
160 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
161 "ahb_spi2", "ahb_spi3", "ahb_sata",
162 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
163 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
164 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
165 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
166 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
170 apb0: apb0@01c20054 {
172 compatible = "allwinner,sun4i-a10-apb0-clk";
173 reg = <0x01c20054 0x4>;
175 clock-output-names = "apb0";
178 apb0_gates: clk@01c20068 {
180 compatible = "allwinner,sun7i-a20-apb0-gates-clk";
181 reg = <0x01c20068 0x4>;
183 clock-output-names = "apb0_codec", "apb0_spdif",
184 "apb0_ac97", "apb0_iis0", "apb0_iis1",
185 "apb0_pio", "apb0_ir0", "apb0_ir1",
186 "apb0_iis2", "apb0_keypad";
189 apb1_mux: apb1_mux@01c20058 {
191 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
192 reg = <0x01c20058 0x4>;
193 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
194 clock-output-names = "apb1_mux";
197 apb1: apb1@01c20058 {
199 compatible = "allwinner,sun4i-a10-apb1-clk";
200 reg = <0x01c20058 0x4>;
201 clocks = <&apb1_mux>;
202 clock-output-names = "apb1";
205 apb1_gates: clk@01c2006c {
207 compatible = "allwinner,sun7i-a20-apb1-gates-clk";
208 reg = <0x01c2006c 0x4>;
210 clock-output-names = "apb1_i2c0", "apb1_i2c1",
211 "apb1_i2c2", "apb1_i2c3", "apb1_can",
212 "apb1_scr", "apb1_ps20", "apb1_ps21",
213 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
214 "apb1_uart2", "apb1_uart3", "apb1_uart4",
215 "apb1_uart5", "apb1_uart6", "apb1_uart7";
218 nand_clk: clk@01c20080 {
220 compatible = "allwinner,sun4i-a10-mod0-clk";
221 reg = <0x01c20080 0x4>;
222 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
223 clock-output-names = "nand";
226 ms_clk: clk@01c20084 {
228 compatible = "allwinner,sun4i-a10-mod0-clk";
229 reg = <0x01c20084 0x4>;
230 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
231 clock-output-names = "ms";
234 mmc0_clk: clk@01c20088 {
236 compatible = "allwinner,sun4i-a10-mod0-clk";
237 reg = <0x01c20088 0x4>;
238 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
239 clock-output-names = "mmc0";
242 mmc1_clk: clk@01c2008c {
244 compatible = "allwinner,sun4i-a10-mod0-clk";
245 reg = <0x01c2008c 0x4>;
246 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
247 clock-output-names = "mmc1";
250 mmc2_clk: clk@01c20090 {
252 compatible = "allwinner,sun4i-a10-mod0-clk";
253 reg = <0x01c20090 0x4>;
254 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
255 clock-output-names = "mmc2";
258 mmc3_clk: clk@01c20094 {
260 compatible = "allwinner,sun4i-a10-mod0-clk";
261 reg = <0x01c20094 0x4>;
262 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
263 clock-output-names = "mmc3";
266 ts_clk: clk@01c20098 {
268 compatible = "allwinner,sun4i-a10-mod0-clk";
269 reg = <0x01c20098 0x4>;
270 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
271 clock-output-names = "ts";
274 ss_clk: clk@01c2009c {
276 compatible = "allwinner,sun4i-a10-mod0-clk";
277 reg = <0x01c2009c 0x4>;
278 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
279 clock-output-names = "ss";
282 spi0_clk: clk@01c200a0 {
284 compatible = "allwinner,sun4i-a10-mod0-clk";
285 reg = <0x01c200a0 0x4>;
286 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
287 clock-output-names = "spi0";
290 spi1_clk: clk@01c200a4 {
292 compatible = "allwinner,sun4i-a10-mod0-clk";
293 reg = <0x01c200a4 0x4>;
294 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
295 clock-output-names = "spi1";
298 spi2_clk: clk@01c200a8 {
300 compatible = "allwinner,sun4i-a10-mod0-clk";
301 reg = <0x01c200a8 0x4>;
302 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
303 clock-output-names = "spi2";
306 pata_clk: clk@01c200ac {
308 compatible = "allwinner,sun4i-a10-mod0-clk";
309 reg = <0x01c200ac 0x4>;
310 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
311 clock-output-names = "pata";
314 ir0_clk: clk@01c200b0 {
316 compatible = "allwinner,sun4i-a10-mod0-clk";
317 reg = <0x01c200b0 0x4>;
318 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
319 clock-output-names = "ir0";
322 ir1_clk: clk@01c200b4 {
324 compatible = "allwinner,sun4i-a10-mod0-clk";
325 reg = <0x01c200b4 0x4>;
326 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
327 clock-output-names = "ir1";
330 usb_clk: clk@01c200cc {
333 compatible = "allwinner,sun4i-a10-usb-clk";
334 reg = <0x01c200cc 0x4>;
336 clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
339 spi3_clk: clk@01c200d4 {
341 compatible = "allwinner,sun4i-a10-mod0-clk";
342 reg = <0x01c200d4 0x4>;
343 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
344 clock-output-names = "spi3";
347 mbus_clk: clk@01c2015c {
349 compatible = "allwinner,sun4i-a10-mod0-clk";
350 reg = <0x01c2015c 0x4>;
351 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
352 clock-output-names = "mbus";
356 * The following two are dummy clocks, placeholders used in the gmac_tx
357 * clock. The gmac driver will choose one parent depending on the PHY
358 * interface mode, using clk_set_rate auto-reparenting.
359 * The actual TX clock rate is not controlled by the gmac_tx clock.
361 mii_phy_tx_clk: clk@2 {
363 compatible = "fixed-clock";
364 clock-frequency = <25000000>;
365 clock-output-names = "mii_phy_tx";
368 gmac_int_tx_clk: clk@3 {
370 compatible = "fixed-clock";
371 clock-frequency = <125000000>;
372 clock-output-names = "gmac_int_tx";
375 gmac_tx_clk: clk@01c20164 {
377 compatible = "allwinner,sun7i-a20-gmac-clk";
378 reg = <0x01c20164 0x4>;
379 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
380 clock-output-names = "gmac_tx";
384 * Dummy clock used by output clocks
388 compatible = "fixed-factor-clock";
392 clock-output-names = "osc24M_32k";
395 clk_out_a: clk@01c201f0 {
397 compatible = "allwinner,sun7i-a20-out-clk";
398 reg = <0x01c201f0 0x4>;
399 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
400 clock-output-names = "clk_out_a";
403 clk_out_b: clk@01c201f4 {
405 compatible = "allwinner,sun7i-a20-out-clk";
406 reg = <0x01c201f4 0x4>;
407 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
408 clock-output-names = "clk_out_b";
413 compatible = "simple-bus";
414 #address-cells = <1>;
418 nmi_intc: interrupt-controller@01c00030 {
419 compatible = "allwinner,sun7i-a20-sc-nmi";
420 interrupt-controller;
421 #interrupt-cells = <2>;
422 reg = <0x01c00030 0x0c>;
423 interrupts = <0 0 4>;
426 dma: dma-controller@01c02000 {
427 compatible = "allwinner,sun4i-a10-dma";
428 reg = <0x01c02000 0x1000>;
429 interrupts = <0 27 4>;
430 clocks = <&ahb_gates 6>;
435 compatible = "allwinner,sun4i-a10-spi";
436 reg = <0x01c05000 0x1000>;
437 interrupts = <0 10 4>;
438 clocks = <&ahb_gates 20>, <&spi0_clk>;
439 clock-names = "ahb", "mod";
440 dmas = <&dma 1 27>, <&dma 1 26>;
441 dma-names = "rx", "tx";
443 #address-cells = <1>;
448 compatible = "allwinner,sun4i-a10-spi";
449 reg = <0x01c06000 0x1000>;
450 interrupts = <0 11 4>;
451 clocks = <&ahb_gates 21>, <&spi1_clk>;
452 clock-names = "ahb", "mod";
453 dmas = <&dma 1 9>, <&dma 1 8>;
454 dma-names = "rx", "tx";
456 #address-cells = <1>;
460 emac: ethernet@01c0b000 {
461 compatible = "allwinner,sun4i-a10-emac";
462 reg = <0x01c0b000 0x1000>;
463 interrupts = <0 55 4>;
464 clocks = <&ahb_gates 17>;
469 compatible = "allwinner,sun4i-a10-mdio";
470 reg = <0x01c0b080 0x14>;
472 #address-cells = <1>;
477 compatible = "allwinner,sun5i-a13-mmc";
478 reg = <0x01c0f000 0x1000>;
479 clocks = <&ahb_gates 8>, <&mmc0_clk>;
480 clock-names = "ahb", "mmc";
481 interrupts = <0 32 4>;
486 compatible = "allwinner,sun5i-a13-mmc";
487 reg = <0x01c10000 0x1000>;
488 clocks = <&ahb_gates 9>, <&mmc1_clk>;
489 clock-names = "ahb", "mmc";
490 interrupts = <0 33 4>;
495 compatible = "allwinner,sun5i-a13-mmc";
496 reg = <0x01c11000 0x1000>;
497 clocks = <&ahb_gates 10>, <&mmc2_clk>;
498 clock-names = "ahb", "mmc";
499 interrupts = <0 34 4>;
504 compatible = "allwinner,sun5i-a13-mmc";
505 reg = <0x01c12000 0x1000>;
506 clocks = <&ahb_gates 11>, <&mmc3_clk>;
507 clock-names = "ahb", "mmc";
508 interrupts = <0 35 4>;
512 usbphy: phy@01c13400 {
514 compatible = "allwinner,sun7i-a20-usb-phy";
515 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
516 reg-names = "phy_ctrl", "pmu1", "pmu2";
517 clocks = <&usb_clk 8>;
518 clock-names = "usb_phy";
519 resets = <&usb_clk 1>, <&usb_clk 2>;
520 reset-names = "usb1_reset", "usb2_reset";
524 ehci0: usb@01c14000 {
525 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
526 reg = <0x01c14000 0x100>;
527 interrupts = <0 39 4>;
528 clocks = <&ahb_gates 1>;
534 ohci0: usb@01c14400 {
535 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
536 reg = <0x01c14400 0x100>;
537 interrupts = <0 64 4>;
538 clocks = <&usb_clk 6>, <&ahb_gates 2>;
545 compatible = "allwinner,sun4i-a10-spi";
546 reg = <0x01c17000 0x1000>;
547 interrupts = <0 12 4>;
548 clocks = <&ahb_gates 22>, <&spi2_clk>;
549 clock-names = "ahb", "mod";
550 dmas = <&dma 1 29>, <&dma 1 28>;
551 dma-names = "rx", "tx";
553 #address-cells = <1>;
557 ahci: sata@01c18000 {
558 compatible = "allwinner,sun4i-a10-ahci";
559 reg = <0x01c18000 0x1000>;
560 interrupts = <0 56 4>;
561 clocks = <&pll6 0>, <&ahb_gates 25>;
565 ehci1: usb@01c1c000 {
566 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
567 reg = <0x01c1c000 0x100>;
568 interrupts = <0 40 4>;
569 clocks = <&ahb_gates 3>;
575 ohci1: usb@01c1c400 {
576 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
577 reg = <0x01c1c400 0x100>;
578 interrupts = <0 65 4>;
579 clocks = <&usb_clk 7>, <&ahb_gates 4>;
586 compatible = "allwinner,sun4i-a10-spi";
587 reg = <0x01c1f000 0x1000>;
588 interrupts = <0 50 4>;
589 clocks = <&ahb_gates 23>, <&spi3_clk>;
590 clock-names = "ahb", "mod";
591 dmas = <&dma 1 31>, <&dma 1 30>;
592 dma-names = "rx", "tx";
594 #address-cells = <1>;
598 pio: pinctrl@01c20800 {
599 compatible = "allwinner,sun7i-a20-pinctrl";
600 reg = <0x01c20800 0x400>;
601 interrupts = <0 28 4>;
602 clocks = <&apb0_gates 5>;
604 interrupt-controller;
605 #interrupt-cells = <2>;
609 pwm0_pins_a: pwm0@0 {
610 allwinner,pins = "PB2";
611 allwinner,function = "pwm";
612 allwinner,drive = <0>;
613 allwinner,pull = <0>;
616 pwm1_pins_a: pwm1@0 {
617 allwinner,pins = "PI3";
618 allwinner,function = "pwm";
619 allwinner,drive = <0>;
620 allwinner,pull = <0>;
623 uart0_pins_a: uart0@0 {
624 allwinner,pins = "PB22", "PB23";
625 allwinner,function = "uart0";
626 allwinner,drive = <0>;
627 allwinner,pull = <0>;
630 uart2_pins_a: uart2@0 {
631 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
632 allwinner,function = "uart2";
633 allwinner,drive = <0>;
634 allwinner,pull = <0>;
637 uart6_pins_a: uart6@0 {
638 allwinner,pins = "PI12", "PI13";
639 allwinner,function = "uart6";
640 allwinner,drive = <0>;
641 allwinner,pull = <0>;
644 uart7_pins_a: uart7@0 {
645 allwinner,pins = "PI20", "PI21";
646 allwinner,function = "uart7";
647 allwinner,drive = <0>;
648 allwinner,pull = <0>;
651 i2c0_pins_a: i2c0@0 {
652 allwinner,pins = "PB0", "PB1";
653 allwinner,function = "i2c0";
654 allwinner,drive = <0>;
655 allwinner,pull = <0>;
658 i2c1_pins_a: i2c1@0 {
659 allwinner,pins = "PB18", "PB19";
660 allwinner,function = "i2c1";
661 allwinner,drive = <0>;
662 allwinner,pull = <0>;
665 i2c2_pins_a: i2c2@0 {
666 allwinner,pins = "PB20", "PB21";
667 allwinner,function = "i2c2";
668 allwinner,drive = <0>;
669 allwinner,pull = <0>;
672 emac_pins_a: emac0@0 {
673 allwinner,pins = "PA0", "PA1", "PA2",
674 "PA3", "PA4", "PA5", "PA6",
675 "PA7", "PA8", "PA9", "PA10",
676 "PA11", "PA12", "PA13", "PA14",
678 allwinner,function = "emac";
679 allwinner,drive = <0>;
680 allwinner,pull = <0>;
683 clk_out_a_pins_a: clk_out_a@0 {
684 allwinner,pins = "PI12";
685 allwinner,function = "clk_out_a";
686 allwinner,drive = <0>;
687 allwinner,pull = <0>;
690 clk_out_b_pins_a: clk_out_b@0 {
691 allwinner,pins = "PI13";
692 allwinner,function = "clk_out_b";
693 allwinner,drive = <0>;
694 allwinner,pull = <0>;
697 gmac_pins_mii_a: gmac_mii@0 {
698 allwinner,pins = "PA0", "PA1", "PA2",
699 "PA3", "PA4", "PA5", "PA6",
700 "PA7", "PA8", "PA9", "PA10",
701 "PA11", "PA12", "PA13", "PA14",
703 allwinner,function = "gmac";
704 allwinner,drive = <0>;
705 allwinner,pull = <0>;
708 gmac_pins_rgmii_a: gmac_rgmii@0 {
709 allwinner,pins = "PA0", "PA1", "PA2",
710 "PA3", "PA4", "PA5", "PA6",
711 "PA7", "PA8", "PA10",
712 "PA11", "PA12", "PA13",
714 allwinner,function = "gmac";
716 * data lines in RGMII mode use DDR mode
717 * and need a higher signal drive strength
719 allwinner,drive = <3>;
720 allwinner,pull = <0>;
723 spi1_pins_a: spi1@0 {
724 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
725 allwinner,function = "spi1";
726 allwinner,drive = <0>;
727 allwinner,pull = <0>;
730 spi2_pins_a: spi2@0 {
731 allwinner,pins = "PC19", "PC20", "PC21", "PC22";
732 allwinner,function = "spi2";
733 allwinner,drive = <0>;
734 allwinner,pull = <0>;
737 mmc0_pins_a: mmc0@0 {
738 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
739 allwinner,function = "mmc0";
740 allwinner,drive = <2>;
741 allwinner,pull = <0>;
744 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
745 allwinner,pins = "PH1";
746 allwinner,function = "gpio_in";
747 allwinner,drive = <0>;
748 allwinner,pull = <1>;
751 mmc3_pins_a: mmc3@0 {
752 allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
753 allwinner,function = "mmc3";
754 allwinner,drive = <2>;
755 allwinner,pull = <0>;
759 allwinner,pins = "PB3","PB4";
760 allwinner,function = "ir0";
761 allwinner,drive = <0>;
762 allwinner,pull = <0>;
766 allwinner,pins = "PB22","PB23";
767 allwinner,function = "ir1";
768 allwinner,drive = <0>;
769 allwinner,pull = <0>;
774 compatible = "allwinner,sun4i-a10-timer";
775 reg = <0x01c20c00 0x90>;
776 interrupts = <0 22 4>,
785 wdt: watchdog@01c20c90 {
786 compatible = "allwinner,sun4i-a10-wdt";
787 reg = <0x01c20c90 0x10>;
791 compatible = "allwinner,sun7i-a20-rtc";
792 reg = <0x01c20d00 0x20>;
793 interrupts = <0 24 4>;
797 compatible = "allwinner,sun7i-a20-pwm";
798 reg = <0x01c20e00 0xc>;
805 compatible = "allwinner,sun4i-a10-ir";
806 clocks = <&apb0_gates 6>, <&ir0_clk>;
807 clock-names = "apb", "ir";
808 interrupts = <0 5 4>;
809 reg = <0x01c21800 0x40>;
814 compatible = "allwinner,sun4i-a10-ir";
815 clocks = <&apb0_gates 7>, <&ir1_clk>;
816 clock-names = "apb", "ir";
817 interrupts = <0 6 4>;
818 reg = <0x01c21c00 0x40>;
822 sid: eeprom@01c23800 {
823 compatible = "allwinner,sun7i-a20-sid";
824 reg = <0x01c23800 0x200>;
828 compatible = "allwinner,sun4i-a10-ts";
829 reg = <0x01c25000 0x100>;
830 interrupts = <0 29 4>;
833 uart0: serial@01c28000 {
834 compatible = "snps,dw-apb-uart";
835 reg = <0x01c28000 0x400>;
836 interrupts = <0 1 4>;
839 clocks = <&apb1_gates 16>;
843 uart1: serial@01c28400 {
844 compatible = "snps,dw-apb-uart";
845 reg = <0x01c28400 0x400>;
846 interrupts = <0 2 4>;
849 clocks = <&apb1_gates 17>;
853 uart2: serial@01c28800 {
854 compatible = "snps,dw-apb-uart";
855 reg = <0x01c28800 0x400>;
856 interrupts = <0 3 4>;
859 clocks = <&apb1_gates 18>;
863 uart3: serial@01c28c00 {
864 compatible = "snps,dw-apb-uart";
865 reg = <0x01c28c00 0x400>;
866 interrupts = <0 4 4>;
869 clocks = <&apb1_gates 19>;
873 uart4: serial@01c29000 {
874 compatible = "snps,dw-apb-uart";
875 reg = <0x01c29000 0x400>;
876 interrupts = <0 17 4>;
879 clocks = <&apb1_gates 20>;
883 uart5: serial@01c29400 {
884 compatible = "snps,dw-apb-uart";
885 reg = <0x01c29400 0x400>;
886 interrupts = <0 18 4>;
889 clocks = <&apb1_gates 21>;
893 uart6: serial@01c29800 {
894 compatible = "snps,dw-apb-uart";
895 reg = <0x01c29800 0x400>;
896 interrupts = <0 19 4>;
899 clocks = <&apb1_gates 22>;
903 uart7: serial@01c29c00 {
904 compatible = "snps,dw-apb-uart";
905 reg = <0x01c29c00 0x400>;
906 interrupts = <0 20 4>;
909 clocks = <&apb1_gates 23>;
914 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
915 reg = <0x01c2ac00 0x400>;
916 interrupts = <0 7 4>;
917 clocks = <&apb1_gates 0>;
919 #address-cells = <1>;
924 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
925 reg = <0x01c2b000 0x400>;
926 interrupts = <0 8 4>;
927 clocks = <&apb1_gates 1>;
929 #address-cells = <1>;
934 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
935 reg = <0x01c2b400 0x400>;
936 interrupts = <0 9 4>;
937 clocks = <&apb1_gates 2>;
939 #address-cells = <1>;
944 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
945 reg = <0x01c2b800 0x400>;
946 interrupts = <0 88 4>;
947 clocks = <&apb1_gates 3>;
949 #address-cells = <1>;
954 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
955 reg = <0x01c2c000 0x400>;
956 interrupts = <0 89 4>;
957 clocks = <&apb1_gates 15>;
959 #address-cells = <1>;
963 gmac: ethernet@01c50000 {
964 compatible = "allwinner,sun7i-a20-gmac";
965 reg = <0x01c50000 0x10000>;
966 interrupts = <0 85 4>;
967 interrupt-names = "macirq";
968 clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
969 clock-names = "stmmaceth", "allwinner_gmac_tx";
972 snps,force_sf_dma_mode;
974 #address-cells = <1>;
979 compatible = "allwinner,sun7i-a20-hstimer";
980 reg = <0x01c60000 0x1000>;
981 interrupts = <0 81 4>,
985 clocks = <&ahb_gates 28>;
988 gic: interrupt-controller@01c81000 {
989 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
990 reg = <0x01c81000 0x1000>,
994 interrupt-controller;
995 #interrupt-cells = <3>;
996 interrupts = <1 9 0xf04>;