2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include "skeleton.dtsi"
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/thermal/thermal.h>
50 #include <dt-bindings/clock/sun4i-a10-pll2.h>
51 #include <dt-bindings/dma/sun4i-a10.h>
52 #include <dt-bindings/pinctrl/sun4i-a10.h>
55 interrupt-parent = <&gic>;
67 compatible = "allwinner,simple-framebuffer",
69 allwinner,pipeline = "de_be0-lcd0-hdmi";
70 clocks = <&ahb_gates 36>, <&ahb_gates 43>,
71 <&ahb_gates 44>, <&de_be0_clk>,
72 <&tcon0_ch1_clk>, <&dram_gates 26>;
77 compatible = "allwinner,simple-framebuffer",
79 allwinner,pipeline = "de_be0-lcd0";
80 clocks = <&ahb_gates 36>, <&ahb_gates 44>,
81 <&de_be0_clk>, <&tcon0_ch0_clk>,
87 compatible = "allwinner,simple-framebuffer",
89 allwinner,pipeline = "de_be0-lcd0-tve0";
90 clocks = <&ahb_gates 34>, <&ahb_gates 36>,
92 <&de_be0_clk>, <&tcon0_ch1_clk>,
93 <&dram_gates 5>, <&dram_gates 26>;
103 compatible = "arm,cortex-a7";
107 clock-latency = <244144>; /* 8 32k periods */
118 #cooling-cells = <2>;
119 cooling-min-level = <0>;
120 cooling-max-level = <6>;
124 compatible = "arm,cortex-a7";
133 polling-delay-passive = <250>;
134 polling-delay = <1000>;
135 thermal-sensors = <&rtp>;
139 trip = <&cpu_alert0>;
140 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
145 cpu_alert0: cpu_alert0 {
147 temperature = <75000>;
154 temperature = <100000>;
163 reg = <0x40000000 0x80000000>;
167 compatible = "arm,armv7-timer";
168 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
169 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
170 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
171 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
175 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
176 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
181 #address-cells = <1>;
185 osc24M: clk@01c20050 {
187 compatible = "allwinner,sun4i-a10-osc-clk";
188 reg = <0x01c20050 0x4>;
189 clock-frequency = <24000000>;
190 clock-output-names = "osc24M";
195 compatible = "fixed-factor-clock";
199 clock-output-names = "osc3M";
204 compatible = "fixed-clock";
205 clock-frequency = <32768>;
206 clock-output-names = "osc32k";
211 compatible = "allwinner,sun4i-a10-pll1-clk";
212 reg = <0x01c20000 0x4>;
214 clock-output-names = "pll1";
219 compatible = "allwinner,sun4i-a10-pll2-clk";
220 reg = <0x01c20008 0x8>;
222 clock-output-names = "pll2-1x", "pll2-2x",
223 "pll2-4x", "pll2-8x";
228 compatible = "allwinner,sun4i-a10-pll3-clk";
229 reg = <0x01c20010 0x4>;
231 clock-output-names = "pll3";
236 compatible = "fixed-factor-clock";
240 clock-output-names = "pll3-2x";
245 compatible = "allwinner,sun7i-a20-pll4-clk";
246 reg = <0x01c20018 0x4>;
248 clock-output-names = "pll4";
253 compatible = "allwinner,sun4i-a10-pll5-clk";
254 reg = <0x01c20020 0x4>;
256 clock-output-names = "pll5_ddr", "pll5_other";
261 compatible = "allwinner,sun4i-a10-pll6-clk";
262 reg = <0x01c20028 0x4>;
264 clock-output-names = "pll6_sata", "pll6_other", "pll6",
270 compatible = "allwinner,sun4i-a10-pll3-clk";
271 reg = <0x01c20030 0x4>;
273 clock-output-names = "pll7";
278 compatible = "fixed-factor-clock";
282 clock-output-names = "pll7-2x";
287 compatible = "allwinner,sun7i-a20-pll4-clk";
288 reg = <0x01c20040 0x4>;
290 clock-output-names = "pll8";
295 compatible = "allwinner,sun4i-a10-cpu-clk";
296 reg = <0x01c20054 0x4>;
297 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
298 clock-output-names = "cpu";
303 compatible = "allwinner,sun4i-a10-axi-clk";
304 reg = <0x01c20054 0x4>;
306 clock-output-names = "axi";
311 compatible = "allwinner,sun5i-a13-ahb-clk";
312 reg = <0x01c20054 0x4>;
313 clocks = <&axi>, <&pll6 3>, <&pll6 1>;
314 clock-output-names = "ahb";
316 * Use PLL6 as parent, instead of CPU/AXI
317 * which has rate changes due to cpufreq
319 assigned-clocks = <&ahb>;
320 assigned-clock-parents = <&pll6 3>;
323 ahb_gates: clk@01c20060 {
325 compatible = "allwinner,sun7i-a20-ahb-gates-clk";
326 reg = <0x01c20060 0x8>;
328 clock-indices = <0>, <1>,
331 <9>, <10>, <11>, <12>,
333 <17>, <18>, <20>, <21>,
335 <28>, <32>, <33>, <34>,
336 <35>, <36>, <37>, <40>,
341 clock-output-names = "ahb_usb0", "ahb_ehci0",
342 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
343 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
344 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
345 "ahb_nand", "ahb_sdram", "ahb_ace",
346 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
347 "ahb_spi2", "ahb_spi3", "ahb_sata",
348 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
349 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
350 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
351 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
352 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
356 apb0: apb0@01c20054 {
358 compatible = "allwinner,sun4i-a10-apb0-clk";
359 reg = <0x01c20054 0x4>;
361 clock-output-names = "apb0";
364 apb0_gates: clk@01c20068 {
366 compatible = "allwinner,sun7i-a20-apb0-gates-clk";
367 reg = <0x01c20068 0x4>;
369 clock-indices = <0>, <1>,
373 clock-output-names = "apb0_codec", "apb0_spdif",
374 "apb0_ac97", "apb0_i2s0", "apb0_i2s1",
375 "apb0_pio", "apb0_ir0", "apb0_ir1",
376 "apb0_i2s2", "apb0_keypad";
381 compatible = "allwinner,sun4i-a10-apb1-clk";
382 reg = <0x01c20058 0x4>;
383 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
384 clock-output-names = "apb1";
387 apb1_gates: clk@01c2006c {
389 compatible = "allwinner,sun7i-a20-apb1-gates-clk";
390 reg = <0x01c2006c 0x4>;
392 clock-indices = <0>, <1>,
398 clock-output-names = "apb1_i2c0", "apb1_i2c1",
399 "apb1_i2c2", "apb1_i2c3", "apb1_can",
400 "apb1_scr", "apb1_ps20", "apb1_ps21",
401 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
402 "apb1_uart2", "apb1_uart3", "apb1_uart4",
403 "apb1_uart5", "apb1_uart6", "apb1_uart7";
406 nand_clk: clk@01c20080 {
408 compatible = "allwinner,sun4i-a10-mod0-clk";
409 reg = <0x01c20080 0x4>;
410 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
411 clock-output-names = "nand";
414 ms_clk: clk@01c20084 {
416 compatible = "allwinner,sun4i-a10-mod0-clk";
417 reg = <0x01c20084 0x4>;
418 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
419 clock-output-names = "ms";
422 mmc0_clk: clk@01c20088 {
424 compatible = "allwinner,sun4i-a10-mmc-clk";
425 reg = <0x01c20088 0x4>;
426 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
427 clock-output-names = "mmc0",
432 mmc1_clk: clk@01c2008c {
434 compatible = "allwinner,sun4i-a10-mmc-clk";
435 reg = <0x01c2008c 0x4>;
436 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
437 clock-output-names = "mmc1",
442 mmc2_clk: clk@01c20090 {
444 compatible = "allwinner,sun4i-a10-mmc-clk";
445 reg = <0x01c20090 0x4>;
446 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
447 clock-output-names = "mmc2",
452 mmc3_clk: clk@01c20094 {
454 compatible = "allwinner,sun4i-a10-mmc-clk";
455 reg = <0x01c20094 0x4>;
456 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
457 clock-output-names = "mmc3",
462 ts_clk: clk@01c20098 {
464 compatible = "allwinner,sun4i-a10-mod0-clk";
465 reg = <0x01c20098 0x4>;
466 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
467 clock-output-names = "ts";
470 ss_clk: clk@01c2009c {
472 compatible = "allwinner,sun4i-a10-mod0-clk";
473 reg = <0x01c2009c 0x4>;
474 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
475 clock-output-names = "ss";
478 spi0_clk: clk@01c200a0 {
480 compatible = "allwinner,sun4i-a10-mod0-clk";
481 reg = <0x01c200a0 0x4>;
482 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
483 clock-output-names = "spi0";
486 spi1_clk: clk@01c200a4 {
488 compatible = "allwinner,sun4i-a10-mod0-clk";
489 reg = <0x01c200a4 0x4>;
490 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
491 clock-output-names = "spi1";
494 spi2_clk: clk@01c200a8 {
496 compatible = "allwinner,sun4i-a10-mod0-clk";
497 reg = <0x01c200a8 0x4>;
498 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
499 clock-output-names = "spi2";
502 pata_clk: clk@01c200ac {
504 compatible = "allwinner,sun4i-a10-mod0-clk";
505 reg = <0x01c200ac 0x4>;
506 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
507 clock-output-names = "pata";
510 ir0_clk: clk@01c200b0 {
512 compatible = "allwinner,sun4i-a10-mod0-clk";
513 reg = <0x01c200b0 0x4>;
514 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
515 clock-output-names = "ir0";
518 ir1_clk: clk@01c200b4 {
520 compatible = "allwinner,sun4i-a10-mod0-clk";
521 reg = <0x01c200b4 0x4>;
522 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
523 clock-output-names = "ir1";
526 i2s0_clk: clk@01c200b8 {
528 compatible = "allwinner,sun4i-a10-mod1-clk";
529 reg = <0x01c200b8 0x4>;
530 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
531 <&pll2 SUN4I_A10_PLL2_4X>,
532 <&pll2 SUN4I_A10_PLL2_2X>,
533 <&pll2 SUN4I_A10_PLL2_1X>;
534 clock-output-names = "i2s0";
537 ac97_clk: clk@01c200bc {
539 compatible = "allwinner,sun4i-a10-mod1-clk";
540 reg = <0x01c200bc 0x4>;
541 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
542 <&pll2 SUN4I_A10_PLL2_4X>,
543 <&pll2 SUN4I_A10_PLL2_2X>,
544 <&pll2 SUN4I_A10_PLL2_1X>;
545 clock-output-names = "ac97";
548 spdif_clk: clk@01c200c0 {
550 compatible = "allwinner,sun4i-a10-mod1-clk";
551 reg = <0x01c200c0 0x4>;
552 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
553 <&pll2 SUN4I_A10_PLL2_4X>,
554 <&pll2 SUN4I_A10_PLL2_2X>,
555 <&pll2 SUN4I_A10_PLL2_1X>;
556 clock-output-names = "spdif";
559 keypad_clk: clk@01c200c4 {
561 compatible = "allwinner,sun4i-a10-mod0-clk";
562 reg = <0x01c200c4 0x4>;
564 clock-output-names = "keypad";
567 usb_clk: clk@01c200cc {
570 compatible = "allwinner,sun4i-a10-usb-clk";
571 reg = <0x01c200cc 0x4>;
573 clock-output-names = "usb_ohci0", "usb_ohci1",
577 spi3_clk: clk@01c200d4 {
579 compatible = "allwinner,sun4i-a10-mod0-clk";
580 reg = <0x01c200d4 0x4>;
581 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
582 clock-output-names = "spi3";
585 i2s1_clk: clk@01c200d8 {
587 compatible = "allwinner,sun4i-a10-mod1-clk";
588 reg = <0x01c200d8 0x4>;
589 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
590 <&pll2 SUN4I_A10_PLL2_4X>,
591 <&pll2 SUN4I_A10_PLL2_2X>,
592 <&pll2 SUN4I_A10_PLL2_1X>;
593 clock-output-names = "i2s1";
596 i2s2_clk: clk@01c200dc {
598 compatible = "allwinner,sun4i-a10-mod1-clk";
599 reg = <0x01c200dc 0x4>;
600 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
601 <&pll2 SUN4I_A10_PLL2_4X>,
602 <&pll2 SUN4I_A10_PLL2_2X>,
603 <&pll2 SUN4I_A10_PLL2_1X>;
604 clock-output-names = "i2s2";
607 dram_gates: clk@01c20100 {
609 compatible = "allwinner,sun4i-a10-dram-gates-clk";
610 reg = <0x01c20100 0x4>;
621 clock-output-names = "dram_ve",
622 "dram_csi0", "dram_csi1",
625 "dram_tve0", "dram_tve1",
627 "dram_de_fe1", "dram_de_fe0",
628 "dram_de_be0", "dram_de_be1",
629 "dram_de_mp", "dram_ace";
632 de_be0_clk: clk@01c20104 {
635 compatible = "allwinner,sun4i-a10-display-clk";
636 reg = <0x01c20104 0x4>;
637 clocks = <&pll3>, <&pll7>, <&pll5 1>;
638 clock-output-names = "de-be0";
641 de_be1_clk: clk@01c20108 {
644 compatible = "allwinner,sun4i-a10-display-clk";
645 reg = <0x01c20108 0x4>;
646 clocks = <&pll3>, <&pll7>, <&pll5 1>;
647 clock-output-names = "de-be1";
650 de_fe0_clk: clk@01c2010c {
653 compatible = "allwinner,sun4i-a10-display-clk";
654 reg = <0x01c2010c 0x4>;
655 clocks = <&pll3>, <&pll7>, <&pll5 1>;
656 clock-output-names = "de-fe0";
659 de_fe1_clk: clk@01c20110 {
662 compatible = "allwinner,sun4i-a10-display-clk";
663 reg = <0x01c20110 0x4>;
664 clocks = <&pll3>, <&pll7>, <&pll5 1>;
665 clock-output-names = "de-fe1";
668 tcon0_ch0_clk: clk@01c20118 {
671 compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
672 reg = <0x01c20118 0x4>;
673 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
674 clock-output-names = "tcon0-ch0-sclk";
678 tcon1_ch0_clk: clk@01c2011c {
681 compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
682 reg = <0x01c2011c 0x4>;
683 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
684 clock-output-names = "tcon1-ch0-sclk";
688 tcon0_ch1_clk: clk@01c2012c {
690 compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
691 reg = <0x01c2012c 0x4>;
692 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
693 clock-output-names = "tcon0-ch1-sclk";
697 tcon1_ch1_clk: clk@01c20130 {
699 compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
700 reg = <0x01c20130 0x4>;
701 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
702 clock-output-names = "tcon1-ch1-sclk";
706 ve_clk: clk@01c2013c {
709 compatible = "allwinner,sun4i-a10-ve-clk";
710 reg = <0x01c2013c 0x4>;
712 clock-output-names = "ve";
715 codec_clk: clk@01c20140 {
717 compatible = "allwinner,sun4i-a10-codec-clk";
718 reg = <0x01c20140 0x4>;
719 clocks = <&pll2 SUN4I_A10_PLL2_1X>;
720 clock-output-names = "codec";
723 mbus_clk: clk@01c2015c {
725 compatible = "allwinner,sun5i-a13-mbus-clk";
726 reg = <0x01c2015c 0x4>;
727 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
728 clock-output-names = "mbus";
732 * The following two are dummy clocks, placeholders
733 * used in the gmac_tx clock. The gmac driver will
734 * choose one parent depending on the PHY interface
735 * mode, using clk_set_rate auto-reparenting.
737 * The actual TX clock rate is not controlled by the
740 mii_phy_tx_clk: clk@2 {
742 compatible = "fixed-clock";
743 clock-frequency = <25000000>;
744 clock-output-names = "mii_phy_tx";
747 gmac_int_tx_clk: clk@3 {
749 compatible = "fixed-clock";
750 clock-frequency = <125000000>;
751 clock-output-names = "gmac_int_tx";
754 gmac_tx_clk: clk@01c20164 {
756 compatible = "allwinner,sun7i-a20-gmac-clk";
757 reg = <0x01c20164 0x4>;
758 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
759 clock-output-names = "gmac_tx";
763 * Dummy clock used by output clocks
767 compatible = "fixed-factor-clock";
771 clock-output-names = "osc24M_32k";
774 clk_out_a: clk@01c201f0 {
776 compatible = "allwinner,sun7i-a20-out-clk";
777 reg = <0x01c201f0 0x4>;
778 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
779 clock-output-names = "clk_out_a";
782 clk_out_b: clk@01c201f4 {
784 compatible = "allwinner,sun7i-a20-out-clk";
785 reg = <0x01c201f4 0x4>;
786 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
787 clock-output-names = "clk_out_b";
792 compatible = "simple-bus";
793 #address-cells = <1>;
797 sram-controller@01c00000 {
798 compatible = "allwinner,sun4i-a10-sram-controller";
799 reg = <0x01c00000 0x30>;
800 #address-cells = <1>;
804 sram_a: sram@00000000 {
805 compatible = "mmio-sram";
806 reg = <0x00000000 0xc000>;
807 #address-cells = <1>;
809 ranges = <0 0x00000000 0xc000>;
811 emac_sram: sram-section@8000 {
812 compatible = "allwinner,sun4i-a10-sram-a3-a4";
813 reg = <0x8000 0x4000>;
818 sram_d: sram@00010000 {
819 compatible = "mmio-sram";
820 reg = <0x00010000 0x1000>;
821 #address-cells = <1>;
823 ranges = <0 0x00010000 0x1000>;
825 otg_sram: sram-section@0000 {
826 compatible = "allwinner,sun4i-a10-sram-d";
827 reg = <0x0000 0x1000>;
833 nmi_intc: interrupt-controller@01c00030 {
834 compatible = "allwinner,sun7i-a20-sc-nmi";
835 interrupt-controller;
836 #interrupt-cells = <2>;
837 reg = <0x01c00030 0x0c>;
838 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
841 dma: dma-controller@01c02000 {
842 compatible = "allwinner,sun4i-a10-dma";
843 reg = <0x01c02000 0x1000>;
844 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
845 clocks = <&ahb_gates 6>;
850 compatible = "allwinner,sun4i-a10-nand";
851 reg = <0x01c03000 0x1000>;
852 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
853 clocks = <&ahb_gates 13>, <&nand_clk>;
854 clock-names = "ahb", "mod";
855 dmas = <&dma SUN4I_DMA_DEDICATED 3>;
858 #address-cells = <1>;
863 compatible = "allwinner,sun4i-a10-spi";
864 reg = <0x01c05000 0x1000>;
865 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
866 clocks = <&ahb_gates 20>, <&spi0_clk>;
867 clock-names = "ahb", "mod";
868 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
869 <&dma SUN4I_DMA_DEDICATED 26>;
870 dma-names = "rx", "tx";
872 #address-cells = <1>;
877 compatible = "allwinner,sun4i-a10-spi";
878 reg = <0x01c06000 0x1000>;
879 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
880 clocks = <&ahb_gates 21>, <&spi1_clk>;
881 clock-names = "ahb", "mod";
882 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
883 <&dma SUN4I_DMA_DEDICATED 8>;
884 dma-names = "rx", "tx";
886 #address-cells = <1>;
890 emac: ethernet@01c0b000 {
891 compatible = "allwinner,sun4i-a10-emac";
892 reg = <0x01c0b000 0x1000>;
893 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
894 clocks = <&ahb_gates 17>;
895 allwinner,sram = <&emac_sram 1>;
899 mdio: mdio@01c0b080 {
900 compatible = "allwinner,sun4i-a10-mdio";
901 reg = <0x01c0b080 0x14>;
903 #address-cells = <1>;
908 compatible = "allwinner,sun7i-a20-mmc";
909 reg = <0x01c0f000 0x1000>;
910 clocks = <&ahb_gates 8>,
918 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
920 #address-cells = <1>;
925 compatible = "allwinner,sun7i-a20-mmc";
926 reg = <0x01c10000 0x1000>;
927 clocks = <&ahb_gates 9>,
935 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
937 #address-cells = <1>;
942 compatible = "allwinner,sun7i-a20-mmc";
943 reg = <0x01c11000 0x1000>;
944 clocks = <&ahb_gates 10>,
952 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
954 #address-cells = <1>;
959 compatible = "allwinner,sun7i-a20-mmc";
960 reg = <0x01c12000 0x1000>;
961 clocks = <&ahb_gates 11>,
969 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
971 #address-cells = <1>;
975 usb_otg: usb@01c13000 {
976 compatible = "allwinner,sun4i-a10-musb";
977 reg = <0x01c13000 0x0400>;
978 clocks = <&ahb_gates 0>;
979 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
980 interrupt-names = "mc";
983 extcon = <&usbphy 0>;
984 allwinner,sram = <&otg_sram 1>;
988 usbphy: phy@01c13400 {
990 compatible = "allwinner,sun7i-a20-usb-phy";
991 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
992 reg-names = "phy_ctrl", "pmu1", "pmu2";
993 clocks = <&usb_clk 8>;
994 clock-names = "usb_phy";
995 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
996 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
1000 ehci0: usb@01c14000 {
1001 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
1002 reg = <0x01c14000 0x100>;
1003 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1004 clocks = <&ahb_gates 1>;
1007 status = "disabled";
1010 ohci0: usb@01c14400 {
1011 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
1012 reg = <0x01c14400 0x100>;
1013 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1014 clocks = <&usb_clk 6>, <&ahb_gates 2>;
1017 status = "disabled";
1020 crypto: crypto-engine@01c15000 {
1021 compatible = "allwinner,sun4i-a10-crypto";
1022 reg = <0x01c15000 0x1000>;
1023 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1024 clocks = <&ahb_gates 5>, <&ss_clk>;
1025 clock-names = "ahb", "mod";
1028 spi2: spi@01c17000 {
1029 compatible = "allwinner,sun4i-a10-spi";
1030 reg = <0x01c17000 0x1000>;
1031 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1032 clocks = <&ahb_gates 22>, <&spi2_clk>;
1033 clock-names = "ahb", "mod";
1034 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
1035 <&dma SUN4I_DMA_DEDICATED 28>;
1036 dma-names = "rx", "tx";
1037 status = "disabled";
1038 #address-cells = <1>;
1042 ahci: sata@01c18000 {
1043 compatible = "allwinner,sun4i-a10-ahci";
1044 reg = <0x01c18000 0x1000>;
1045 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1046 clocks = <&pll6 0>, <&ahb_gates 25>;
1047 status = "disabled";
1050 ehci1: usb@01c1c000 {
1051 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
1052 reg = <0x01c1c000 0x100>;
1053 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1054 clocks = <&ahb_gates 3>;
1057 status = "disabled";
1060 ohci1: usb@01c1c400 {
1061 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
1062 reg = <0x01c1c400 0x100>;
1063 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1064 clocks = <&usb_clk 7>, <&ahb_gates 4>;
1067 status = "disabled";
1070 spi3: spi@01c1f000 {
1071 compatible = "allwinner,sun4i-a10-spi";
1072 reg = <0x01c1f000 0x1000>;
1073 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1074 clocks = <&ahb_gates 23>, <&spi3_clk>;
1075 clock-names = "ahb", "mod";
1076 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
1077 <&dma SUN4I_DMA_DEDICATED 30>;
1078 dma-names = "rx", "tx";
1079 status = "disabled";
1080 #address-cells = <1>;
1084 pio: pinctrl@01c20800 {
1085 compatible = "allwinner,sun7i-a20-pinctrl";
1086 reg = <0x01c20800 0x400>;
1087 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1088 clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>;
1089 clock-names = "apb", "hosc", "losc";
1091 interrupt-controller;
1092 #interrupt-cells = <3>;
1095 clk_out_a_pins_a: clk_out_a@0 {
1097 function = "clk_out_a";
1100 clk_out_b_pins_a: clk_out_b@0 {
1102 function = "clk_out_b";
1105 emac_pins_a: emac0@0 {
1106 pins = "PA0", "PA1", "PA2",
1107 "PA3", "PA4", "PA5", "PA6",
1108 "PA7", "PA8", "PA9", "PA10",
1109 "PA11", "PA12", "PA13", "PA14",
1114 gmac_pins_mii_a: gmac_mii@0 {
1115 pins = "PA0", "PA1", "PA2",
1116 "PA3", "PA4", "PA5", "PA6",
1117 "PA7", "PA8", "PA9", "PA10",
1118 "PA11", "PA12", "PA13", "PA14",
1123 gmac_pins_rgmii_a: gmac_rgmii@0 {
1124 pins = "PA0", "PA1", "PA2",
1125 "PA3", "PA4", "PA5", "PA6",
1126 "PA7", "PA8", "PA10",
1127 "PA11", "PA12", "PA13",
1131 * data lines in RGMII mode use DDR mode
1132 * and need a higher signal drive strength
1134 drive-strength = <40>;
1137 i2c0_pins_a: i2c0@0 {
1138 pins = "PB0", "PB1";
1142 i2c1_pins_a: i2c1@0 {
1143 pins = "PB18", "PB19";
1147 i2c2_pins_a: i2c2@0 {
1148 pins = "PB20", "PB21";
1152 i2c3_pins_a: i2c3@0 {
1153 pins = "PI0", "PI1";
1157 ir0_rx_pins_a: ir0@0 {
1162 ir0_tx_pins_a: ir0@1 {
1167 ir1_rx_pins_a: ir1@0 {
1172 ir1_tx_pins_a: ir1@1 {
1177 mmc0_pins_a: mmc0@0 {
1178 pins = "PF0", "PF1", "PF2",
1179 "PF3", "PF4", "PF5";
1181 drive-strength = <30>;
1184 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
1186 function = "gpio_in";
1190 mmc2_pins_a: mmc2@0 {
1191 pins = "PC6", "PC7", "PC8",
1192 "PC9", "PC10", "PC11";
1194 drive-strength = <30>;
1198 mmc3_pins_a: mmc3@0 {
1199 pins = "PI4", "PI5", "PI6",
1200 "PI7", "PI8", "PI9";
1202 drive-strength = <30>;
1205 ps20_pins_a: ps20@0 {
1206 pins = "PI20", "PI21";
1210 ps21_pins_a: ps21@0 {
1211 pins = "PH12", "PH13";
1215 pwm0_pins_a: pwm0@0 {
1220 pwm1_pins_a: pwm1@0 {
1225 spdif_tx_pins_a: spdif@0 {
1231 spi0_pins_a: spi0@0 {
1232 pins = "PI11", "PI12", "PI13";
1236 spi0_cs0_pins_a: spi0_cs0@0 {
1241 spi0_cs1_pins_a: spi0_cs1@0 {
1246 spi1_pins_a: spi1@0 {
1247 pins = "PI17", "PI18", "PI19";
1251 spi1_cs0_pins_a: spi1_cs0@0 {
1256 spi2_pins_a: spi2@0 {
1257 pins = "PC20", "PC21", "PC22";
1261 spi2_pins_b: spi2@1 {
1262 pins = "PB15", "PB16", "PB17";
1266 spi2_cs0_pins_a: spi2_cs0@0 {
1271 spi2_cs0_pins_b: spi2_cs0@1 {
1276 uart0_pins_a: uart0@0 {
1277 pins = "PB22", "PB23";
1281 uart2_pins_a: uart2@0 {
1282 pins = "PI16", "PI17", "PI18", "PI19";
1286 uart3_pins_a: uart3@0 {
1287 pins = "PG6", "PG7", "PG8", "PG9";
1291 uart3_pins_b: uart3@1 {
1292 pins = "PH0", "PH1";
1296 uart4_pins_a: uart4@0 {
1297 pins = "PG10", "PG11";
1301 uart4_pins_b: uart4@1 {
1302 pins = "PH4", "PH5";
1306 uart5_pins_a: uart5@0 {
1307 pins = "PI10", "PI11";
1311 uart6_pins_a: uart6@0 {
1312 pins = "PI12", "PI13";
1316 uart7_pins_a: uart7@0 {
1317 pins = "PI20", "PI21";
1323 compatible = "allwinner,sun4i-a10-timer";
1324 reg = <0x01c20c00 0x90>;
1325 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
1326 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
1327 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1328 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1329 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
1330 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1334 wdt: watchdog@01c20c90 {
1335 compatible = "allwinner,sun4i-a10-wdt";
1336 reg = <0x01c20c90 0x10>;
1340 compatible = "allwinner,sun7i-a20-rtc";
1341 reg = <0x01c20d00 0x20>;
1342 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1346 compatible = "allwinner,sun7i-a20-pwm";
1347 reg = <0x01c20e00 0xc>;
1350 status = "disabled";
1353 spdif: spdif@01c21000 {
1354 #sound-dai-cells = <0>;
1355 compatible = "allwinner,sun4i-a10-spdif";
1356 reg = <0x01c21000 0x400>;
1357 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1358 clocks = <&apb0_gates 1>, <&spdif_clk>;
1359 clock-names = "apb", "spdif";
1360 dmas = <&dma SUN4I_DMA_NORMAL 2>,
1361 <&dma SUN4I_DMA_NORMAL 2>;
1362 dma-names = "rx", "tx";
1363 status = "disabled";
1367 compatible = "allwinner,sun4i-a10-ir";
1368 clocks = <&apb0_gates 6>, <&ir0_clk>;
1369 clock-names = "apb", "ir";
1370 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1371 reg = <0x01c21800 0x40>;
1372 status = "disabled";
1376 compatible = "allwinner,sun4i-a10-ir";
1377 clocks = <&apb0_gates 7>, <&ir1_clk>;
1378 clock-names = "apb", "ir";
1379 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1380 reg = <0x01c21c00 0x40>;
1381 status = "disabled";
1384 i2s1: i2s@01c22000 {
1385 #sound-dai-cells = <0>;
1386 compatible = "allwinner,sun4i-a10-i2s";
1387 reg = <0x01c22000 0x400>;
1388 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1389 clocks = <&apb0_gates 4>, <&i2s1_clk>;
1390 clock-names = "apb", "mod";
1391 dmas = <&dma SUN4I_DMA_NORMAL 4>,
1392 <&dma SUN4I_DMA_NORMAL 4>;
1393 dma-names = "rx", "tx";
1394 status = "disabled";
1397 i2s0: i2s@01c22400 {
1398 #sound-dai-cells = <0>;
1399 compatible = "allwinner,sun4i-a10-i2s";
1400 reg = <0x01c22400 0x400>;
1401 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1402 clocks = <&apb0_gates 3>, <&i2s0_clk>;
1403 clock-names = "apb", "mod";
1404 dmas = <&dma SUN4I_DMA_NORMAL 3>,
1405 <&dma SUN4I_DMA_NORMAL 3>;
1406 dma-names = "rx", "tx";
1407 status = "disabled";
1410 lradc: lradc@01c22800 {
1411 compatible = "allwinner,sun4i-a10-lradc-keys";
1412 reg = <0x01c22800 0x100>;
1413 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1414 status = "disabled";
1417 codec: codec@01c22c00 {
1418 #sound-dai-cells = <0>;
1419 compatible = "allwinner,sun7i-a20-codec";
1420 reg = <0x01c22c00 0x40>;
1421 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1422 clocks = <&apb0_gates 0>, <&codec_clk>;
1423 clock-names = "apb", "codec";
1424 dmas = <&dma SUN4I_DMA_NORMAL 19>,
1425 <&dma SUN4I_DMA_NORMAL 19>;
1426 dma-names = "rx", "tx";
1427 status = "disabled";
1430 sid: eeprom@01c23800 {
1431 compatible = "allwinner,sun7i-a20-sid";
1432 reg = <0x01c23800 0x200>;
1435 i2s2: i2s@01c24400 {
1436 #sound-dai-cells = <0>;
1437 compatible = "allwinner,sun4i-a10-i2s";
1438 reg = <0x01c24400 0x400>;
1439 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1440 clocks = <&apb0_gates 8>, <&i2s2_clk>;
1441 clock-names = "apb", "mod";
1442 dmas = <&dma SUN4I_DMA_NORMAL 6>,
1443 <&dma SUN4I_DMA_NORMAL 6>;
1444 dma-names = "rx", "tx";
1445 status = "disabled";
1449 compatible = "allwinner,sun5i-a13-ts";
1450 reg = <0x01c25000 0x100>;
1451 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1452 #thermal-sensor-cells = <0>;
1455 uart0: serial@01c28000 {
1456 compatible = "snps,dw-apb-uart";
1457 reg = <0x01c28000 0x400>;
1458 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1461 clocks = <&apb1_gates 16>;
1462 status = "disabled";
1465 uart1: serial@01c28400 {
1466 compatible = "snps,dw-apb-uart";
1467 reg = <0x01c28400 0x400>;
1468 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1471 clocks = <&apb1_gates 17>;
1472 status = "disabled";
1475 uart2: serial@01c28800 {
1476 compatible = "snps,dw-apb-uart";
1477 reg = <0x01c28800 0x400>;
1478 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1481 clocks = <&apb1_gates 18>;
1482 status = "disabled";
1485 uart3: serial@01c28c00 {
1486 compatible = "snps,dw-apb-uart";
1487 reg = <0x01c28c00 0x400>;
1488 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1491 clocks = <&apb1_gates 19>;
1492 status = "disabled";
1495 uart4: serial@01c29000 {
1496 compatible = "snps,dw-apb-uart";
1497 reg = <0x01c29000 0x400>;
1498 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1501 clocks = <&apb1_gates 20>;
1502 status = "disabled";
1505 uart5: serial@01c29400 {
1506 compatible = "snps,dw-apb-uart";
1507 reg = <0x01c29400 0x400>;
1508 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1511 clocks = <&apb1_gates 21>;
1512 status = "disabled";
1515 uart6: serial@01c29800 {
1516 compatible = "snps,dw-apb-uart";
1517 reg = <0x01c29800 0x400>;
1518 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1521 clocks = <&apb1_gates 22>;
1522 status = "disabled";
1525 uart7: serial@01c29c00 {
1526 compatible = "snps,dw-apb-uart";
1527 reg = <0x01c29c00 0x400>;
1528 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1531 clocks = <&apb1_gates 23>;
1532 status = "disabled";
1535 i2c0: i2c@01c2ac00 {
1536 compatible = "allwinner,sun7i-a20-i2c",
1537 "allwinner,sun4i-a10-i2c";
1538 reg = <0x01c2ac00 0x400>;
1539 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1540 clocks = <&apb1_gates 0>;
1541 status = "disabled";
1542 #address-cells = <1>;
1546 i2c1: i2c@01c2b000 {
1547 compatible = "allwinner,sun7i-a20-i2c",
1548 "allwinner,sun4i-a10-i2c";
1549 reg = <0x01c2b000 0x400>;
1550 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1551 clocks = <&apb1_gates 1>;
1552 status = "disabled";
1553 #address-cells = <1>;
1557 i2c2: i2c@01c2b400 {
1558 compatible = "allwinner,sun7i-a20-i2c",
1559 "allwinner,sun4i-a10-i2c";
1560 reg = <0x01c2b400 0x400>;
1561 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1562 clocks = <&apb1_gates 2>;
1563 status = "disabled";
1564 #address-cells = <1>;
1568 i2c3: i2c@01c2b800 {
1569 compatible = "allwinner,sun7i-a20-i2c",
1570 "allwinner,sun4i-a10-i2c";
1571 reg = <0x01c2b800 0x400>;
1572 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1573 clocks = <&apb1_gates 3>;
1574 status = "disabled";
1575 #address-cells = <1>;
1579 i2c4: i2c@01c2c000 {
1580 compatible = "allwinner,sun7i-a20-i2c",
1581 "allwinner,sun4i-a10-i2c";
1582 reg = <0x01c2c000 0x400>;
1583 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1584 clocks = <&apb1_gates 15>;
1585 status = "disabled";
1586 #address-cells = <1>;
1590 gmac: ethernet@01c50000 {
1591 compatible = "allwinner,sun7i-a20-gmac";
1592 reg = <0x01c50000 0x10000>;
1593 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1594 interrupt-names = "macirq";
1595 clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
1596 clock-names = "stmmaceth", "allwinner_gmac_tx";
1599 snps,force_sf_dma_mode;
1600 status = "disabled";
1601 #address-cells = <1>;
1606 compatible = "allwinner,sun7i-a20-hstimer";
1607 reg = <0x01c60000 0x1000>;
1608 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1609 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1610 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1611 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1612 clocks = <&ahb_gates 28>;
1615 gic: interrupt-controller@01c81000 {
1616 compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1617 reg = <0x01c81000 0x1000>,
1618 <0x01c82000 0x2000>,
1619 <0x01c84000 0x2000>,
1620 <0x01c86000 0x2000>;
1621 interrupt-controller;
1622 #interrupt-cells = <3>;
1623 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1626 ps20: ps2@01c2a000 {
1627 compatible = "allwinner,sun4i-a10-ps2";
1628 reg = <0x01c2a000 0x400>;
1629 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1630 clocks = <&apb1_gates 6>;
1631 status = "disabled";
1634 ps21: ps2@01c2a400 {
1635 compatible = "allwinner,sun4i-a10-ps2";
1636 reg = <0x01c2a400 0x400>;
1637 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1638 clocks = <&apb1_gates 7>;
1639 status = "disabled";