2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include "skeleton.dtsi"
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/thermal/thermal.h>
50 #include <dt-bindings/dma/sun4i-a10.h>
51 #include <dt-bindings/pinctrl/sun4i-a10.h>
54 interrupt-parent = <&gic>;
66 compatible = "allwinner,simple-framebuffer",
68 allwinner,pipeline = "de_be0-lcd0-hdmi";
69 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
75 compatible = "allwinner,simple-framebuffer",
77 allwinner,pipeline = "de_be0-lcd0";
78 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
83 compatible = "allwinner,simple-framebuffer",
85 allwinner,pipeline = "de_be0-lcd0-tve0";
86 clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
97 compatible = "arm,cortex-a7";
101 clock-latency = <244144>; /* 8 32k periods */
112 #cooling-cells = <2>;
113 cooling-min-level = <0>;
114 cooling-max-level = <6>;
118 compatible = "arm,cortex-a7";
127 polling-delay-passive = <250>;
128 polling-delay = <1000>;
129 thermal-sensors = <&rtp>;
133 trip = <&cpu_alert0>;
134 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
139 cpu_alert0: cpu_alert0 {
141 temperature = <75000>;
148 temperature = <100000>;
157 reg = <0x40000000 0x80000000>;
161 compatible = "arm,armv7-timer";
162 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
163 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
164 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
165 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
169 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
170 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
175 #address-cells = <1>;
179 osc24M: clk@01c20050 {
181 compatible = "allwinner,sun4i-a10-osc-clk";
182 reg = <0x01c20050 0x4>;
183 clock-frequency = <24000000>;
184 clock-output-names = "osc24M";
189 compatible = "fixed-clock";
190 clock-frequency = <32768>;
191 clock-output-names = "osc32k";
196 compatible = "allwinner,sun4i-a10-pll1-clk";
197 reg = <0x01c20000 0x4>;
199 clock-output-names = "pll1";
204 compatible = "allwinner,sun7i-a20-pll4-clk";
205 reg = <0x01c20018 0x4>;
207 clock-output-names = "pll4";
212 compatible = "allwinner,sun4i-a10-pll5-clk";
213 reg = <0x01c20020 0x4>;
215 clock-output-names = "pll5_ddr", "pll5_other";
220 compatible = "allwinner,sun4i-a10-pll6-clk";
221 reg = <0x01c20028 0x4>;
223 clock-output-names = "pll6_sata", "pll6_other", "pll6",
229 compatible = "allwinner,sun7i-a20-pll4-clk";
230 reg = <0x01c20040 0x4>;
232 clock-output-names = "pll8";
237 compatible = "allwinner,sun4i-a10-cpu-clk";
238 reg = <0x01c20054 0x4>;
239 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
240 clock-output-names = "cpu";
245 compatible = "allwinner,sun4i-a10-axi-clk";
246 reg = <0x01c20054 0x4>;
248 clock-output-names = "axi";
253 compatible = "allwinner,sun5i-a13-ahb-clk";
254 reg = <0x01c20054 0x4>;
255 clocks = <&axi>, <&pll6 3>, <&pll6 1>;
256 clock-output-names = "ahb";
258 * Use PLL6 as parent, instead of CPU/AXI
259 * which has rate changes due to cpufreq
261 assigned-clocks = <&ahb>;
262 assigned-clock-parents = <&pll6 3>;
265 ahb_gates: clk@01c20060 {
267 compatible = "allwinner,sun7i-a20-ahb-gates-clk";
268 reg = <0x01c20060 0x8>;
270 clock-output-names = "ahb_usb0", "ahb_ehci0",
271 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
272 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
273 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
274 "ahb_nand", "ahb_sdram", "ahb_ace",
275 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
276 "ahb_spi2", "ahb_spi3", "ahb_sata",
277 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
278 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
279 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
280 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
281 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
285 apb0: apb0@01c20054 {
287 compatible = "allwinner,sun4i-a10-apb0-clk";
288 reg = <0x01c20054 0x4>;
290 clock-output-names = "apb0";
293 apb0_gates: clk@01c20068 {
295 compatible = "allwinner,sun7i-a20-apb0-gates-clk";
296 reg = <0x01c20068 0x4>;
298 clock-output-names = "apb0_codec", "apb0_spdif",
299 "apb0_ac97", "apb0_iis0", "apb0_iis1",
300 "apb0_pio", "apb0_ir0", "apb0_ir1",
301 "apb0_iis2", "apb0_keypad";
306 compatible = "allwinner,sun4i-a10-apb1-clk";
307 reg = <0x01c20058 0x4>;
308 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
309 clock-output-names = "apb1";
312 apb1_gates: clk@01c2006c {
314 compatible = "allwinner,sun7i-a20-apb1-gates-clk";
315 reg = <0x01c2006c 0x4>;
317 clock-output-names = "apb1_i2c0", "apb1_i2c1",
318 "apb1_i2c2", "apb1_i2c3", "apb1_can",
319 "apb1_scr", "apb1_ps20", "apb1_ps21",
320 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
321 "apb1_uart2", "apb1_uart3", "apb1_uart4",
322 "apb1_uart5", "apb1_uart6", "apb1_uart7";
325 nand_clk: clk@01c20080 {
327 compatible = "allwinner,sun4i-a10-mod0-clk";
328 reg = <0x01c20080 0x4>;
329 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
330 clock-output-names = "nand";
333 ms_clk: clk@01c20084 {
335 compatible = "allwinner,sun4i-a10-mod0-clk";
336 reg = <0x01c20084 0x4>;
337 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
338 clock-output-names = "ms";
341 mmc0_clk: clk@01c20088 {
343 compatible = "allwinner,sun4i-a10-mmc-clk";
344 reg = <0x01c20088 0x4>;
345 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
346 clock-output-names = "mmc0",
351 mmc1_clk: clk@01c2008c {
353 compatible = "allwinner,sun4i-a10-mmc-clk";
354 reg = <0x01c2008c 0x4>;
355 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
356 clock-output-names = "mmc1",
361 mmc2_clk: clk@01c20090 {
363 compatible = "allwinner,sun4i-a10-mmc-clk";
364 reg = <0x01c20090 0x4>;
365 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
366 clock-output-names = "mmc2",
371 mmc3_clk: clk@01c20094 {
373 compatible = "allwinner,sun4i-a10-mmc-clk";
374 reg = <0x01c20094 0x4>;
375 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
376 clock-output-names = "mmc3",
381 ts_clk: clk@01c20098 {
383 compatible = "allwinner,sun4i-a10-mod0-clk";
384 reg = <0x01c20098 0x4>;
385 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
386 clock-output-names = "ts";
389 ss_clk: clk@01c2009c {
391 compatible = "allwinner,sun4i-a10-mod0-clk";
392 reg = <0x01c2009c 0x4>;
393 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
394 clock-output-names = "ss";
397 spi0_clk: clk@01c200a0 {
399 compatible = "allwinner,sun4i-a10-mod0-clk";
400 reg = <0x01c200a0 0x4>;
401 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
402 clock-output-names = "spi0";
405 spi1_clk: clk@01c200a4 {
407 compatible = "allwinner,sun4i-a10-mod0-clk";
408 reg = <0x01c200a4 0x4>;
409 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
410 clock-output-names = "spi1";
413 spi2_clk: clk@01c200a8 {
415 compatible = "allwinner,sun4i-a10-mod0-clk";
416 reg = <0x01c200a8 0x4>;
417 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
418 clock-output-names = "spi2";
421 pata_clk: clk@01c200ac {
423 compatible = "allwinner,sun4i-a10-mod0-clk";
424 reg = <0x01c200ac 0x4>;
425 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
426 clock-output-names = "pata";
429 ir0_clk: clk@01c200b0 {
431 compatible = "allwinner,sun4i-a10-mod0-clk";
432 reg = <0x01c200b0 0x4>;
433 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
434 clock-output-names = "ir0";
437 ir1_clk: clk@01c200b4 {
439 compatible = "allwinner,sun4i-a10-mod0-clk";
440 reg = <0x01c200b4 0x4>;
441 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
442 clock-output-names = "ir1";
445 usb_clk: clk@01c200cc {
448 compatible = "allwinner,sun4i-a10-usb-clk";
449 reg = <0x01c200cc 0x4>;
451 clock-output-names = "usb_ohci0", "usb_ohci1",
455 spi3_clk: clk@01c200d4 {
457 compatible = "allwinner,sun4i-a10-mod0-clk";
458 reg = <0x01c200d4 0x4>;
459 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
460 clock-output-names = "spi3";
463 mbus_clk: clk@01c2015c {
465 compatible = "allwinner,sun5i-a13-mbus-clk";
466 reg = <0x01c2015c 0x4>;
467 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
468 clock-output-names = "mbus";
472 * The following two are dummy clocks, placeholders
473 * used in the gmac_tx clock. The gmac driver will
474 * choose one parent depending on the PHY interface
475 * mode, using clk_set_rate auto-reparenting.
477 * The actual TX clock rate is not controlled by the
480 mii_phy_tx_clk: clk@2 {
482 compatible = "fixed-clock";
483 clock-frequency = <25000000>;
484 clock-output-names = "mii_phy_tx";
487 gmac_int_tx_clk: clk@3 {
489 compatible = "fixed-clock";
490 clock-frequency = <125000000>;
491 clock-output-names = "gmac_int_tx";
494 gmac_tx_clk: clk@01c20164 {
496 compatible = "allwinner,sun7i-a20-gmac-clk";
497 reg = <0x01c20164 0x4>;
498 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
499 clock-output-names = "gmac_tx";
503 * Dummy clock used by output clocks
507 compatible = "fixed-factor-clock";
511 clock-output-names = "osc24M_32k";
514 clk_out_a: clk@01c201f0 {
516 compatible = "allwinner,sun7i-a20-out-clk";
517 reg = <0x01c201f0 0x4>;
518 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
519 clock-output-names = "clk_out_a";
522 clk_out_b: clk@01c201f4 {
524 compatible = "allwinner,sun7i-a20-out-clk";
525 reg = <0x01c201f4 0x4>;
526 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
527 clock-output-names = "clk_out_b";
532 compatible = "simple-bus";
533 #address-cells = <1>;
537 sram-controller@01c00000 {
538 compatible = "allwinner,sun4i-a10-sram-controller";
539 reg = <0x01c00000 0x30>;
540 #address-cells = <1>;
544 sram_a: sram@00000000 {
545 compatible = "mmio-sram";
546 reg = <0x00000000 0xc000>;
547 #address-cells = <1>;
549 ranges = <0 0x00000000 0xc000>;
551 emac_sram: sram-section@8000 {
552 compatible = "allwinner,sun4i-a10-sram-a3-a4";
553 reg = <0x8000 0x4000>;
558 sram_d: sram@00010000 {
559 compatible = "mmio-sram";
560 reg = <0x00010000 0x1000>;
561 #address-cells = <1>;
563 ranges = <0 0x00010000 0x1000>;
565 otg_sram: sram-section@0000 {
566 compatible = "allwinner,sun4i-a10-sram-d";
567 reg = <0x0000 0x1000>;
573 nmi_intc: interrupt-controller@01c00030 {
574 compatible = "allwinner,sun7i-a20-sc-nmi";
575 interrupt-controller;
576 #interrupt-cells = <2>;
577 reg = <0x01c00030 0x0c>;
578 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
581 dma: dma-controller@01c02000 {
582 compatible = "allwinner,sun4i-a10-dma";
583 reg = <0x01c02000 0x1000>;
584 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
585 clocks = <&ahb_gates 6>;
590 compatible = "allwinner,sun4i-a10-spi";
591 reg = <0x01c05000 0x1000>;
592 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
593 clocks = <&ahb_gates 20>, <&spi0_clk>;
594 clock-names = "ahb", "mod";
595 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
596 <&dma SUN4I_DMA_DEDICATED 26>;
597 dma-names = "rx", "tx";
599 #address-cells = <1>;
604 compatible = "allwinner,sun4i-a10-spi";
605 reg = <0x01c06000 0x1000>;
606 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&ahb_gates 21>, <&spi1_clk>;
608 clock-names = "ahb", "mod";
609 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
610 <&dma SUN4I_DMA_DEDICATED 8>;
611 dma-names = "rx", "tx";
613 #address-cells = <1>;
617 emac: ethernet@01c0b000 {
618 compatible = "allwinner,sun4i-a10-emac";
619 reg = <0x01c0b000 0x1000>;
620 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&ahb_gates 17>;
622 allwinner,sram = <&emac_sram 1>;
626 mdio: mdio@01c0b080 {
627 compatible = "allwinner,sun4i-a10-mdio";
628 reg = <0x01c0b080 0x14>;
630 #address-cells = <1>;
635 compatible = "allwinner,sun5i-a13-mmc";
636 reg = <0x01c0f000 0x1000>;
637 clocks = <&ahb_gates 8>,
645 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
647 #address-cells = <1>;
652 compatible = "allwinner,sun5i-a13-mmc";
653 reg = <0x01c10000 0x1000>;
654 clocks = <&ahb_gates 9>,
662 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
664 #address-cells = <1>;
669 compatible = "allwinner,sun5i-a13-mmc";
670 reg = <0x01c11000 0x1000>;
671 clocks = <&ahb_gates 10>,
679 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
681 #address-cells = <1>;
686 compatible = "allwinner,sun5i-a13-mmc";
687 reg = <0x01c12000 0x1000>;
688 clocks = <&ahb_gates 11>,
696 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
698 #address-cells = <1>;
702 usb_otg: usb@01c13000 {
703 compatible = "allwinner,sun4i-a10-musb";
704 reg = <0x01c13000 0x0400>;
705 clocks = <&ahb_gates 0>;
706 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
707 interrupt-names = "mc";
710 extcon = <&usbphy 0>;
711 allwinner,sram = <&otg_sram 1>;
715 usbphy: phy@01c13400 {
717 compatible = "allwinner,sun7i-a20-usb-phy";
718 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
719 reg-names = "phy_ctrl", "pmu1", "pmu2";
720 clocks = <&usb_clk 8>;
721 clock-names = "usb_phy";
722 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
723 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
727 ehci0: usb@01c14000 {
728 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
729 reg = <0x01c14000 0x100>;
730 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
731 clocks = <&ahb_gates 1>;
737 ohci0: usb@01c14400 {
738 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
739 reg = <0x01c14400 0x100>;
740 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
741 clocks = <&usb_clk 6>, <&ahb_gates 2>;
748 compatible = "allwinner,sun4i-a10-spi";
749 reg = <0x01c17000 0x1000>;
750 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
751 clocks = <&ahb_gates 22>, <&spi2_clk>;
752 clock-names = "ahb", "mod";
753 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
754 <&dma SUN4I_DMA_DEDICATED 28>;
755 dma-names = "rx", "tx";
757 #address-cells = <1>;
761 ahci: sata@01c18000 {
762 compatible = "allwinner,sun4i-a10-ahci";
763 reg = <0x01c18000 0x1000>;
764 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
765 clocks = <&pll6 0>, <&ahb_gates 25>;
769 ehci1: usb@01c1c000 {
770 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
771 reg = <0x01c1c000 0x100>;
772 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
773 clocks = <&ahb_gates 3>;
779 ohci1: usb@01c1c400 {
780 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
781 reg = <0x01c1c400 0x100>;
782 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
783 clocks = <&usb_clk 7>, <&ahb_gates 4>;
790 compatible = "allwinner,sun4i-a10-spi";
791 reg = <0x01c1f000 0x1000>;
792 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
793 clocks = <&ahb_gates 23>, <&spi3_clk>;
794 clock-names = "ahb", "mod";
795 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
796 <&dma SUN4I_DMA_DEDICATED 30>;
797 dma-names = "rx", "tx";
799 #address-cells = <1>;
803 pio: pinctrl@01c20800 {
804 compatible = "allwinner,sun7i-a20-pinctrl";
805 reg = <0x01c20800 0x400>;
806 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
807 clocks = <&apb0_gates 5>;
809 interrupt-controller;
810 #interrupt-cells = <3>;
813 pwm0_pins_a: pwm0@0 {
814 allwinner,pins = "PB2";
815 allwinner,function = "pwm";
816 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
817 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
820 pwm1_pins_a: pwm1@0 {
821 allwinner,pins = "PI3";
822 allwinner,function = "pwm";
823 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
824 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
827 uart0_pins_a: uart0@0 {
828 allwinner,pins = "PB22", "PB23";
829 allwinner,function = "uart0";
830 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
831 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
834 uart2_pins_a: uart2@0 {
835 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
836 allwinner,function = "uart2";
837 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
838 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
841 uart3_pins_a: uart3@0 {
842 allwinner,pins = "PG6", "PG7", "PG8", "PG9";
843 allwinner,function = "uart3";
844 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
845 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
848 uart3_pins_b: uart3@1 {
849 allwinner,pins = "PH0", "PH1";
850 allwinner,function = "uart3";
851 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
852 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
855 uart4_pins_a: uart4@0 {
856 allwinner,pins = "PG10", "PG11";
857 allwinner,function = "uart4";
858 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
859 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
862 uart4_pins_b: uart4@1 {
863 allwinner,pins = "PH4", "PH5";
864 allwinner,function = "uart4";
865 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
866 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
869 uart5_pins_a: uart5@0 {
870 allwinner,pins = "PI10", "PI11";
871 allwinner,function = "uart5";
872 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
873 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
876 uart6_pins_a: uart6@0 {
877 allwinner,pins = "PI12", "PI13";
878 allwinner,function = "uart6";
879 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
880 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
883 uart7_pins_a: uart7@0 {
884 allwinner,pins = "PI20", "PI21";
885 allwinner,function = "uart7";
886 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
887 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
890 i2c0_pins_a: i2c0@0 {
891 allwinner,pins = "PB0", "PB1";
892 allwinner,function = "i2c0";
893 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
894 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
897 i2c1_pins_a: i2c1@0 {
898 allwinner,pins = "PB18", "PB19";
899 allwinner,function = "i2c1";
900 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
901 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
904 i2c2_pins_a: i2c2@0 {
905 allwinner,pins = "PB20", "PB21";
906 allwinner,function = "i2c2";
907 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
908 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
911 i2c3_pins_a: i2c3@0 {
912 allwinner,pins = "PI0", "PI1";
913 allwinner,function = "i2c3";
914 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
915 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
918 emac_pins_a: emac0@0 {
919 allwinner,pins = "PA0", "PA1", "PA2",
920 "PA3", "PA4", "PA5", "PA6",
921 "PA7", "PA8", "PA9", "PA10",
922 "PA11", "PA12", "PA13", "PA14",
924 allwinner,function = "emac";
925 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
926 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
929 clk_out_a_pins_a: clk_out_a@0 {
930 allwinner,pins = "PI12";
931 allwinner,function = "clk_out_a";
932 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
933 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
936 clk_out_b_pins_a: clk_out_b@0 {
937 allwinner,pins = "PI13";
938 allwinner,function = "clk_out_b";
939 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
940 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
943 gmac_pins_mii_a: gmac_mii@0 {
944 allwinner,pins = "PA0", "PA1", "PA2",
945 "PA3", "PA4", "PA5", "PA6",
946 "PA7", "PA8", "PA9", "PA10",
947 "PA11", "PA12", "PA13", "PA14",
949 allwinner,function = "gmac";
950 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
951 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
954 gmac_pins_rgmii_a: gmac_rgmii@0 {
955 allwinner,pins = "PA0", "PA1", "PA2",
956 "PA3", "PA4", "PA5", "PA6",
957 "PA7", "PA8", "PA10",
958 "PA11", "PA12", "PA13",
960 allwinner,function = "gmac";
962 * data lines in RGMII mode use DDR mode
963 * and need a higher signal drive strength
965 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
966 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
969 spi0_pins_a: spi0@0 {
970 allwinner,pins = "PI11", "PI12", "PI13";
971 allwinner,function = "spi0";
972 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
973 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
976 spi0_cs0_pins_a: spi0_cs0@0 {
977 allwinner,pins = "PI10";
978 allwinner,function = "spi0";
979 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
980 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
983 spi0_cs1_pins_a: spi0_cs1@0 {
984 allwinner,pins = "PI14";
985 allwinner,function = "spi0";
986 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
987 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
990 spi1_pins_a: spi1@0 {
991 allwinner,pins = "PI17", "PI18", "PI19";
992 allwinner,function = "spi1";
993 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
994 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
997 spi1_cs0_pins_a: spi1_cs0@0 {
998 allwinner,pins = "PI16";
999 allwinner,function = "spi1";
1000 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1001 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1004 spi2_pins_a: spi2@0 {
1005 allwinner,pins = "PC20", "PC21", "PC22";
1006 allwinner,function = "spi2";
1007 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1008 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1011 spi2_pins_b: spi2@1 {
1012 allwinner,pins = "PB15", "PB16", "PB17";
1013 allwinner,function = "spi2";
1014 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1015 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1018 spi2_cs0_pins_a: spi2_cs0@0 {
1019 allwinner,pins = "PC19";
1020 allwinner,function = "spi2";
1021 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1022 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1025 spi2_cs0_pins_b: spi2_cs0@1 {
1026 allwinner,pins = "PB14";
1027 allwinner,function = "spi2";
1028 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1029 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1032 mmc0_pins_a: mmc0@0 {
1033 allwinner,pins = "PF0", "PF1", "PF2",
1034 "PF3", "PF4", "PF5";
1035 allwinner,function = "mmc0";
1036 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
1037 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1040 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
1041 allwinner,pins = "PH1";
1042 allwinner,function = "gpio_in";
1043 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1044 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
1047 mmc2_pins_a: mmc2@0 {
1048 allwinner,pins = "PC6", "PC7", "PC8",
1049 "PC9", "PC10", "PC11";
1050 allwinner,function = "mmc2";
1051 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
1052 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
1055 mmc3_pins_a: mmc3@0 {
1056 allwinner,pins = "PI4", "PI5", "PI6",
1057 "PI7", "PI8", "PI9";
1058 allwinner,function = "mmc3";
1059 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
1060 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1063 ir0_rx_pins_a: ir0@0 {
1064 allwinner,pins = "PB4";
1065 allwinner,function = "ir0";
1066 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1067 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1070 ir0_tx_pins_a: ir0@1 {
1071 allwinner,pins = "PB3";
1072 allwinner,function = "ir0";
1073 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1074 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1077 ir1_rx_pins_a: ir1@0 {
1078 allwinner,pins = "PB23";
1079 allwinner,function = "ir1";
1080 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1081 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1084 ir1_tx_pins_a: ir1@1 {
1085 allwinner,pins = "PB22";
1086 allwinner,function = "ir1";
1087 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1088 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1091 ps20_pins_a: ps20@0 {
1092 allwinner,pins = "PI20", "PI21";
1093 allwinner,function = "ps2";
1094 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1095 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1098 ps21_pins_a: ps21@0 {
1099 allwinner,pins = "PH12", "PH13";
1100 allwinner,function = "ps2";
1101 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1102 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1107 compatible = "allwinner,sun4i-a10-timer";
1108 reg = <0x01c20c00 0x90>;
1109 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
1110 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
1111 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1112 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1113 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
1114 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1118 wdt: watchdog@01c20c90 {
1119 compatible = "allwinner,sun4i-a10-wdt";
1120 reg = <0x01c20c90 0x10>;
1124 compatible = "allwinner,sun7i-a20-rtc";
1125 reg = <0x01c20d00 0x20>;
1126 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1130 compatible = "allwinner,sun7i-a20-pwm";
1131 reg = <0x01c20e00 0xc>;
1134 status = "disabled";
1138 compatible = "allwinner,sun4i-a10-ir";
1139 clocks = <&apb0_gates 6>, <&ir0_clk>;
1140 clock-names = "apb", "ir";
1141 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1142 reg = <0x01c21800 0x40>;
1143 status = "disabled";
1147 compatible = "allwinner,sun4i-a10-ir";
1148 clocks = <&apb0_gates 7>, <&ir1_clk>;
1149 clock-names = "apb", "ir";
1150 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1151 reg = <0x01c21c00 0x40>;
1152 status = "disabled";
1155 lradc: lradc@01c22800 {
1156 compatible = "allwinner,sun4i-a10-lradc-keys";
1157 reg = <0x01c22800 0x100>;
1158 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1159 status = "disabled";
1162 sid: eeprom@01c23800 {
1163 compatible = "allwinner,sun7i-a20-sid";
1164 reg = <0x01c23800 0x200>;
1168 compatible = "allwinner,sun5i-a13-ts";
1169 reg = <0x01c25000 0x100>;
1170 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1171 #thermal-sensor-cells = <0>;
1174 uart0: serial@01c28000 {
1175 compatible = "snps,dw-apb-uart";
1176 reg = <0x01c28000 0x400>;
1177 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1180 clocks = <&apb1_gates 16>;
1181 status = "disabled";
1184 uart1: serial@01c28400 {
1185 compatible = "snps,dw-apb-uart";
1186 reg = <0x01c28400 0x400>;
1187 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1190 clocks = <&apb1_gates 17>;
1191 status = "disabled";
1194 uart2: serial@01c28800 {
1195 compatible = "snps,dw-apb-uart";
1196 reg = <0x01c28800 0x400>;
1197 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1200 clocks = <&apb1_gates 18>;
1201 status = "disabled";
1204 uart3: serial@01c28c00 {
1205 compatible = "snps,dw-apb-uart";
1206 reg = <0x01c28c00 0x400>;
1207 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1210 clocks = <&apb1_gates 19>;
1211 status = "disabled";
1214 uart4: serial@01c29000 {
1215 compatible = "snps,dw-apb-uart";
1216 reg = <0x01c29000 0x400>;
1217 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1220 clocks = <&apb1_gates 20>;
1221 status = "disabled";
1224 uart5: serial@01c29400 {
1225 compatible = "snps,dw-apb-uart";
1226 reg = <0x01c29400 0x400>;
1227 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1230 clocks = <&apb1_gates 21>;
1231 status = "disabled";
1234 uart6: serial@01c29800 {
1235 compatible = "snps,dw-apb-uart";
1236 reg = <0x01c29800 0x400>;
1237 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1240 clocks = <&apb1_gates 22>;
1241 status = "disabled";
1244 uart7: serial@01c29c00 {
1245 compatible = "snps,dw-apb-uart";
1246 reg = <0x01c29c00 0x400>;
1247 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1250 clocks = <&apb1_gates 23>;
1251 status = "disabled";
1254 i2c0: i2c@01c2ac00 {
1255 compatible = "allwinner,sun7i-a20-i2c",
1256 "allwinner,sun4i-a10-i2c";
1257 reg = <0x01c2ac00 0x400>;
1258 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1259 clocks = <&apb1_gates 0>;
1260 status = "disabled";
1261 #address-cells = <1>;
1265 i2c1: i2c@01c2b000 {
1266 compatible = "allwinner,sun7i-a20-i2c",
1267 "allwinner,sun4i-a10-i2c";
1268 reg = <0x01c2b000 0x400>;
1269 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1270 clocks = <&apb1_gates 1>;
1271 status = "disabled";
1272 #address-cells = <1>;
1276 i2c2: i2c@01c2b400 {
1277 compatible = "allwinner,sun7i-a20-i2c",
1278 "allwinner,sun4i-a10-i2c";
1279 reg = <0x01c2b400 0x400>;
1280 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1281 clocks = <&apb1_gates 2>;
1282 status = "disabled";
1283 #address-cells = <1>;
1287 i2c3: i2c@01c2b800 {
1288 compatible = "allwinner,sun7i-a20-i2c",
1289 "allwinner,sun4i-a10-i2c";
1290 reg = <0x01c2b800 0x400>;
1291 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1292 clocks = <&apb1_gates 3>;
1293 status = "disabled";
1294 #address-cells = <1>;
1298 i2c4: i2c@01c2c000 {
1299 compatible = "allwinner,sun7i-a20-i2c",
1300 "allwinner,sun4i-a10-i2c";
1301 reg = <0x01c2c000 0x400>;
1302 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1303 clocks = <&apb1_gates 15>;
1304 status = "disabled";
1305 #address-cells = <1>;
1309 gmac: ethernet@01c50000 {
1310 compatible = "allwinner,sun7i-a20-gmac";
1311 reg = <0x01c50000 0x10000>;
1312 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1313 interrupt-names = "macirq";
1314 clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
1315 clock-names = "stmmaceth", "allwinner_gmac_tx";
1318 snps,force_sf_dma_mode;
1319 status = "disabled";
1320 #address-cells = <1>;
1325 compatible = "allwinner,sun7i-a20-hstimer";
1326 reg = <0x01c60000 0x1000>;
1327 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1328 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1329 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1330 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1331 clocks = <&ahb_gates 28>;
1334 gic: interrupt-controller@01c81000 {
1335 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1336 reg = <0x01c81000 0x1000>,
1337 <0x01c82000 0x1000>,
1338 <0x01c84000 0x2000>,
1339 <0x01c86000 0x2000>;
1340 interrupt-controller;
1341 #interrupt-cells = <3>;
1342 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1345 ps20: ps2@01c2a000 {
1346 compatible = "allwinner,sun4i-a10-ps2";
1347 reg = <0x01c2a000 0x400>;
1348 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1349 clocks = <&apb1_gates 6>;
1350 status = "disabled";
1353 ps21: ps2@01c2a400 {
1354 compatible = "allwinner,sun4i-a10-ps2";
1355 reg = <0x01c2a400 0x400>;
1356 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1357 clocks = <&apb1_gates 7>;
1358 status = "disabled";