2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 /include/ "skeleton.dtsi"
17 interrupt-parent = <&gic>;
36 compatible = "arm,cortex-a7";
42 compatible = "arm,cortex-a7";
49 reg = <0x40000000 0x80000000>;
57 osc24M: clk@01c20050 {
59 compatible = "allwinner,sun4i-osc-clk";
60 reg = <0x01c20050 0x4>;
61 clock-frequency = <24000000>;
62 clock-output-names = "osc24M";
67 compatible = "fixed-clock";
68 clock-frequency = <32768>;
69 clock-output-names = "osc32k";
74 compatible = "allwinner,sun4i-pll1-clk";
75 reg = <0x01c20000 0x4>;
77 clock-output-names = "pll1";
82 compatible = "allwinner,sun4i-pll1-clk";
83 reg = <0x01c20018 0x4>;
85 clock-output-names = "pll4";
90 compatible = "allwinner,sun4i-pll5-clk";
91 reg = <0x01c20020 0x4>;
93 clock-output-names = "pll5_ddr", "pll5_other";
98 compatible = "allwinner,sun4i-pll6-clk";
99 reg = <0x01c20028 0x4>;
101 clock-output-names = "pll6_sata", "pll6_other", "pll6";
106 compatible = "allwinner,sun4i-cpu-clk";
107 reg = <0x01c20054 0x4>;
108 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
109 clock-output-names = "cpu";
114 compatible = "allwinner,sun4i-axi-clk";
115 reg = <0x01c20054 0x4>;
117 clock-output-names = "axi";
122 compatible = "allwinner,sun4i-ahb-clk";
123 reg = <0x01c20054 0x4>;
125 clock-output-names = "ahb";
128 ahb_gates: clk@01c20060 {
130 compatible = "allwinner,sun7i-a20-ahb-gates-clk";
131 reg = <0x01c20060 0x8>;
133 clock-output-names = "ahb_usb0", "ahb_ehci0",
134 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
135 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
136 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
137 "ahb_nand", "ahb_sdram", "ahb_ace",
138 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
139 "ahb_spi2", "ahb_spi3", "ahb_sata",
140 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
141 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
142 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
143 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
144 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
148 apb0: apb0@01c20054 {
150 compatible = "allwinner,sun4i-apb0-clk";
151 reg = <0x01c20054 0x4>;
153 clock-output-names = "apb0";
156 apb0_gates: clk@01c20068 {
158 compatible = "allwinner,sun7i-a20-apb0-gates-clk";
159 reg = <0x01c20068 0x4>;
161 clock-output-names = "apb0_codec", "apb0_spdif",
162 "apb0_ac97", "apb0_iis0", "apb0_iis1",
163 "apb0_pio", "apb0_ir0", "apb0_ir1",
164 "apb0_iis2", "apb0_keypad";
167 apb1_mux: apb1_mux@01c20058 {
169 compatible = "allwinner,sun4i-apb1-mux-clk";
170 reg = <0x01c20058 0x4>;
171 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
172 clock-output-names = "apb1_mux";
175 apb1: apb1@01c20058 {
177 compatible = "allwinner,sun4i-apb1-clk";
178 reg = <0x01c20058 0x4>;
179 clocks = <&apb1_mux>;
180 clock-output-names = "apb1";
183 apb1_gates: clk@01c2006c {
185 compatible = "allwinner,sun7i-a20-apb1-gates-clk";
186 reg = <0x01c2006c 0x4>;
188 clock-output-names = "apb1_i2c0", "apb1_i2c1",
189 "apb1_i2c2", "apb1_i2c3", "apb1_can",
190 "apb1_scr", "apb1_ps20", "apb1_ps21",
191 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
192 "apb1_uart2", "apb1_uart3", "apb1_uart4",
193 "apb1_uart5", "apb1_uart6", "apb1_uart7";
196 nand_clk: clk@01c20080 {
198 compatible = "allwinner,sun4i-mod0-clk";
199 reg = <0x01c20080 0x4>;
200 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
201 clock-output-names = "nand";
204 ms_clk: clk@01c20084 {
206 compatible = "allwinner,sun4i-mod0-clk";
207 reg = <0x01c20084 0x4>;
208 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
209 clock-output-names = "ms";
212 mmc0_clk: clk@01c20088 {
214 compatible = "allwinner,sun4i-mod0-clk";
215 reg = <0x01c20088 0x4>;
216 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
217 clock-output-names = "mmc0";
220 mmc1_clk: clk@01c2008c {
222 compatible = "allwinner,sun4i-mod0-clk";
223 reg = <0x01c2008c 0x4>;
224 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
225 clock-output-names = "mmc1";
228 mmc2_clk: clk@01c20090 {
230 compatible = "allwinner,sun4i-mod0-clk";
231 reg = <0x01c20090 0x4>;
232 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
233 clock-output-names = "mmc2";
236 mmc3_clk: clk@01c20094 {
238 compatible = "allwinner,sun4i-mod0-clk";
239 reg = <0x01c20094 0x4>;
240 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
241 clock-output-names = "mmc3";
244 ts_clk: clk@01c20098 {
246 compatible = "allwinner,sun4i-mod0-clk";
247 reg = <0x01c20098 0x4>;
248 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
249 clock-output-names = "ts";
252 ss_clk: clk@01c2009c {
254 compatible = "allwinner,sun4i-mod0-clk";
255 reg = <0x01c2009c 0x4>;
256 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
257 clock-output-names = "ss";
260 spi0_clk: clk@01c200a0 {
262 compatible = "allwinner,sun4i-mod0-clk";
263 reg = <0x01c200a0 0x4>;
264 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
265 clock-output-names = "spi0";
268 spi1_clk: clk@01c200a4 {
270 compatible = "allwinner,sun4i-mod0-clk";
271 reg = <0x01c200a4 0x4>;
272 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
273 clock-output-names = "spi1";
276 spi2_clk: clk@01c200a8 {
278 compatible = "allwinner,sun4i-mod0-clk";
279 reg = <0x01c200a8 0x4>;
280 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
281 clock-output-names = "spi2";
284 pata_clk: clk@01c200ac {
286 compatible = "allwinner,sun4i-mod0-clk";
287 reg = <0x01c200ac 0x4>;
288 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
289 clock-output-names = "pata";
292 ir0_clk: clk@01c200b0 {
294 compatible = "allwinner,sun4i-mod0-clk";
295 reg = <0x01c200b0 0x4>;
296 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
297 clock-output-names = "ir0";
300 ir1_clk: clk@01c200b4 {
302 compatible = "allwinner,sun4i-mod0-clk";
303 reg = <0x01c200b4 0x4>;
304 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
305 clock-output-names = "ir1";
308 spi3_clk: clk@01c200d4 {
310 compatible = "allwinner,sun4i-mod0-clk";
311 reg = <0x01c200d4 0x4>;
312 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
313 clock-output-names = "spi3";
316 mbus_clk: clk@01c2015c {
318 compatible = "allwinner,sun4i-mod0-clk";
319 reg = <0x01c2015c 0x4>;
320 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
321 clock-output-names = "mbus";
325 * The following two are dummy clocks, placeholders used in the gmac_tx
326 * clock. The gmac driver will choose one parent depending on the PHY
327 * interface mode, using clk_set_rate auto-reparenting.
328 * The actual TX clock rate is not controlled by the gmac_tx clock.
330 mii_phy_tx_clk: clk@2 {
332 compatible = "fixed-clock";
333 clock-frequency = <25000000>;
334 clock-output-names = "mii_phy_tx";
337 gmac_int_tx_clk: clk@3 {
339 compatible = "fixed-clock";
340 clock-frequency = <125000000>;
341 clock-output-names = "gmac_int_tx";
344 gmac_tx_clk: clk@01c20164 {
346 compatible = "allwinner,sun7i-a20-gmac-clk";
347 reg = <0x01c20164 0x4>;
348 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
349 clock-output-names = "gmac_tx";
353 * Dummy clock used by output clocks
357 compatible = "fixed-factor-clock";
361 clock-output-names = "osc24M_32k";
364 clk_out_a: clk@01c201f0 {
366 compatible = "allwinner,sun7i-a20-out-clk";
367 reg = <0x01c201f0 0x4>;
368 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
369 clock-output-names = "clk_out_a";
372 clk_out_b: clk@01c201f4 {
374 compatible = "allwinner,sun7i-a20-out-clk";
375 reg = <0x01c201f4 0x4>;
376 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
377 clock-output-names = "clk_out_b";
382 compatible = "simple-bus";
383 #address-cells = <1>;
387 emac: ethernet@01c0b000 {
388 compatible = "allwinner,sun4i-emac";
389 reg = <0x01c0b000 0x1000>;
390 interrupts = <0 55 4>;
391 clocks = <&ahb_gates 17>;
396 compatible = "allwinner,sun4i-mdio";
397 reg = <0x01c0b080 0x14>;
399 #address-cells = <1>;
403 pio: pinctrl@01c20800 {
404 compatible = "allwinner,sun7i-a20-pinctrl";
405 reg = <0x01c20800 0x400>;
406 interrupts = <0 28 4>;
407 clocks = <&apb0_gates 5>;
409 interrupt-controller;
410 #address-cells = <1>;
414 uart0_pins_a: uart0@0 {
415 allwinner,pins = "PB22", "PB23";
416 allwinner,function = "uart0";
417 allwinner,drive = <0>;
418 allwinner,pull = <0>;
421 uart2_pins_a: uart2@0 {
422 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
423 allwinner,function = "uart2";
424 allwinner,drive = <0>;
425 allwinner,pull = <0>;
428 uart6_pins_a: uart6@0 {
429 allwinner,pins = "PI12", "PI13";
430 allwinner,function = "uart6";
431 allwinner,drive = <0>;
432 allwinner,pull = <0>;
435 uart7_pins_a: uart7@0 {
436 allwinner,pins = "PI20", "PI21";
437 allwinner,function = "uart7";
438 allwinner,drive = <0>;
439 allwinner,pull = <0>;
442 i2c0_pins_a: i2c0@0 {
443 allwinner,pins = "PB0", "PB1";
444 allwinner,function = "i2c0";
445 allwinner,drive = <0>;
446 allwinner,pull = <0>;
449 i2c1_pins_a: i2c1@0 {
450 allwinner,pins = "PB18", "PB19";
451 allwinner,function = "i2c1";
452 allwinner,drive = <0>;
453 allwinner,pull = <0>;
456 i2c2_pins_a: i2c2@0 {
457 allwinner,pins = "PB20", "PB21";
458 allwinner,function = "i2c2";
459 allwinner,drive = <0>;
460 allwinner,pull = <0>;
463 emac_pins_a: emac0@0 {
464 allwinner,pins = "PA0", "PA1", "PA2",
465 "PA3", "PA4", "PA5", "PA6",
466 "PA7", "PA8", "PA9", "PA10",
467 "PA11", "PA12", "PA13", "PA14",
469 allwinner,function = "emac";
470 allwinner,drive = <0>;
471 allwinner,pull = <0>;
474 clk_out_a_pins_a: clk_out_a@0 {
475 allwinner,pins = "PI12";
476 allwinner,function = "clk_out_a";
477 allwinner,drive = <0>;
478 allwinner,pull = <0>;
481 clk_out_b_pins_a: clk_out_b@0 {
482 allwinner,pins = "PI13";
483 allwinner,function = "clk_out_b";
484 allwinner,drive = <0>;
485 allwinner,pull = <0>;
490 compatible = "allwinner,sun4i-timer";
491 reg = <0x01c20c00 0x90>;
492 interrupts = <0 22 4>,
501 wdt: watchdog@01c20c90 {
502 compatible = "allwinner,sun4i-wdt";
503 reg = <0x01c20c90 0x10>;
507 compatible = "allwinner,sun7i-a20-rtc";
508 reg = <0x01c20d00 0x20>;
509 interrupts = <0 24 1>;
512 sid: eeprom@01c23800 {
513 compatible = "allwinner,sun7i-a20-sid";
514 reg = <0x01c23800 0x200>;
518 compatible = "allwinner,sun4i-ts";
519 reg = <0x01c25000 0x100>;
520 interrupts = <0 29 4>;
523 uart0: serial@01c28000 {
524 compatible = "snps,dw-apb-uart";
525 reg = <0x01c28000 0x400>;
526 interrupts = <0 1 4>;
529 clocks = <&apb1_gates 16>;
533 uart1: serial@01c28400 {
534 compatible = "snps,dw-apb-uart";
535 reg = <0x01c28400 0x400>;
536 interrupts = <0 2 4>;
539 clocks = <&apb1_gates 17>;
543 uart2: serial@01c28800 {
544 compatible = "snps,dw-apb-uart";
545 reg = <0x01c28800 0x400>;
546 interrupts = <0 3 4>;
549 clocks = <&apb1_gates 18>;
553 uart3: serial@01c28c00 {
554 compatible = "snps,dw-apb-uart";
555 reg = <0x01c28c00 0x400>;
556 interrupts = <0 4 4>;
559 clocks = <&apb1_gates 19>;
563 uart4: serial@01c29000 {
564 compatible = "snps,dw-apb-uart";
565 reg = <0x01c29000 0x400>;
566 interrupts = <0 17 4>;
569 clocks = <&apb1_gates 20>;
573 uart5: serial@01c29400 {
574 compatible = "snps,dw-apb-uart";
575 reg = <0x01c29400 0x400>;
576 interrupts = <0 18 4>;
579 clocks = <&apb1_gates 21>;
583 uart6: serial@01c29800 {
584 compatible = "snps,dw-apb-uart";
585 reg = <0x01c29800 0x400>;
586 interrupts = <0 19 4>;
589 clocks = <&apb1_gates 22>;
593 uart7: serial@01c29c00 {
594 compatible = "snps,dw-apb-uart";
595 reg = <0x01c29c00 0x400>;
596 interrupts = <0 20 4>;
599 clocks = <&apb1_gates 23>;
604 compatible = "allwinner,sun4i-i2c";
605 reg = <0x01c2ac00 0x400>;
606 interrupts = <0 7 4>;
607 clocks = <&apb1_gates 0>;
608 clock-frequency = <100000>;
613 compatible = "allwinner,sun4i-i2c";
614 reg = <0x01c2b000 0x400>;
615 interrupts = <0 8 4>;
616 clocks = <&apb1_gates 1>;
617 clock-frequency = <100000>;
622 compatible = "allwinner,sun4i-i2c";
623 reg = <0x01c2b400 0x400>;
624 interrupts = <0 9 4>;
625 clocks = <&apb1_gates 2>;
626 clock-frequency = <100000>;
631 compatible = "allwinner,sun4i-i2c";
632 reg = <0x01c2b800 0x400>;
633 interrupts = <0 88 4>;
634 clocks = <&apb1_gates 3>;
635 clock-frequency = <100000>;
640 compatible = "allwinner,sun4i-i2c";
641 reg = <0x01c2bc00 0x400>;
642 interrupts = <0 89 4>;
643 clocks = <&apb1_gates 15>;
644 clock-frequency = <100000>;
648 gmac: ethernet@01c50000 {
649 compatible = "allwinner,sun7i-a20-gmac";
650 reg = <0x01c50000 0x10000>;
651 interrupts = <0 85 4>;
652 interrupt-names = "macirq";
653 clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
654 clock-names = "stmmaceth", "allwinner_gmac_tx";
657 snps,force_sf_dma_mode;
659 #address-cells = <1>;
664 compatible = "allwinner,sun7i-a20-hstimer";
665 reg = <0x01c60000 0x1000>;
666 interrupts = <0 81 1>,
670 clocks = <&ahb_gates 28>;
673 gic: interrupt-controller@01c81000 {
674 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
675 reg = <0x01c81000 0x1000>,
679 interrupt-controller;
680 #interrupt-cells = <3>;
681 interrupts = <1 9 0xf04>;