2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include "skeleton.dtsi"
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 #include <dt-bindings/pinctrl/sun4i-a10.h>
52 interrupt-parent = <&gic>;
59 simplefb_lcd: framebuffer@0 {
60 compatible = "allwinner,simple-framebuffer",
62 allwinner,pipeline = "de_be0-lcd0";
69 compatible = "arm,armv7-timer";
70 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
71 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
72 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
73 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
74 clock-frequency = <24000000>;
75 arm,cpu-registers-not-fw-configured;
79 enable-method = "allwinner,sun8i-a23";
84 compatible = "arm,cortex-a7";
90 compatible = "arm,cortex-a7";
103 compatible = "fixed-clock";
104 clock-frequency = <24000000>;
105 clock-output-names = "osc24M";
110 compatible = "fixed-clock";
111 clock-frequency = <32768>;
112 clock-output-names = "osc32k";
117 compatible = "allwinner,sun8i-a23-pll1-clk";
118 reg = <0x01c20000 0x4>;
120 clock-output-names = "pll1";
123 /* dummy clock until actually implemented */
126 compatible = "fixed-clock";
127 clock-frequency = <0>;
128 clock-output-names = "pll5";
133 compatible = "allwinner,sun6i-a31-pll6-clk";
134 reg = <0x01c20028 0x4>;
136 clock-output-names = "pll6";
140 compatible = "fixed-factor-clock";
145 clock-output-names = "pll6-2x";
148 cpu: cpu_clk@01c20050 {
150 compatible = "allwinner,sun4i-a10-cpu-clk";
151 reg = <0x01c20050 0x4>;
154 * PLL1 is listed twice here.
155 * While it looks suspicious, it's actually documented
156 * that way both in the datasheet and in the code from
159 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
160 clock-output-names = "cpu";
163 axi: axi_clk@01c20050 {
165 compatible = "allwinner,sun8i-a23-axi-clk";
166 reg = <0x01c20050 0x4>;
168 clock-output-names = "axi";
171 ahb1: ahb1_clk@01c20054 {
173 compatible = "allwinner,sun6i-a31-ahb1-clk";
174 reg = <0x01c20054 0x4>;
175 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
176 clock-output-names = "ahb1";
179 apb1: apb1_clk@01c20054 {
181 compatible = "allwinner,sun4i-a10-apb0-clk";
182 reg = <0x01c20054 0x4>;
184 clock-output-names = "apb1";
187 apb1_gates: clk@01c20068 {
189 compatible = "allwinner,sun8i-a23-apb1-gates-clk";
190 reg = <0x01c20068 0x4>;
192 clock-indices = <0>, <5>,
194 clock-output-names = "apb1_codec", "apb1_pio",
195 "apb1_daudio0", "apb1_daudio1";
200 compatible = "allwinner,sun4i-a10-apb1-clk";
201 reg = <0x01c20058 0x4>;
202 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
203 clock-output-names = "apb2";
206 apb2_gates: clk@01c2006c {
208 compatible = "allwinner,sun8i-a23-apb2-gates-clk";
209 reg = <0x01c2006c 0x4>;
211 clock-indices = <0>, <1>,
215 clock-output-names = "apb2_i2c0", "apb2_i2c1",
216 "apb2_i2c2", "apb2_uart0",
217 "apb2_uart1", "apb2_uart2",
218 "apb2_uart3", "apb2_uart4";
221 mmc0_clk: clk@01c20088 {
223 compatible = "allwinner,sun4i-a10-mmc-clk";
224 reg = <0x01c20088 0x4>;
225 clocks = <&osc24M>, <&pll6>;
226 clock-output-names = "mmc0",
231 mmc1_clk: clk@01c2008c {
233 compatible = "allwinner,sun4i-a10-mmc-clk";
234 reg = <0x01c2008c 0x4>;
235 clocks = <&osc24M>, <&pll6>;
236 clock-output-names = "mmc1",
241 mmc2_clk: clk@01c20090 {
243 compatible = "allwinner,sun4i-a10-mmc-clk";
244 reg = <0x01c20090 0x4>;
245 clocks = <&osc24M>, <&pll6>;
246 clock-output-names = "mmc2",
251 usb_clk: clk@01c200cc {
254 compatible = "allwinner,sun8i-a23-usb-clk";
255 reg = <0x01c200cc 0x4>;
257 clock-output-names = "usb_phy0", "usb_phy1", "usb_hsic",
258 "usb_hsic_12M", "usb_ohci0";
263 compatible = "simple-bus";
264 #address-cells = <1>;
268 dma: dma-controller@01c02000 {
269 compatible = "allwinner,sun8i-a23-dma";
270 reg = <0x01c02000 0x1000>;
271 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
272 clocks = <&ahb1_gates 6>;
273 resets = <&ahb1_rst 6>;
278 compatible = "allwinner,sun5i-a13-mmc";
279 reg = <0x01c0f000 0x1000>;
280 clocks = <&ahb1_gates 8>,
288 resets = <&ahb1_rst 8>;
290 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
292 #address-cells = <1>;
297 compatible = "allwinner,sun5i-a13-mmc";
298 reg = <0x01c10000 0x1000>;
299 clocks = <&ahb1_gates 9>,
307 resets = <&ahb1_rst 9>;
309 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
311 #address-cells = <1>;
316 compatible = "allwinner,sun5i-a13-mmc";
317 reg = <0x01c11000 0x1000>;
318 clocks = <&ahb1_gates 10>,
326 resets = <&ahb1_rst 10>;
328 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
330 #address-cells = <1>;
334 ehci0: usb@01c1a000 {
335 compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
336 reg = <0x01c1a000 0x100>;
337 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&ahb1_gates 26>;
339 resets = <&ahb1_rst 26>;
345 ohci0: usb@01c1a400 {
346 compatible = "allwinner,sun8i-a23-ohci", "generic-ohci";
347 reg = <0x01c1a400 0x100>;
348 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&ahb1_gates 29>, <&usb_clk 16>;
350 resets = <&ahb1_rst 29>;
356 pio: pinctrl@01c20800 {
357 /* compatible gets set in SoC specific dtsi file */
358 reg = <0x01c20800 0x400>;
359 /* interrupts get set in SoC specific dtsi file */
360 clocks = <&apb1_gates 5>;
362 interrupt-controller;
363 #interrupt-cells = <3>;
366 uart0_pins_a: uart0@0 {
367 allwinner,pins = "PF2", "PF4";
368 allwinner,function = "uart0";
369 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
370 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
373 mmc0_pins_a: mmc0@0 {
374 allwinner,pins = "PF0", "PF1", "PF2",
376 allwinner,function = "mmc0";
377 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
378 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
381 mmc1_pins_a: mmc1@0 {
382 allwinner,pins = "PG0", "PG1", "PG2",
384 allwinner,function = "mmc1";
385 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
386 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
389 mmc2_8bit_pins: mmc2_8bit {
390 allwinner,pins = "PC5", "PC6", "PC8",
391 "PC9", "PC10", "PC11",
392 "PC12", "PC13", "PC14",
394 allwinner,function = "mmc2";
395 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
396 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
400 allwinner,pins = "PH0";
401 allwinner,function = "pwm0";
402 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
403 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
406 i2c0_pins_a: i2c0@0 {
407 allwinner,pins = "PH2", "PH3";
408 allwinner,function = "i2c0";
409 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
410 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
413 i2c1_pins_a: i2c1@0 {
414 allwinner,pins = "PH4", "PH5";
415 allwinner,function = "i2c1";
416 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
417 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
420 i2c2_pins_a: i2c2@0 {
421 allwinner,pins = "PE12", "PE13";
422 allwinner,function = "i2c2";
423 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
424 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
428 ahb1_rst: reset@01c202c0 {
430 compatible = "allwinner,sun6i-a31-clock-reset";
431 reg = <0x01c202c0 0xc>;
434 apb1_rst: reset@01c202d0 {
436 compatible = "allwinner,sun6i-a31-clock-reset";
437 reg = <0x01c202d0 0x4>;
440 apb2_rst: reset@01c202d8 {
442 compatible = "allwinner,sun6i-a31-clock-reset";
443 reg = <0x01c202d8 0x4>;
447 compatible = "allwinner,sun4i-a10-timer";
448 reg = <0x01c20c00 0xa0>;
449 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
450 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
454 wdt0: watchdog@01c20ca0 {
455 compatible = "allwinner,sun6i-a31-wdt";
456 reg = <0x01c20ca0 0x20>;
457 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
461 compatible = "allwinner,sun7i-a20-pwm";
462 reg = <0x01c21400 0xc>;
468 lradc: lradc@01c22800 {
469 compatible = "allwinner,sun4i-a10-lradc-keys";
470 reg = <0x01c22800 0x100>;
471 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
475 uart0: serial@01c28000 {
476 compatible = "snps,dw-apb-uart";
477 reg = <0x01c28000 0x400>;
478 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&apb2_gates 16>;
482 resets = <&apb2_rst 16>;
483 dmas = <&dma 6>, <&dma 6>;
484 dma-names = "rx", "tx";
488 uart1: serial@01c28400 {
489 compatible = "snps,dw-apb-uart";
490 reg = <0x01c28400 0x400>;
491 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&apb2_gates 17>;
495 resets = <&apb2_rst 17>;
496 dmas = <&dma 7>, <&dma 7>;
497 dma-names = "rx", "tx";
501 uart2: serial@01c28800 {
502 compatible = "snps,dw-apb-uart";
503 reg = <0x01c28800 0x400>;
504 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
507 clocks = <&apb2_gates 18>;
508 resets = <&apb2_rst 18>;
509 dmas = <&dma 8>, <&dma 8>;
510 dma-names = "rx", "tx";
514 uart3: serial@01c28c00 {
515 compatible = "snps,dw-apb-uart";
516 reg = <0x01c28c00 0x400>;
517 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
520 clocks = <&apb2_gates 19>;
521 resets = <&apb2_rst 19>;
522 dmas = <&dma 9>, <&dma 9>;
523 dma-names = "rx", "tx";
527 uart4: serial@01c29000 {
528 compatible = "snps,dw-apb-uart";
529 reg = <0x01c29000 0x400>;
530 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&apb2_gates 20>;
534 resets = <&apb2_rst 20>;
535 dmas = <&dma 10>, <&dma 10>;
536 dma-names = "rx", "tx";
541 compatible = "allwinner,sun6i-a31-i2c";
542 reg = <0x01c2ac00 0x400>;
543 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
544 clocks = <&apb2_gates 0>;
545 resets = <&apb2_rst 0>;
547 #address-cells = <1>;
552 compatible = "allwinner,sun6i-a31-i2c";
553 reg = <0x01c2b000 0x400>;
554 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
555 clocks = <&apb2_gates 1>;
556 resets = <&apb2_rst 1>;
558 #address-cells = <1>;
563 compatible = "allwinner,sun6i-a31-i2c";
564 reg = <0x01c2b400 0x400>;
565 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&apb2_gates 2>;
567 resets = <&apb2_rst 2>;
569 #address-cells = <1>;
573 gic: interrupt-controller@01c81000 {
574 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
575 reg = <0x01c81000 0x1000>,
579 interrupt-controller;
580 #interrupt-cells = <3>;
581 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
585 compatible = "allwinner,sun6i-a31-rtc";
586 reg = <0x01f00000 0x54>;
587 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
588 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
591 nmi_intc: interrupt-controller@01f00c0c {
592 compatible = "allwinner,sun6i-a31-sc-nmi";
593 interrupt-controller;
594 #interrupt-cells = <2>;
595 reg = <0x01f00c0c 0x38>;
596 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
600 compatible = "allwinner,sun8i-a23-prcm";
601 reg = <0x01f01400 0x200>;
604 compatible = "fixed-factor-clock";
609 clock-output-names = "ar100";
613 compatible = "fixed-factor-clock";
618 clock-output-names = "ahb0";
622 compatible = "allwinner,sun8i-a23-apb0-clk";
625 clock-output-names = "apb0";
628 apb0_gates: apb0_gates_clk {
629 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
632 clock-output-names = "apb0_pio", "apb0_timer",
633 "apb0_rsb", "apb0_uart",
638 compatible = "allwinner,sun6i-a31-clock-reset";
644 compatible = "allwinner,sun8i-a23-cpuconfig";
645 reg = <0x01f01c00 0x300>;
648 r_uart: serial@01f02800 {
649 compatible = "snps,dw-apb-uart";
650 reg = <0x01f02800 0x400>;
651 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
654 clocks = <&apb0_gates 4>;
655 resets = <&apb0_rst 4>;
659 r_pio: pinctrl@01f02c00 {
660 compatible = "allwinner,sun8i-a23-r-pinctrl";
661 reg = <0x01f02c00 0x400>;
662 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
663 clocks = <&apb0_gates 0>;
664 resets = <&apb0_rst 0>;
666 interrupt-controller;
667 #interrupt-cells = <3>;
668 #address-cells = <1>;
673 allwinner,pins = "PL0", "PL1";
674 allwinner,function = "s_rsb";
675 allwinner,drive = <SUN4I_PINCTRL_20_MA>;
676 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
679 r_uart_pins_a: r_uart@0 {
680 allwinner,pins = "PL2", "PL3";
681 allwinner,function = "s_uart";
682 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
683 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
687 r_rsb: rsb@01f03400 {
688 compatible = "allwinner,sun8i-a23-rsb";
689 reg = <0x01f03400 0x400>;
690 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
691 clocks = <&apb0_gates 3>;
692 clock-frequency = <3000000>;
693 resets = <&apb0_rst 3>;
694 pinctrl-names = "default";
695 pinctrl-0 = <&r_rsb_pins>;
697 #address-cells = <1>;