2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include "skeleton.dtsi"
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 #include <dt-bindings/pinctrl/sun4i-a10.h>
52 interrupt-parent = <&gic>;
60 compatible = "allwinner,simple-framebuffer",
62 allwinner,pipeline = "de_be0-lcd0";
69 compatible = "arm,armv7-timer";
70 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
71 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
72 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
73 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
74 clock-frequency = <24000000>;
75 arm,cpu-registers-not-fw-configured;
79 enable-method = "allwinner,sun8i-a23";
84 compatible = "arm,cortex-a7";
90 compatible = "arm,cortex-a7";
103 compatible = "fixed-clock";
104 clock-frequency = <24000000>;
105 clock-output-names = "osc24M";
110 compatible = "fixed-clock";
111 clock-frequency = <32768>;
112 clock-output-names = "osc32k";
117 compatible = "allwinner,sun8i-a23-pll1-clk";
118 reg = <0x01c20000 0x4>;
120 clock-output-names = "pll1";
123 /* dummy clock until actually implemented */
126 compatible = "fixed-clock";
127 clock-frequency = <0>;
128 clock-output-names = "pll5";
133 compatible = "allwinner,sun6i-a31-pll6-clk";
134 reg = <0x01c20028 0x4>;
136 clock-output-names = "pll6", "pll6x2";
139 cpu: cpu_clk@01c20050 {
141 compatible = "allwinner,sun4i-a10-cpu-clk";
142 reg = <0x01c20050 0x4>;
145 * PLL1 is listed twice here.
146 * While it looks suspicious, it's actually documented
147 * that way both in the datasheet and in the code from
150 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
151 clock-output-names = "cpu";
154 axi: axi_clk@01c20050 {
156 compatible = "allwinner,sun8i-a23-axi-clk";
157 reg = <0x01c20050 0x4>;
159 clock-output-names = "axi";
162 ahb1: ahb1_clk@01c20054 {
164 compatible = "allwinner,sun6i-a31-ahb1-clk";
165 reg = <0x01c20054 0x4>;
166 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
167 clock-output-names = "ahb1";
170 apb1: apb1_clk@01c20054 {
172 compatible = "allwinner,sun4i-a10-apb0-clk";
173 reg = <0x01c20054 0x4>;
175 clock-output-names = "apb1";
178 ahb1_gates: clk@01c20060 {
180 compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
181 reg = <0x01c20060 0x8>;
183 clock-output-names = "ahb1_mipidsi", "ahb1_dma",
184 "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
185 "ahb1_nand", "ahb1_sdram",
186 "ahb1_hstimer", "ahb1_spi0",
187 "ahb1_spi1", "ahb1_otg", "ahb1_ehci",
188 "ahb1_ohci", "ahb1_ve", "ahb1_lcd",
189 "ahb1_csi", "ahb1_be", "ahb1_fe",
190 "ahb1_gpu", "ahb1_spinlock",
194 apb1_gates: clk@01c20068 {
196 compatible = "allwinner,sun8i-a23-apb1-gates-clk";
197 reg = <0x01c20068 0x4>;
199 clock-output-names = "apb1_codec", "apb1_pio",
200 "apb1_daudio0", "apb1_daudio1";
205 compatible = "allwinner,sun4i-a10-apb1-clk";
206 reg = <0x01c20058 0x4>;
207 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
208 clock-output-names = "apb2";
211 apb2_gates: clk@01c2006c {
213 compatible = "allwinner,sun8i-a23-apb2-gates-clk";
214 reg = <0x01c2006c 0x4>;
216 clock-output-names = "apb2_i2c0", "apb2_i2c1",
217 "apb2_i2c2", "apb2_uart0",
218 "apb2_uart1", "apb2_uart2",
219 "apb2_uart3", "apb2_uart4";
222 mmc0_clk: clk@01c20088 {
224 compatible = "allwinner,sun4i-a10-mmc-clk";
225 reg = <0x01c20088 0x4>;
226 clocks = <&osc24M>, <&pll6 0>;
227 clock-output-names = "mmc0",
232 mmc1_clk: clk@01c2008c {
234 compatible = "allwinner,sun4i-a10-mmc-clk";
235 reg = <0x01c2008c 0x4>;
236 clocks = <&osc24M>, <&pll6 0>;
237 clock-output-names = "mmc1",
242 mmc2_clk: clk@01c20090 {
244 compatible = "allwinner,sun4i-a10-mmc-clk";
245 reg = <0x01c20090 0x4>;
246 clocks = <&osc24M>, <&pll6 0>;
247 clock-output-names = "mmc2",
252 usb_clk: clk@01c200cc {
255 compatible = "allwinner,sun8i-a23-usb-clk";
256 reg = <0x01c200cc 0x4>;
258 clock-output-names = "usb_phy0", "usb_phy1", "usb_hsic",
259 "usb_hsic_12M", "usb_ohci0";
264 compatible = "simple-bus";
265 #address-cells = <1>;
269 dma: dma-controller@01c02000 {
270 compatible = "allwinner,sun8i-a23-dma";
271 reg = <0x01c02000 0x1000>;
272 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
273 clocks = <&ahb1_gates 6>;
274 resets = <&ahb1_rst 6>;
279 compatible = "allwinner,sun5i-a13-mmc";
280 reg = <0x01c0f000 0x1000>;
281 clocks = <&ahb1_gates 8>,
289 resets = <&ahb1_rst 8>;
291 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
293 #address-cells = <1>;
298 compatible = "allwinner,sun5i-a13-mmc";
299 reg = <0x01c10000 0x1000>;
300 clocks = <&ahb1_gates 9>,
308 resets = <&ahb1_rst 9>;
310 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
312 #address-cells = <1>;
317 compatible = "allwinner,sun5i-a13-mmc";
318 reg = <0x01c11000 0x1000>;
319 clocks = <&ahb1_gates 10>,
327 resets = <&ahb1_rst 10>;
329 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
331 #address-cells = <1>;
335 ehci0: usb@01c1a000 {
336 compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
337 reg = <0x01c1a000 0x100>;
338 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
339 clocks = <&ahb1_gates 26>;
340 resets = <&ahb1_rst 26>;
346 ohci0: usb@01c1a400 {
347 compatible = "allwinner,sun8i-a23-ohci", "generic-ohci";
348 reg = <0x01c1a400 0x100>;
349 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&ahb1_gates 29>, <&usb_clk 16>;
351 resets = <&ahb1_rst 29>;
357 pio: pinctrl@01c20800 {
358 /* compatible gets set in SoC specific dtsi file */
359 reg = <0x01c20800 0x400>;
360 /* interrupts get set in SoC specific dtsi file */
361 clocks = <&apb1_gates 5>;
363 interrupt-controller;
364 #interrupt-cells = <3>;
367 uart0_pins_a: uart0@0 {
368 allwinner,pins = "PF2", "PF4";
369 allwinner,function = "uart0";
370 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
371 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
374 mmc0_pins_a: mmc0@0 {
375 allwinner,pins = "PF0", "PF1", "PF2",
377 allwinner,function = "mmc0";
378 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
379 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
382 mmc1_pins_a: mmc1@0 {
383 allwinner,pins = "PG0", "PG1", "PG2",
385 allwinner,function = "mmc1";
386 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
387 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
390 mmc2_8bit_pins: mmc2_8bit {
391 allwinner,pins = "PC5", "PC6", "PC8",
392 "PC9", "PC10", "PC11",
393 "PC12", "PC13", "PC14",
395 allwinner,function = "mmc2";
396 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
397 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
400 i2c0_pins_a: i2c0@0 {
401 allwinner,pins = "PH2", "PH3";
402 allwinner,function = "i2c0";
403 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
404 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
407 i2c1_pins_a: i2c1@0 {
408 allwinner,pins = "PH4", "PH5";
409 allwinner,function = "i2c1";
410 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
411 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
414 i2c2_pins_a: i2c2@0 {
415 allwinner,pins = "PE12", "PE13";
416 allwinner,function = "i2c2";
417 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
418 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
422 ahb1_rst: reset@01c202c0 {
424 compatible = "allwinner,sun6i-a31-clock-reset";
425 reg = <0x01c202c0 0xc>;
428 apb1_rst: reset@01c202d0 {
430 compatible = "allwinner,sun6i-a31-clock-reset";
431 reg = <0x01c202d0 0x4>;
434 apb2_rst: reset@01c202d8 {
436 compatible = "allwinner,sun6i-a31-clock-reset";
437 reg = <0x01c202d8 0x4>;
441 compatible = "allwinner,sun4i-a10-timer";
442 reg = <0x01c20c00 0xa0>;
443 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
448 wdt0: watchdog@01c20ca0 {
449 compatible = "allwinner,sun6i-a31-wdt";
450 reg = <0x01c20ca0 0x20>;
451 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
454 lradc: lradc@01c22800 {
455 compatible = "allwinner,sun4i-a10-lradc-keys";
456 reg = <0x01c22800 0x100>;
457 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
461 uart0: serial@01c28000 {
462 compatible = "snps,dw-apb-uart";
463 reg = <0x01c28000 0x400>;
464 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
467 clocks = <&apb2_gates 16>;
468 resets = <&apb2_rst 16>;
469 dmas = <&dma 6>, <&dma 6>;
470 dma-names = "rx", "tx";
474 uart1: serial@01c28400 {
475 compatible = "snps,dw-apb-uart";
476 reg = <0x01c28400 0x400>;
477 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
480 clocks = <&apb2_gates 17>;
481 resets = <&apb2_rst 17>;
482 dmas = <&dma 7>, <&dma 7>;
483 dma-names = "rx", "tx";
487 uart2: serial@01c28800 {
488 compatible = "snps,dw-apb-uart";
489 reg = <0x01c28800 0x400>;
490 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
493 clocks = <&apb2_gates 18>;
494 resets = <&apb2_rst 18>;
495 dmas = <&dma 8>, <&dma 8>;
496 dma-names = "rx", "tx";
500 uart3: serial@01c28c00 {
501 compatible = "snps,dw-apb-uart";
502 reg = <0x01c28c00 0x400>;
503 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
506 clocks = <&apb2_gates 19>;
507 resets = <&apb2_rst 19>;
508 dmas = <&dma 9>, <&dma 9>;
509 dma-names = "rx", "tx";
513 uart4: serial@01c29000 {
514 compatible = "snps,dw-apb-uart";
515 reg = <0x01c29000 0x400>;
516 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
519 clocks = <&apb2_gates 20>;
520 resets = <&apb2_rst 20>;
521 dmas = <&dma 10>, <&dma 10>;
522 dma-names = "rx", "tx";
527 compatible = "allwinner,sun6i-a31-i2c";
528 reg = <0x01c2ac00 0x400>;
529 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&apb2_gates 0>;
531 resets = <&apb2_rst 0>;
533 #address-cells = <1>;
538 compatible = "allwinner,sun6i-a31-i2c";
539 reg = <0x01c2b000 0x400>;
540 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
541 clocks = <&apb2_gates 1>;
542 resets = <&apb2_rst 1>;
544 #address-cells = <1>;
549 compatible = "allwinner,sun6i-a31-i2c";
550 reg = <0x01c2b400 0x400>;
551 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
552 clocks = <&apb2_gates 2>;
553 resets = <&apb2_rst 2>;
555 #address-cells = <1>;
559 gic: interrupt-controller@01c81000 {
560 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
561 reg = <0x01c81000 0x1000>,
565 interrupt-controller;
566 #interrupt-cells = <3>;
567 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
571 compatible = "allwinner,sun6i-a31-rtc";
572 reg = <0x01f00000 0x54>;
573 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
574 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
578 compatible = "allwinner,sun8i-a23-prcm";
579 reg = <0x01f01400 0x200>;
582 compatible = "fixed-factor-clock";
587 clock-output-names = "ar100";
591 compatible = "fixed-factor-clock";
596 clock-output-names = "ahb0";
600 compatible = "allwinner,sun8i-a23-apb0-clk";
603 clock-output-names = "apb0";
606 apb0_gates: apb0_gates_clk {
607 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
610 clock-output-names = "apb0_pio", "apb0_timer",
611 "apb0_rsb", "apb0_uart",
616 compatible = "allwinner,sun6i-a31-clock-reset";
622 compatible = "allwinner,sun8i-a23-cpuconfig";
623 reg = <0x01f01c00 0x300>;
626 r_uart: serial@01f02800 {
627 compatible = "snps,dw-apb-uart";
628 reg = <0x01f02800 0x400>;
629 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&apb0_gates 4>;
633 resets = <&apb0_rst 4>;
637 r_pio: pinctrl@01f02c00 {
638 compatible = "allwinner,sun8i-a23-r-pinctrl";
639 reg = <0x01f02c00 0x400>;
640 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
641 clocks = <&apb0_gates 0>;
642 resets = <&apb0_rst 0>;
644 interrupt-controller;
645 #address-cells = <1>;
649 r_uart_pins_a: r_uart@0 {
650 allwinner,pins = "PL2", "PL3";
651 allwinner,function = "s_uart";
652 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
653 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;