arch/arm/boot/dts/sun8i-a23-a33.dtsi

   1 /*
   2  * Copyright 2014 Chen-Yu Tsai
   3  *
   4  * Chen-Yu Tsai <wens@csie.org>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include "skeleton.dtsi"
  46
  47 #include <dt-bindings/interrupt-controller/arm-gic.h>
  48
  49 #include <dt-bindings/pinctrl/sun4i-a10.h>
  50
  51 / {
  52         interrupt-parent = <&gic>;
  53
  54         chosen {
  55                 #address-cells = <1>;
  56                 #size-cells = <1>;
  57                 ranges;
  58
  59                 simplefb_lcd: framebuffer@0 {
  60                         compatible = "allwinner,simple-framebuffer",
  61                                      "simple-framebuffer";
  62                         allwinner,pipeline = "de_be0-lcd0";
  63                         clocks = <&pll6>;
  64                         status = "disabled";
  65                 };
  66         };
  67
  68         timer {
  69                 compatible = "arm,armv7-timer";
  70                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  71                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  72                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  73                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  74                 clock-frequency = <24000000>;
  75                 arm,cpu-registers-not-fw-configured;
  76         };
  77
  78         cpus {
  79                 enable-method = "allwinner,sun8i-a23";
  80                 #address-cells = <1>;
  81                 #size-cells = <0>;
  82
  83                 cpu@0 {
  84                         compatible = "arm,cortex-a7";
  85                         device_type = "cpu";
  86                         reg = <0>;
  87                 };
  88
  89                 cpu@1 {
  90                         compatible = "arm,cortex-a7";
  91                         device_type = "cpu";
  92                         reg = <1>;
  93                 };
  94         };
  95
  96         clocks {
  97                 #address-cells = <1>;
  98                 #size-cells = <1>;
  99                 ranges;
 100
 101                 osc24M: osc24M_clk {
 102                         #clock-cells = <0>;
 103                         compatible = "fixed-clock";
 104                         clock-frequency = <24000000>;
 105                         clock-output-names = "osc24M";
 106                 };
 107
 108                 osc32k: osc32k_clk {
 109                         #clock-cells = <0>;
 110                         compatible = "fixed-clock";
 111                         clock-frequency = <32768>;
 112                         clock-output-names = "osc32k";
 113                 };
 114
 115                 pll1: clk@01c20000 {
 116                         #clock-cells = <0>;
 117                         compatible = "allwinner,sun8i-a23-pll1-clk";
 118                         reg = <0x01c20000 0x4>;
 119                         clocks = <&osc24M>;
 120                         clock-output-names = "pll1";
 121                 };
 122
 123                 /* dummy clock until actually implemented */
 124                 pll5: pll5_clk {
 125                         #clock-cells = <0>;
 126                         compatible = "fixed-clock";
 127                         clock-frequency = <0>;
 128                         clock-output-names = "pll5";
 129                 };
 130
 131                 pll6: clk@01c20028 {
 132                         #clock-cells = <0>;
 133                         compatible = "allwinner,sun6i-a31-pll6-clk";
 134                         reg = <0x01c20028 0x4>;
 135                         clocks = <&osc24M>;
 136                         clock-output-names = "pll6";
 137                 };
 138
 139                 pll6x2: pll6x2_clk {
 140                         compatible = "fixed-factor-clock";
 141                         #clock-cells = <0>;
 142                         clock-div = <1>;
 143                         clock-mult = <2>;
 144                         clocks = <&pll6>;
 145                         clock-output-names = "pll6-2x";
 146                 };
 147
 148                 cpu: cpu_clk@01c20050 {
 149                         #clock-cells = <0>;
 150                         compatible = "allwinner,sun4i-a10-cpu-clk";
 151                         reg = <0x01c20050 0x4>;
 152
 153                         /*
 154                          * PLL1 is listed twice here.
 155                          * While it looks suspicious, it's actually documented
 156                          * that way both in the datasheet and in the code from
 157                          * Allwinner.
 158                          */
 159                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
 160                         clock-output-names = "cpu";
 161                 };
 162
 163                 axi: axi_clk@01c20050 {
 164                         #clock-cells = <0>;
 165                         compatible = "allwinner,sun8i-a23-axi-clk";
 166                         reg = <0x01c20050 0x4>;
 167                         clocks = <&cpu>;
 168                         clock-output-names = "axi";
 169                 };
 170
 171                 ahb1: ahb1_clk@01c20054 {
 172                         #clock-cells = <0>;
 173                         compatible = "allwinner,sun6i-a31-ahb1-clk";
 174                         reg = <0x01c20054 0x4>;
 175                         clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
 176                         clock-output-names = "ahb1";
 177                 };
 178
 179                 apb1: apb1_clk@01c20054 {
 180                         #clock-cells = <0>;
 181                         compatible = "allwinner,sun4i-a10-apb0-clk";
 182                         reg = <0x01c20054 0x4>;
 183                         clocks = <&ahb1>;
 184                         clock-output-names = "apb1";
 185                 };
 186
 187                 apb1_gates: clk@01c20068 {
 188                         #clock-cells = <1>;
 189                         compatible = "allwinner,sun8i-a23-apb1-gates-clk";
 190                         reg = <0x01c20068 0x4>;
 191                         clocks = <&apb1>;
 192                         clock-indices = <0>, <5>,
 193                                         <12>, <13>;
 194                         clock-output-names = "apb1_codec", "apb1_pio",
 195                                         "apb1_daudio0", "apb1_daudio1";
 196                 };
 197
 198                 apb2: clk@01c20058 {
 199                         #clock-cells = <0>;
 200                         compatible = "allwinner,sun4i-a10-apb1-clk";
 201                         reg = <0x01c20058 0x4>;
 202                         clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
 203                         clock-output-names = "apb2";
 204                 };
 205
 206                 apb2_gates: clk@01c2006c {
 207                         #clock-cells = <1>;
 208                         compatible = "allwinner,sun8i-a23-apb2-gates-clk";
 209                         reg = <0x01c2006c 0x4>;
 210                         clocks = <&apb2>;
 211                         clock-indices = <0>, <1>,
 212                                         <2>, <16>,
 213                                         <17>, <18>,
 214                                         <19>, <20>;
 215                         clock-output-names = "apb2_i2c0", "apb2_i2c1",
 216                                         "apb2_i2c2", "apb2_uart0",
 217                                         "apb2_uart1", "apb2_uart2",
 218                                         "apb2_uart3", "apb2_uart4";
 219                 };
 220
 221                 mmc0_clk: clk@01c20088 {
 222                         #clock-cells = <1>;
 223                         compatible = "allwinner,sun4i-a10-mmc-clk";
 224                         reg = <0x01c20088 0x4>;
 225                         clocks = <&osc24M>, <&pll6>;
 226                         clock-output-names = "mmc0",
 227                                              "mmc0_output",
 228                                              "mmc0_sample";
 229                 };
 230
 231                 mmc1_clk: clk@01c2008c {
 232                         #clock-cells = <1>;
 233                         compatible = "allwinner,sun4i-a10-mmc-clk";
 234                         reg = <0x01c2008c 0x4>;
 235                         clocks = <&osc24M>, <&pll6>;
 236                         clock-output-names = "mmc1",
 237                                              "mmc1_output",
 238                                              "mmc1_sample";
 239                 };
 240
 241                 mmc2_clk: clk@01c20090 {
 242                         #clock-cells = <1>;
 243                         compatible = "allwinner,sun4i-a10-mmc-clk";
 244                         reg = <0x01c20090 0x4>;
 245                         clocks = <&osc24M>, <&pll6>;
 246                         clock-output-names = "mmc2",
 247                                              "mmc2_output",
 248                                              "mmc2_sample";
 249                 };
 250
 251                 usb_clk: clk@01c200cc {
 252                         #clock-cells = <1>;
 253                         #reset-cells = <1>;
 254                         compatible = "allwinner,sun8i-a23-usb-clk";
 255                         reg = <0x01c200cc 0x4>;
 256                         clocks = <&osc24M>;
 257                         clock-output-names = "usb_phy0", "usb_phy1", "usb_hsic",
 258                                              "usb_hsic_12M", "usb_ohci0";
 259                 };
 260         };
 261
 262         soc@01c00000 {
 263                 compatible = "simple-bus";
 264                 #address-cells = <1>;
 265                 #size-cells = <1>;
 266                 ranges;
 267
 268                 dma: dma-controller@01c02000 {
 269                         compatible = "allwinner,sun8i-a23-dma";
 270                         reg = <0x01c02000 0x1000>;
 271                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 272                         clocks = <&ahb1_gates 6>;
 273                         resets = <&ahb1_rst 6>;
 274                         #dma-cells = <1>;
 275                 };
 276
 277                 mmc0: mmc@01c0f000 {
 278                         compatible = "allwinner,sun5i-a13-mmc";
 279                         reg = <0x01c0f000 0x1000>;
 280                         clocks = <&ahb1_gates 8>,
 281                                  <&mmc0_clk 0>,
 282                                  <&mmc0_clk 1>,
 283                                  <&mmc0_clk 2>;
 284                         clock-names = "ahb",
 285                                       "mmc",
 286                                       "output",
 287                                       "sample";
 288                         resets = <&ahb1_rst 8>;
 289                         reset-names = "ahb";
 290                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 291                         status = "disabled";
 292                         #address-cells = <1>;
 293                         #size-cells = <0>;
 294                 };
 295
 296                 mmc1: mmc@01c10000 {
 297                         compatible = "allwinner,sun5i-a13-mmc";
 298                         reg = <0x01c10000 0x1000>;
 299                         clocks = <&ahb1_gates 9>,
 300                                  <&mmc1_clk 0>,
 301                                  <&mmc1_clk 1>,
 302                                  <&mmc1_clk 2>;
 303                         clock-names = "ahb",
 304                                       "mmc",
 305                                       "output",
 306                                       "sample";
 307                         resets = <&ahb1_rst 9>;
 308                         reset-names = "ahb";
 309                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 310                         status = "disabled";
 311                         #address-cells = <1>;
 312                         #size-cells = <0>;
 313                 };
 314
 315                 mmc2: mmc@01c11000 {
 316                         compatible = "allwinner,sun5i-a13-mmc";
 317                         reg = <0x01c11000 0x1000>;
 318                         clocks = <&ahb1_gates 10>,
 319                                  <&mmc2_clk 0>,
 320                                  <&mmc2_clk 1>,
 321                                  <&mmc2_clk 2>;
 322                         clock-names = "ahb",
 323                                       "mmc",
 324                                       "output",
 325                                       "sample";
 326                         resets = <&ahb1_rst 10>;
 327                         reset-names = "ahb";
 328                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 329                         status = "disabled";
 330                         #address-cells = <1>;
 331                         #size-cells = <0>;
 332                 };
 333
 334                 ehci0: usb@01c1a000 {
 335                         compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
 336                         reg = <0x01c1a000 0x100>;
 337                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 338                         clocks = <&ahb1_gates 26>;
 339                         resets = <&ahb1_rst 26>;
 340                         phys = <&usbphy 1>;
 341                         phy-names = "usb";
 342                         status = "disabled";
 343                 };
 344
 345                 ohci0: usb@01c1a400 {
 346                         compatible = "allwinner,sun8i-a23-ohci", "generic-ohci";
 347                         reg = <0x01c1a400 0x100>;
 348                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 349                         clocks = <&ahb1_gates 29>, <&usb_clk 16>;
 350                         resets = <&ahb1_rst 29>;
 351                         phys = <&usbphy 1>;
 352                         phy-names = "usb";
 353                         status = "disabled";
 354                 };
 355
 356                 pio: pinctrl@01c20800 {
 357                         /* compatible gets set in SoC specific dtsi file */
 358                         reg = <0x01c20800 0x400>;
 359                         /* interrupts get set in SoC specific dtsi file */
 360                         clocks = <&apb1_gates 5>;
 361                         gpio-controller;
 362                         interrupt-controller;
 363                         #interrupt-cells = <3>;
 364                         #gpio-cells = <3>;
 365
 366                         uart0_pins_a: uart0@0 {
 367                                 allwinner,pins = "PF2", "PF4";
 368                                 allwinner,function = "uart0";
 369                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 370                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 371                         };
 372
 373                         mmc0_pins_a: mmc0@0 {
 374                                 allwinner,pins = "PF0", "PF1", "PF2",
 375                                                  "PF3", "PF4", "PF5";
 376                                 allwinner,function = "mmc0";
 377                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 378                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 379                         };
 380
 381                         mmc1_pins_a: mmc1@0 {
 382                                 allwinner,pins = "PG0", "PG1", "PG2",
 383                                                  "PG3", "PG4", "PG5";
 384                                 allwinner,function = "mmc1";
 385                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 386                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 387                         };
 388
 389                         mmc2_8bit_pins: mmc2_8bit {
 390                                 allwinner,pins = "PC5", "PC6", "PC8",
 391                                                  "PC9", "PC10", "PC11",
 392                                                  "PC12", "PC13", "PC14",
 393                                                  "PC15";
 394                                 allwinner,function = "mmc2";
 395                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 396                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 397                         };
 398
 399                         pwm0_pins: pwm0 {
 400                                 allwinner,pins = "PH0";
 401                                 allwinner,function = "pwm0";
 402                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 403                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 404                         };
 405
 406                         i2c0_pins_a: i2c0@0 {
 407                                 allwinner,pins = "PH2", "PH3";
 408                                 allwinner,function = "i2c0";
 409                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 410                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 411                         };
 412
 413                         i2c1_pins_a: i2c1@0 {
 414                                 allwinner,pins = "PH4", "PH5";
 415                                 allwinner,function = "i2c1";
 416                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 417                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 418                         };
 419
 420                         i2c2_pins_a: i2c2@0 {
 421                                 allwinner,pins = "PE12", "PE13";
 422                                 allwinner,function = "i2c2";
 423                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 424                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 425                         };
 426                 };
 427
 428                 ahb1_rst: reset@01c202c0 {
 429                         #reset-cells = <1>;
 430                         compatible = "allwinner,sun6i-a31-clock-reset";
 431                         reg = <0x01c202c0 0xc>;
 432                 };
 433
 434                 apb1_rst: reset@01c202d0 {
 435                         #reset-cells = <1>;
 436                         compatible = "allwinner,sun6i-a31-clock-reset";
 437                         reg = <0x01c202d0 0x4>;
 438                 };
 439
 440                 apb2_rst: reset@01c202d8 {
 441                         #reset-cells = <1>;
 442                         compatible = "allwinner,sun6i-a31-clock-reset";
 443                         reg = <0x01c202d8 0x4>;
 444                 };
 445
 446                 timer@01c20c00 {
 447                         compatible = "allwinner,sun4i-a10-timer";
 448                         reg = <0x01c20c00 0xa0>;
 449                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 450                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 451                         clocks = <&osc24M>;
 452                 };
 453
 454                 wdt0: watchdog@01c20ca0 {
 455                         compatible = "allwinner,sun6i-a31-wdt";
 456                         reg = <0x01c20ca0 0x20>;
 457                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 458                 };
 459
 460                 pwm: pwm@01c21400 {
 461                         compatible = "allwinner,sun7i-a20-pwm";
 462                         reg = <0x01c21400 0xc>;
 463                         clocks = <&osc24M>;
 464                         #pwm-cells = <3>;
 465                         status = "disabled";
 466                 };
 467
 468                 lradc: lradc@01c22800 {
 469                         compatible = "allwinner,sun4i-a10-lradc-keys";
 470                         reg = <0x01c22800 0x100>;
 471                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 472                         status = "disabled";
 473                 };
 474
 475                 uart0: serial@01c28000 {
 476                         compatible = "snps,dw-apb-uart";
 477                         reg = <0x01c28000 0x400>;
 478                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 479                         reg-shift = <2>;
 480                         reg-io-width = <4>;
 481                         clocks = <&apb2_gates 16>;
 482                         resets = <&apb2_rst 16>;
 483                         dmas = <&dma 6>, <&dma 6>;
 484                         dma-names = "rx", "tx";
 485                         status = "disabled";
 486                 };
 487
 488                 uart1: serial@01c28400 {
 489                         compatible = "snps,dw-apb-uart";
 490                         reg = <0x01c28400 0x400>;
 491                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 492                         reg-shift = <2>;
 493                         reg-io-width = <4>;
 494                         clocks = <&apb2_gates 17>;
 495                         resets = <&apb2_rst 17>;
 496                         dmas = <&dma 7>, <&dma 7>;
 497                         dma-names = "rx", "tx";
 498                         status = "disabled";
 499                 };
 500
 501                 uart2: serial@01c28800 {
 502                         compatible = "snps,dw-apb-uart";
 503                         reg = <0x01c28800 0x400>;
 504                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 505                         reg-shift = <2>;
 506                         reg-io-width = <4>;
 507                         clocks = <&apb2_gates 18>;
 508                         resets = <&apb2_rst 18>;
 509                         dmas = <&dma 8>, <&dma 8>;
 510                         dma-names = "rx", "tx";
 511                         status = "disabled";
 512                 };
 513
 514                 uart3: serial@01c28c00 {
 515                         compatible = "snps,dw-apb-uart";
 516                         reg = <0x01c28c00 0x400>;
 517                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 518                         reg-shift = <2>;
 519                         reg-io-width = <4>;
 520                         clocks = <&apb2_gates 19>;
 521                         resets = <&apb2_rst 19>;
 522                         dmas = <&dma 9>, <&dma 9>;
 523                         dma-names = "rx", "tx";
 524                         status = "disabled";
 525                 };
 526
 527                 uart4: serial@01c29000 {
 528                         compatible = "snps,dw-apb-uart";
 529                         reg = <0x01c29000 0x400>;
 530                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 531                         reg-shift = <2>;
 532                         reg-io-width = <4>;
 533                         clocks = <&apb2_gates 20>;
 534                         resets = <&apb2_rst 20>;
 535                         dmas = <&dma 10>, <&dma 10>;
 536                         dma-names = "rx", "tx";
 537                         status = "disabled";
 538                 };
 539
 540                 i2c0: i2c@01c2ac00 {
 541                         compatible = "allwinner,sun6i-a31-i2c";
 542                         reg = <0x01c2ac00 0x400>;
 543                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 544                         clocks = <&apb2_gates 0>;
 545                         resets = <&apb2_rst 0>;
 546                         status = "disabled";
 547                         #address-cells = <1>;
 548                         #size-cells = <0>;
 549                 };
 550
 551                 i2c1: i2c@01c2b000 {
 552                         compatible = "allwinner,sun6i-a31-i2c";
 553                         reg = <0x01c2b000 0x400>;
 554                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 555                         clocks = <&apb2_gates 1>;
 556                         resets = <&apb2_rst 1>;
 557                         status = "disabled";
 558                         #address-cells = <1>;
 559                         #size-cells = <0>;
 560                 };
 561
 562                 i2c2: i2c@01c2b400 {
 563                         compatible = "allwinner,sun6i-a31-i2c";
 564                         reg = <0x01c2b400 0x400>;
 565                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 566                         clocks = <&apb2_gates 2>;
 567                         resets = <&apb2_rst 2>;
 568                         status = "disabled";
 569                         #address-cells = <1>;
 570                         #size-cells = <0>;
 571                 };
 572
 573                 gic: interrupt-controller@01c81000 {
 574                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 575                         reg = <0x01c81000 0x1000>,
 576                               <0x01c82000 0x1000>,
 577                               <0x01c84000 0x2000>,
 578                               <0x01c86000 0x2000>;
 579                         interrupt-controller;
 580                         #interrupt-cells = <3>;
 581                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 582                 };
 583
 584                 rtc: rtc@01f00000 {
 585                         compatible = "allwinner,sun6i-a31-rtc";
 586                         reg = <0x01f00000 0x54>;
 587                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 588                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 589                 };
 590
 591                 nmi_intc: interrupt-controller@01f00c0c {
 592                         compatible = "allwinner,sun6i-a31-sc-nmi";
 593                         interrupt-controller;
 594                         #interrupt-cells = <2>;
 595                         reg = <0x01f00c0c 0x38>;
 596                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 597                 };
 598
 599                 prcm@01f01400 {
 600                         compatible = "allwinner,sun8i-a23-prcm";
 601                         reg = <0x01f01400 0x200>;
 602
 603                         ar100: ar100_clk {
 604                                 compatible = "fixed-factor-clock";
 605                                 #clock-cells = <0>;
 606                                 clock-div = <1>;
 607                                 clock-mult = <1>;
 608                                 clocks = <&osc24M>;
 609                                 clock-output-names = "ar100";
 610                         };
 611
 612                         ahb0: ahb0_clk {
 613                                 compatible = "fixed-factor-clock";
 614                                 #clock-cells = <0>;
 615                                 clock-div = <1>;
 616                                 clock-mult = <1>;
 617                                 clocks = <&ar100>;
 618                                 clock-output-names = "ahb0";
 619                         };
 620
 621                         apb0: apb0_clk {
 622                                 compatible = "allwinner,sun8i-a23-apb0-clk";
 623                                 #clock-cells = <0>;
 624                                 clocks = <&ahb0>;
 625                                 clock-output-names = "apb0";
 626                         };
 627
 628                         apb0_gates: apb0_gates_clk {
 629                                 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
 630                                 #clock-cells = <1>;
 631                                 clocks = <&apb0>;
 632                                 clock-output-names = "apb0_pio", "apb0_timer",
 633                                                 "apb0_rsb", "apb0_uart",
 634                                                 "apb0_i2c";
 635                         };
 636
 637                         apb0_rst: apb0_rst {
 638                                 compatible = "allwinner,sun6i-a31-clock-reset";
 639                                 #reset-cells = <1>;
 640                         };
 641                 };
 642
 643                 cpucfg@01f01c00 {
 644                         compatible = "allwinner,sun8i-a23-cpuconfig";
 645                         reg = <0x01f01c00 0x300>;
 646                 };
 647
 648                 r_uart: serial@01f02800 {
 649                         compatible = "snps,dw-apb-uart";
 650                         reg = <0x01f02800 0x400>;
 651                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 652                         reg-shift = <2>;
 653                         reg-io-width = <4>;
 654                         clocks = <&apb0_gates 4>;
 655                         resets = <&apb0_rst 4>;
 656                         status = "disabled";
 657                 };
 658
 659                 r_pio: pinctrl@01f02c00 {
 660                         compatible = "allwinner,sun8i-a23-r-pinctrl";
 661                         reg = <0x01f02c00 0x400>;
 662                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 663                         clocks = <&apb0_gates 0>;
 664                         resets = <&apb0_rst 0>;
 665                         gpio-controller;
 666                         interrupt-controller;
 667                         #interrupt-cells = <3>;
 668                         #address-cells = <1>;
 669                         #size-cells = <0>;
 670                         #gpio-cells = <3>;
 671
 672                         r_rsb_pins: r_rsb {
 673                                 allwinner,pins = "PL0", "PL1";
 674                                 allwinner,function = "s_rsb";
 675                                 allwinner,drive = <SUN4I_PINCTRL_20_MA>;
 676                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 677                         };
 678
 679                         r_uart_pins_a: r_uart@0 {
 680                                 allwinner,pins = "PL2", "PL3";
 681                                 allwinner,function = "s_uart";
 682                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 683                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 684                         };
 685                 };
 686
 687                 r_rsb: rsb@01f03400 {
 688                         compatible = "allwinner,sun8i-a23-rsb";
 689                         reg = <0x01f03400 0x400>;
 690                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 691                         clocks = <&apb0_gates 3>;
 692                         clock-frequency = <3000000>;
 693                         resets = <&apb0_rst 3>;
 694                         pinctrl-names = "default";
 695                         pinctrl-0 = <&r_rsb_pins>;
 696                         status = "disabled";
 697                         #address-cells = <1>;
 698                         #size-cells = <0>;
 699                 };
 700         };
 701 };