2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 /include/ "skeleton.dtsi"
17 interrupt-parent = <&gic>;
33 compatible = "arm,cortex-a7";
39 compatible = "arm,cortex-a7";
46 reg = <0x40000000 0x40000000>;
56 compatible = "fixed-clock";
57 clock-frequency = <24000000>;
58 clock-output-names = "osc24M";
63 compatible = "fixed-clock";
64 clock-frequency = <32768>;
65 clock-output-names = "osc32k";
70 compatible = "allwinner,sun8i-a23-pll1-clk";
71 reg = <0x01c20000 0x4>;
73 clock-output-names = "pll1";
76 /* dummy clock until actually implemented */
79 compatible = "fixed-clock";
80 clock-frequency = <600000000>;
81 clock-output-names = "pll6";
84 cpu: cpu_clk@01c20050 {
86 compatible = "allwinner,sun4i-a10-cpu-clk";
87 reg = <0x01c20050 0x4>;
90 * PLL1 is listed twice here.
91 * While it looks suspicious, it's actually documented
92 * that way both in the datasheet and in the code from
95 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
96 clock-output-names = "cpu";
99 axi: axi_clk@01c20050 {
101 compatible = "allwinner,sun8i-a23-axi-clk";
102 reg = <0x01c20050 0x4>;
104 clock-output-names = "axi";
107 ahb1_mux: ahb1_mux_clk@01c20054 {
109 compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
110 reg = <0x01c20054 0x4>;
111 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
112 clock-output-names = "ahb1_mux";
115 ahb1: ahb1_clk@01c20054 {
117 compatible = "allwinner,sun4i-a10-ahb-clk";
118 reg = <0x01c20054 0x4>;
119 clocks = <&ahb1_mux>;
120 clock-output-names = "ahb1";
123 apb1: apb1_clk@01c20054 {
125 compatible = "allwinner,sun4i-a10-apb0-clk";
126 reg = <0x01c20054 0x4>;
128 clock-output-names = "apb1";
131 ahb1_gates: clk@01c20060 {
133 compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
134 reg = <0x01c20060 0x8>;
136 clock-output-names = "ahb1_mipidsi", "ahb1_dma",
137 "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
138 "ahb1_nand", "ahb1_sdram",
139 "ahb1_hstimer", "ahb1_spi0",
140 "ahb1_spi1", "ahb1_otg", "ahb1_ehci",
141 "ahb1_ohci", "ahb1_ve", "ahb1_lcd",
142 "ahb1_csi", "ahb1_be", "ahb1_fe",
143 "ahb1_gpu", "ahb1_spinlock",
147 apb1_gates: clk@01c20068 {
149 compatible = "allwinner,sun8i-a23-apb1-gates-clk";
150 reg = <0x01c20068 0x4>;
152 clock-output-names = "apb1_codec", "apb1_pio",
153 "apb1_daudio0", "apb1_daudio1";
156 apb2_mux: apb2_mux_clk@01c20058 {
158 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
159 reg = <0x01c20058 0x4>;
160 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
161 clock-output-names = "apb2_mux";
164 apb2: apb2_clk@01c20058 {
166 compatible = "allwinner,sun6i-a31-apb2-div-clk";
167 reg = <0x01c20058 0x4>;
168 clocks = <&apb2_mux>;
169 clock-output-names = "apb2";
172 apb2_gates: clk@01c2006c {
174 compatible = "allwinner,sun8i-a23-apb2-gates-clk";
175 reg = <0x01c2006c 0x4>;
177 clock-output-names = "apb2_i2c0", "apb2_i2c1",
178 "apb2_i2c2", "apb2_uart0",
179 "apb2_uart1", "apb2_uart2",
180 "apb2_uart3", "apb2_uart4";
183 mmc0_clk: clk@01c20088 {
185 compatible = "allwinner,sun4i-a10-mod0-clk";
186 reg = <0x01c20088 0x4>;
187 clocks = <&osc24M>, <&pll6>;
188 clock-output-names = "mmc0";
191 mmc1_clk: clk@01c2008c {
193 compatible = "allwinner,sun4i-a10-mod0-clk";
194 reg = <0x01c2008c 0x4>;
195 clocks = <&osc24M>, <&pll6>;
196 clock-output-names = "mmc1";
199 mmc2_clk: clk@01c20090 {
201 compatible = "allwinner,sun4i-a10-mod0-clk";
202 reg = <0x01c20090 0x4>;
203 clocks = <&osc24M>, <&pll6>;
204 clock-output-names = "mmc2";
209 compatible = "simple-bus";
210 #address-cells = <1>;
215 compatible = "allwinner,sun5i-a13-mmc";
216 reg = <0x01c0f000 0x1000>;
217 clocks = <&ahb1_gates 8>, <&mmc0_clk>;
218 clock-names = "ahb", "mmc";
219 resets = <&ahb1_rst 8>;
221 interrupts = <0 60 4>;
226 compatible = "allwinner,sun5i-a13-mmc";
227 reg = <0x01c10000 0x1000>;
228 clocks = <&ahb1_gates 9>, <&mmc1_clk>;
229 clock-names = "ahb", "mmc";
230 resets = <&ahb1_rst 9>;
232 interrupts = <0 61 4>;
237 compatible = "allwinner,sun5i-a13-mmc";
238 reg = <0x01c11000 0x1000>;
239 clocks = <&ahb1_gates 10>, <&mmc2_clk>;
240 clock-names = "ahb", "mmc";
241 resets = <&ahb1_rst 10>;
243 interrupts = <0 62 4>;
247 pio: pinctrl@01c20800 {
248 compatible = "allwinner,sun8i-a23-pinctrl";
249 reg = <0x01c20800 0x400>;
250 interrupts = <0 11 4>,
253 clocks = <&apb1_gates 5>;
255 interrupt-controller;
256 #address-cells = <1>;
260 uart0_pins_a: uart0@0 {
261 allwinner,pins = "PF2", "PF4";
262 allwinner,function = "uart0";
263 allwinner,drive = <0>;
264 allwinner,pull = <0>;
267 mmc0_pins_a: mmc0@0 {
268 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
269 allwinner,function = "mmc0";
270 allwinner,drive = <2>;
271 allwinner,pull = <0>;
274 mmc1_pins_a: mmc1@0 {
275 allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5";
276 allwinner,function = "mmc1";
277 allwinner,drive = <2>;
278 allwinner,pull = <0>;
281 i2c0_pins_a: i2c0@0 {
282 allwinner,pins = "PH2", "PH3";
283 allwinner,function = "i2c0";
284 allwinner,drive = <0>;
285 allwinner,pull = <0>;
288 i2c1_pins_a: i2c1@0 {
289 allwinner,pins = "PH4", "PH5";
290 allwinner,function = "i2c1";
291 allwinner,drive = <0>;
292 allwinner,pull = <0>;
295 i2c2_pins_a: i2c2@0 {
296 allwinner,pins = "PE12", "PE13";
297 allwinner,function = "i2c2";
298 allwinner,drive = <0>;
299 allwinner,pull = <0>;
303 ahb1_rst: reset@01c202c0 {
305 compatible = "allwinner,sun6i-a31-clock-reset";
306 reg = <0x01c202c0 0xc>;
309 apb1_rst: reset@01c202d0 {
311 compatible = "allwinner,sun6i-a31-clock-reset";
312 reg = <0x01c202d0 0x4>;
315 apb2_rst: reset@01c202d8 {
317 compatible = "allwinner,sun6i-a31-clock-reset";
318 reg = <0x01c202d8 0x4>;
322 compatible = "allwinner,sun4i-a10-timer";
323 reg = <0x01c20c00 0xa0>;
324 interrupts = <0 18 4>,
329 wdt0: watchdog@01c20ca0 {
330 compatible = "allwinner,sun6i-a31-wdt";
331 reg = <0x01c20ca0 0x20>;
332 interrupts = <0 25 4>;
335 uart0: serial@01c28000 {
336 compatible = "snps,dw-apb-uart";
337 reg = <0x01c28000 0x400>;
338 interrupts = <0 0 4>;
341 clocks = <&apb2_gates 16>;
342 resets = <&apb2_rst 16>;
346 uart1: serial@01c28400 {
347 compatible = "snps,dw-apb-uart";
348 reg = <0x01c28400 0x400>;
349 interrupts = <0 1 4>;
352 clocks = <&apb2_gates 17>;
353 resets = <&apb2_rst 17>;
357 uart2: serial@01c28800 {
358 compatible = "snps,dw-apb-uart";
359 reg = <0x01c28800 0x400>;
360 interrupts = <0 2 4>;
363 clocks = <&apb2_gates 18>;
364 resets = <&apb2_rst 18>;
368 uart3: serial@01c28c00 {
369 compatible = "snps,dw-apb-uart";
370 reg = <0x01c28c00 0x400>;
371 interrupts = <0 3 4>;
374 clocks = <&apb2_gates 19>;
375 resets = <&apb2_rst 19>;
379 uart4: serial@01c29000 {
380 compatible = "snps,dw-apb-uart";
381 reg = <0x01c29000 0x400>;
382 interrupts = <0 4 4>;
385 clocks = <&apb2_gates 20>;
386 resets = <&apb2_rst 20>;
390 gic: interrupt-controller@01c81000 {
391 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
392 reg = <0x01c81000 0x1000>,
396 interrupt-controller;
397 #interrupt-cells = <3>;
398 interrupts = <1 9 0xf04>;
402 compatible = "allwinner,sun6i-a31-rtc";
403 reg = <0x01f00000 0x54>;
404 interrupts = <0 40 4>, <0 41 4>;
408 compatible = "allwinner,sun8i-a23-prcm";
409 reg = <0x01f01400 0x200>;
412 compatible = "fixed-factor-clock";
417 clock-output-names = "ar100";
421 compatible = "fixed-factor-clock";
426 clock-output-names = "ahb0";
430 compatible = "allwinner,sun8i-a23-apb0-clk";
433 clock-output-names = "apb0";
436 apb0_gates: apb0_gates_clk {
437 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
440 clock-output-names = "apb0_pio", "apb0_timer",
441 "apb0_rsb", "apb0_uart",
446 compatible = "allwinner,sun6i-a31-clock-reset";
451 r_uart: serial@01f02800 {
452 compatible = "snps,dw-apb-uart";
453 reg = <0x01f02800 0x400>;
454 interrupts = <0 38 4>;
457 clocks = <&apb0_gates 4>;
458 resets = <&apb0_rst 4>;
462 r_pio: pinctrl@01f02c00 {
463 compatible = "allwinner,sun8i-a23-r-pinctrl";
464 reg = <0x01f02c00 0x400>;
465 interrupts = <0 45 4>;
466 clocks = <&apb0_gates 0>;
467 resets = <&apb0_rst 0>;
469 interrupt-controller;
470 #address-cells = <1>;
474 r_uart_pins_a: r_uart@0 {
475 allwinner,pins = "PL2", "PL3";
476 allwinner,function = "s_uart";
477 allwinner,drive = <0>;
478 allwinner,pull = <0>;