2 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include "skeleton.dtsi"
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/pinctrl/sun4i-a10.h>
49 interrupt-parent = <&gic>;
56 compatible = "arm,cortex-a7";
62 compatible = "arm,cortex-a7";
68 compatible = "arm,cortex-a7";
74 compatible = "arm,cortex-a7";
81 compatible = "arm,armv7-timer";
82 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
83 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
84 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
85 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
95 compatible = "fixed-clock";
96 clock-frequency = <24000000>;
97 clock-output-names = "osc24M";
102 compatible = "fixed-clock";
103 clock-frequency = <32768>;
104 clock-output-names = "osc32k";
109 compatible = "allwinner,sun8i-a23-pll1-clk";
110 reg = <0x01c20000 0x4>;
112 clock-output-names = "pll1";
115 /* dummy clock until actually implemented */
118 compatible = "fixed-clock";
119 clock-frequency = <0>;
120 clock-output-names = "pll5";
125 compatible = "allwinner,sun6i-a31-pll6-clk";
126 reg = <0x01c20028 0x4>;
128 clock-output-names = "pll6";
133 compatible = "fixed-factor-clock";
137 clock-output-names = "pll6-d2";
142 compatible = "fixed-factor-clock";
146 clock-output-names = "pll6-2x";
151 compatible = "allwinner,sun6i-a31-pll6-clk";
152 reg = <0x01c20044 0x4>;
154 clock-output-names = "pll8";
157 cpu: cpu_clk@01c20050 {
159 compatible = "allwinner,sun4i-a10-cpu-clk";
160 reg = <0x01c20050 0x4>;
161 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
162 clock-output-names = "cpu";
165 axi: axi_clk@01c20050 {
167 compatible = "allwinner,sun4i-a10-axi-clk";
168 reg = <0x01c20050 0x4>;
170 clock-output-names = "axi";
173 ahb1: ahb1_clk@01c20054 {
175 compatible = "allwinner,sun6i-a31-ahb1-clk";
176 reg = <0x01c20054 0x4>;
177 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
178 clock-output-names = "ahb1";
181 ahb2: ahb2_clk@01c2005c {
183 compatible = "allwinner,sun8i-h3-ahb2-clk";
184 reg = <0x01c2005c 0x4>;
185 clocks = <&ahb1>, <&pll6d2>;
186 clock-output-names = "ahb2";
189 apb1: apb1_clk@01c20054 {
191 compatible = "allwinner,sun4i-a10-apb0-clk";
192 reg = <0x01c20054 0x4>;
194 clock-output-names = "apb1";
197 apb2: apb2_clk@01c20058 {
199 compatible = "allwinner,sun4i-a10-apb1-clk";
200 reg = <0x01c20058 0x4>;
201 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
202 clock-output-names = "apb2";
205 bus_gates: clk@01c20060 {
207 compatible = "allwinner,sun8i-h3-bus-gates-clk";
208 reg = <0x01c20060 0x14>;
209 clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
210 clock-names = "ahb1", "ahb2", "apb1", "apb2";
211 clock-indices = <5>, <6>, <8>,
230 clock-output-names = "bus_ce", "bus_dma", "bus_mmc0",
231 "bus_mmc1", "bus_mmc2", "bus_nand",
232 "bus_sdram", "bus_gmac", "bus_ts",
233 "bus_hstimer", "bus_spi0",
234 "bus_spi1", "bus_otg",
235 "bus_otg_ehci0", "bus_ehci1",
236 "bus_ehci2", "bus_ehci3",
237 "bus_otg_ohci0", "bus_ohci1",
238 "bus_ohci2", "bus_ohci3", "bus_ve",
239 "bus_lcd0", "bus_lcd1", "bus_deint",
240 "bus_csi", "bus_tve", "bus_hdmi",
241 "bus_de", "bus_gpu", "bus_msgbox",
242 "bus_spinlock", "bus_codec",
243 "bus_spdif", "bus_pio", "bus_ths",
244 "bus_i2s0", "bus_i2s1", "bus_i2s2",
245 "bus_i2c0", "bus_i2c1", "bus_i2c2",
246 "bus_uart0", "bus_uart1",
247 "bus_uart2", "bus_uart3",
248 "bus_scr", "bus_ephy", "bus_dbg";
251 mmc0_clk: clk@01c20088 {
253 compatible = "allwinner,sun4i-a10-mmc-clk";
254 reg = <0x01c20088 0x4>;
255 clocks = <&osc24M>, <&pll6>, <&pll8>;
256 clock-output-names = "mmc0",
261 mmc1_clk: clk@01c2008c {
263 compatible = "allwinner,sun4i-a10-mmc-clk";
264 reg = <0x01c2008c 0x4>;
265 clocks = <&osc24M>, <&pll6>, <&pll8>;
266 clock-output-names = "mmc1",
271 mmc2_clk: clk@01c20090 {
273 compatible = "allwinner,sun4i-a10-mmc-clk";
274 reg = <0x01c20090 0x4>;
275 clocks = <&osc24M>, <&pll6>, <&pll8>;
276 clock-output-names = "mmc2",
281 mbus_clk: clk@01c2015c {
283 compatible = "allwinner,sun8i-a23-mbus-clk";
284 reg = <0x01c2015c 0x4>;
285 clocks = <&osc24M>, <&pll6x2>, <&pll5>;
286 clock-output-names = "mbus";
291 compatible = "simple-bus";
292 #address-cells = <1>;
296 dma: dma-controller@01c02000 {
297 compatible = "allwinner,sun8i-h3-dma";
298 reg = <0x01c02000 0x1000>;
299 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&bus_gates 6>;
301 resets = <&ahb_rst 6>;
306 compatible = "allwinner,sun5i-a13-mmc";
307 reg = <0x01c0f000 0x1000>;
308 clocks = <&bus_gates 8>,
316 resets = <&ahb_rst 8>;
318 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
320 #address-cells = <1>;
325 compatible = "allwinner,sun5i-a13-mmc";
326 reg = <0x01c10000 0x1000>;
327 clocks = <&bus_gates 9>,
335 resets = <&ahb_rst 9>;
337 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
339 #address-cells = <1>;
344 compatible = "allwinner,sun5i-a13-mmc";
345 reg = <0x01c11000 0x1000>;
346 clocks = <&bus_gates 10>,
354 resets = <&ahb_rst 10>;
356 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
358 #address-cells = <1>;
362 pio: pinctrl@01c20800 {
363 compatible = "allwinner,sun8i-h3-pinctrl";
364 reg = <0x01c20800 0x400>;
365 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
366 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&bus_gates 69>;
370 interrupt-controller;
371 #interrupt-cells = <2>;
373 uart0_pins_a: uart0@0 {
374 allwinner,pins = "PA4", "PA5";
375 allwinner,function = "uart0";
376 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
377 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
380 mmc0_pins_a: mmc0@0 {
381 allwinner,pins = "PF0", "PF1", "PF2", "PF3",
383 allwinner,function = "mmc0";
384 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
385 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
388 mmc0_cd_pin: mmc0_cd_pin@0 {
389 allwinner,pins = "PF6";
390 allwinner,function = "gpio_in";
391 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
392 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
395 mmc1_pins_a: mmc1@0 {
396 allwinner,pins = "PG0", "PG1", "PG2", "PG3",
398 allwinner,function = "mmc1";
399 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
400 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
404 ahb_rst: reset@01c202c0 {
406 compatible = "allwinner,sun6i-a31-ahb1-reset";
407 reg = <0x01c202c0 0xc>;
410 apb1_rst: reset@01c202d0 {
412 compatible = "allwinner,sun6i-a31-clock-reset";
413 reg = <0x01c202d0 0x4>;
416 apb2_rst: reset@01c202d8 {
418 compatible = "allwinner,sun6i-a31-clock-reset";
419 reg = <0x01c202d8 0x4>;
423 compatible = "allwinner,sun4i-a10-timer";
424 reg = <0x01c20c00 0xa0>;
425 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
426 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
430 wdt0: watchdog@01c20ca0 {
431 compatible = "allwinner,sun6i-a31-wdt";
432 reg = <0x01c20ca0 0x20>;
433 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
436 uart0: serial@01c28000 {
437 compatible = "snps,dw-apb-uart";
438 reg = <0x01c28000 0x400>;
439 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&bus_gates 112>;
443 resets = <&apb2_rst 16>;
444 dmas = <&dma 6>, <&dma 6>;
445 dma-names = "rx", "tx";
449 uart1: serial@01c28400 {
450 compatible = "snps,dw-apb-uart";
451 reg = <0x01c28400 0x400>;
452 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&bus_gates 113>;
456 resets = <&apb2_rst 17>;
457 dmas = <&dma 7>, <&dma 7>;
458 dma-names = "rx", "tx";
462 uart2: serial@01c28800 {
463 compatible = "snps,dw-apb-uart";
464 reg = <0x01c28800 0x400>;
465 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&bus_gates 114>;
469 resets = <&apb2_rst 18>;
470 dmas = <&dma 8>, <&dma 8>;
471 dma-names = "rx", "tx";
475 uart3: serial@01c28c00 {
476 compatible = "snps,dw-apb-uart";
477 reg = <0x01c28c00 0x400>;
478 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&bus_gates 115>;
482 resets = <&apb2_rst 19>;
483 dmas = <&dma 9>, <&dma 9>;
484 dma-names = "rx", "tx";
488 gic: interrupt-controller@01c81000 {
489 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
490 reg = <0x01c81000 0x1000>,
494 interrupt-controller;
495 #interrupt-cells = <3>;
496 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
500 compatible = "allwinner,sun6i-a31-rtc";
501 reg = <0x01f00000 0x54>;
502 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
503 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;