arch/arm/boot/dts/sun8i-h3.dtsi

   1 /*
   2  * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include "skeleton.dtsi"
  44
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/pinctrl/sun4i-a10.h>
  47
  48 / {
  49         interrupt-parent = <&gic>;
  50
  51         cpus {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54
  55                 cpu@0 {
  56                         compatible = "arm,cortex-a7";
  57                         device_type = "cpu";
  58                         reg = <0>;
  59                 };
  60
  61                 cpu@1 {
  62                         compatible = "arm,cortex-a7";
  63                         device_type = "cpu";
  64                         reg = <1>;
  65                 };
  66
  67                 cpu@2 {
  68                         compatible = "arm,cortex-a7";
  69                         device_type = "cpu";
  70                         reg = <2>;
  71                 };
  72
  73                 cpu@3 {
  74                         compatible = "arm,cortex-a7";
  75                         device_type = "cpu";
  76                         reg = <3>;
  77                 };
  78         };
  79
  80         timer {
  81                 compatible = "arm,armv7-timer";
  82                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  83                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  84                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  85                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  86         };
  87
  88         clocks {
  89                 #address-cells = <1>;
  90                 #size-cells = <1>;
  91                 ranges;
  92
  93                 osc24M: osc24M_clk {
  94                         #clock-cells = <0>;
  95                         compatible = "fixed-clock";
  96                         clock-frequency = <24000000>;
  97                         clock-output-names = "osc24M";
  98                 };
  99
 100                 osc32k: osc32k_clk {
 101                         #clock-cells = <0>;
 102                         compatible = "fixed-clock";
 103                         clock-frequency = <32768>;
 104                         clock-output-names = "osc32k";
 105                 };
 106
 107                 pll1: clk@01c20000 {
 108                         #clock-cells = <0>;
 109                         compatible = "allwinner,sun8i-a23-pll1-clk";
 110                         reg = <0x01c20000 0x4>;
 111                         clocks = <&osc24M>;
 112                         clock-output-names = "pll1";
 113                 };
 114
 115                 /* dummy clock until actually implemented */
 116                 pll5: pll5_clk {
 117                         #clock-cells = <0>;
 118                         compatible = "fixed-clock";
 119                         clock-frequency = <0>;
 120                         clock-output-names = "pll5";
 121                 };
 122
 123                 pll6: clk@01c20028 {
 124                         #clock-cells = <0>;
 125                         compatible = "allwinner,sun6i-a31-pll6-clk";
 126                         reg = <0x01c20028 0x4>;
 127                         clocks = <&osc24M>;
 128                         clock-output-names = "pll6";
 129                 };
 130
 131                 pll6d2: pll6d2_clk {
 132                         #clock-cells = <0>;
 133                         compatible = "fixed-factor-clock";
 134                         clock-div = <2>;
 135                         clock-mult = <1>;
 136                         clocks = <&pll6>;
 137                         clock-output-names = "pll6-d2";
 138                 };
 139
 140                 pll6x2: pll6x2_clk {
 141                         #clock-cells = <0>;
 142                         compatible = "fixed-factor-clock";
 143                         clock-div = <1>;
 144                         clock-mult = <2>;
 145                         clocks = <&pll6>;
 146                         clock-output-names = "pll6-2x";
 147                 };
 148
 149                 pll8: clk@01c20044 {
 150                         #clock-cells = <0>;
 151                         compatible = "allwinner,sun6i-a31-pll6-clk";
 152                         reg = <0x01c20044 0x4>;
 153                         clocks = <&osc24M>;
 154                         clock-output-names = "pll8";
 155                 };
 156
 157                 cpu: cpu_clk@01c20050 {
 158                         #clock-cells = <0>;
 159                         compatible = "allwinner,sun4i-a10-cpu-clk";
 160                         reg = <0x01c20050 0x4>;
 161                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
 162                         clock-output-names = "cpu";
 163                 };
 164
 165                 axi: axi_clk@01c20050 {
 166                         #clock-cells = <0>;
 167                         compatible = "allwinner,sun4i-a10-axi-clk";
 168                         reg = <0x01c20050 0x4>;
 169                         clocks = <&cpu>;
 170                         clock-output-names = "axi";
 171                 };
 172
 173                 ahb1: ahb1_clk@01c20054 {
 174                         #clock-cells = <0>;
 175                         compatible = "allwinner,sun6i-a31-ahb1-clk";
 176                         reg = <0x01c20054 0x4>;
 177                         clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
 178                         clock-output-names = "ahb1";
 179                 };
 180
 181                 ahb2: ahb2_clk@01c2005c {
 182                         #clock-cells = <0>;
 183                         compatible = "allwinner,sun8i-h3-ahb2-clk";
 184                         reg = <0x01c2005c 0x4>;
 185                         clocks = <&ahb1>, <&pll6d2>;
 186                         clock-output-names = "ahb2";
 187                 };
 188
 189                 apb1: apb1_clk@01c20054 {
 190                         #clock-cells = <0>;
 191                         compatible = "allwinner,sun4i-a10-apb0-clk";
 192                         reg = <0x01c20054 0x4>;
 193                         clocks = <&ahb1>;
 194                         clock-output-names = "apb1";
 195                 };
 196
 197                 apb2: apb2_clk@01c20058 {
 198                         #clock-cells = <0>;
 199                         compatible = "allwinner,sun4i-a10-apb1-clk";
 200                         reg = <0x01c20058 0x4>;
 201                         clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
 202                         clock-output-names = "apb2";
 203                 };
 204
 205                 bus_gates: clk@01c20060 {
 206                         #clock-cells = <1>;
 207                         compatible = "allwinner,sun8i-h3-bus-gates-clk";
 208                         reg = <0x01c20060 0x14>;
 209                         clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
 210                         clock-names = "ahb1", "ahb2", "apb1", "apb2";
 211                         clock-indices = <5>, <6>, <8>,
 212                                         <9>, <10>, <13>,
 213                                         <14>, <17>, <18>,
 214                                         <19>, <20>,
 215                                         <21>, <23>,
 216                                         <24>, <25>,
 217                                         <26>, <27>,
 218                                         <28>, <29>,
 219                                         <30>, <31>, <32>,
 220                                         <35>, <36>, <37>,
 221                                         <40>, <41>, <43>,
 222                                         <44>, <52>, <53>,
 223                                         <54>, <64>,
 224                                         <65>, <69>, <72>,
 225                                         <76>, <77>, <78>,
 226                                         <96>, <97>, <98>,
 227                                         <112>, <113>,
 228                                         <114>, <115>,
 229                                         <116>, <128>, <135>;
 230                         clock-output-names = "bus_ce", "bus_dma", "bus_mmc0",
 231                                              "bus_mmc1", "bus_mmc2", "bus_nand",
 232                                              "bus_sdram", "bus_gmac", "bus_ts",
 233                                              "bus_hstimer", "bus_spi0",
 234                                              "bus_spi1", "bus_otg",
 235                                              "bus_otg_ehci0", "bus_ehci1",
 236                                              "bus_ehci2", "bus_ehci3",
 237                                              "bus_otg_ohci0", "bus_ohci1",
 238                                              "bus_ohci2", "bus_ohci3", "bus_ve",
 239                                              "bus_lcd0", "bus_lcd1", "bus_deint",
 240                                              "bus_csi", "bus_tve", "bus_hdmi",
 241                                              "bus_de", "bus_gpu", "bus_msgbox",
 242                                              "bus_spinlock", "bus_codec",
 243                                              "bus_spdif", "bus_pio", "bus_ths",
 244                                              "bus_i2s0", "bus_i2s1", "bus_i2s2",
 245                                              "bus_i2c0", "bus_i2c1", "bus_i2c2",
 246                                              "bus_uart0", "bus_uart1",
 247                                              "bus_uart2", "bus_uart3",
 248                                              "bus_scr", "bus_ephy", "bus_dbg";
 249                 };
 250
 251                 mmc0_clk: clk@01c20088 {
 252                         #clock-cells = <1>;
 253                         compatible = "allwinner,sun4i-a10-mmc-clk";
 254                         reg = <0x01c20088 0x4>;
 255                         clocks = <&osc24M>, <&pll6>, <&pll8>;
 256                         clock-output-names = "mmc0",
 257                                              "mmc0_output",
 258                                              "mmc0_sample";
 259                 };
 260
 261                 mmc1_clk: clk@01c2008c {
 262                         #clock-cells = <1>;
 263                         compatible = "allwinner,sun4i-a10-mmc-clk";
 264                         reg = <0x01c2008c 0x4>;
 265                         clocks = <&osc24M>, <&pll6>, <&pll8>;
 266                         clock-output-names = "mmc1",
 267                                              "mmc1_output",
 268                                              "mmc1_sample";
 269                 };
 270
 271                 mmc2_clk: clk@01c20090 {
 272                         #clock-cells = <1>;
 273                         compatible = "allwinner,sun4i-a10-mmc-clk";
 274                         reg = <0x01c20090 0x4>;
 275                         clocks = <&osc24M>, <&pll6>, <&pll8>;
 276                         clock-output-names = "mmc2",
 277                                              "mmc2_output",
 278                                              "mmc2_sample";
 279                 };
 280
 281                 mbus_clk: clk@01c2015c {
 282                         #clock-cells = <0>;
 283                         compatible = "allwinner,sun8i-a23-mbus-clk";
 284                         reg = <0x01c2015c 0x4>;
 285                         clocks = <&osc24M>, <&pll6x2>, <&pll5>;
 286                         clock-output-names = "mbus";
 287                 };
 288         };
 289
 290         soc {
 291                 compatible = "simple-bus";
 292                 #address-cells = <1>;
 293                 #size-cells = <1>;
 294                 ranges;
 295
 296                 dma: dma-controller@01c02000 {
 297                         compatible = "allwinner,sun8i-h3-dma";
 298                         reg = <0x01c02000 0x1000>;
 299                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 300                         clocks = <&bus_gates 6>;
 301                         resets = <&ahb_rst 6>;
 302                         #dma-cells = <1>;
 303                 };
 304
 305                 mmc0: mmc@01c0f000 {
 306                         compatible = "allwinner,sun5i-a13-mmc";
 307                         reg = <0x01c0f000 0x1000>;
 308                         clocks = <&bus_gates 8>,
 309                                  <&mmc0_clk 0>,
 310                                  <&mmc0_clk 1>,
 311                                  <&mmc0_clk 2>;
 312                         clock-names = "ahb",
 313                                       "mmc",
 314                                       "output",
 315                                       "sample";
 316                         resets = <&ahb_rst 8>;
 317                         reset-names = "ahb";
 318                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 319                         status = "disabled";
 320                         #address-cells = <1>;
 321                         #size-cells = <0>;
 322                 };
 323
 324                 mmc1: mmc@01c10000 {
 325                         compatible = "allwinner,sun5i-a13-mmc";
 326                         reg = <0x01c10000 0x1000>;
 327                         clocks = <&bus_gates 9>,
 328                                  <&mmc1_clk 0>,
 329                                  <&mmc1_clk 1>,
 330                                  <&mmc1_clk 2>;
 331                         clock-names = "ahb",
 332                                       "mmc",
 333                                       "output",
 334                                       "sample";
 335                         resets = <&ahb_rst 9>;
 336                         reset-names = "ahb";
 337                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 338                         status = "disabled";
 339                         #address-cells = <1>;
 340                         #size-cells = <0>;
 341                 };
 342
 343                 mmc2: mmc@01c11000 {
 344                         compatible = "allwinner,sun5i-a13-mmc";
 345                         reg = <0x01c11000 0x1000>;
 346                         clocks = <&bus_gates 10>,
 347                                  <&mmc2_clk 0>,
 348                                  <&mmc2_clk 1>,
 349                                  <&mmc2_clk 2>;
 350                         clock-names = "ahb",
 351                                       "mmc",
 352                                       "output",
 353                                       "sample";
 354                         resets = <&ahb_rst 10>;
 355                         reset-names = "ahb";
 356                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 357                         status = "disabled";
 358                         #address-cells = <1>;
 359                         #size-cells = <0>;
 360                 };
 361
 362                 pio: pinctrl@01c20800 {
 363                         compatible = "allwinner,sun8i-h3-pinctrl";
 364                         reg = <0x01c20800 0x400>;
 365                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 366                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 367                         clocks = <&bus_gates 69>;
 368                         gpio-controller;
 369                         #gpio-cells = <3>;
 370                         interrupt-controller;
 371                         #interrupt-cells = <2>;
 372
 373                         uart0_pins_a: uart0@0 {
 374                                 allwinner,pins = "PA4", "PA5";
 375                                 allwinner,function = "uart0";
 376                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 377                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 378                         };
 379
 380                         mmc0_pins_a: mmc0@0 {
 381                                 allwinner,pins = "PF0", "PF1", "PF2", "PF3",
 382                                                  "PF4", "PF5";
 383                                 allwinner,function = "mmc0";
 384                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 385                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 386                         };
 387
 388                         mmc0_cd_pin: mmc0_cd_pin@0 {
 389                                 allwinner,pins = "PF6";
 390                                 allwinner,function = "gpio_in";
 391                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 392                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 393                         };
 394
 395                         mmc1_pins_a: mmc1@0 {
 396                                 allwinner,pins = "PG0", "PG1", "PG2", "PG3",
 397                                                  "PG4", "PG5";
 398                                 allwinner,function = "mmc1";
 399                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 400                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 401                         };
 402                 };
 403
 404                 ahb_rst: reset@01c202c0 {
 405                         #reset-cells = <1>;
 406                         compatible = "allwinner,sun6i-a31-ahb1-reset";
 407                         reg = <0x01c202c0 0xc>;
 408                 };
 409
 410                 apb1_rst: reset@01c202d0 {
 411                         #reset-cells = <1>;
 412                         compatible = "allwinner,sun6i-a31-clock-reset";
 413                         reg = <0x01c202d0 0x4>;
 414                 };
 415
 416                 apb2_rst: reset@01c202d8 {
 417                         #reset-cells = <1>;
 418                         compatible = "allwinner,sun6i-a31-clock-reset";
 419                         reg = <0x01c202d8 0x4>;
 420                 };
 421
 422                 timer@01c20c00 {
 423                         compatible = "allwinner,sun4i-a10-timer";
 424                         reg = <0x01c20c00 0xa0>;
 425                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 426                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 427                         clocks = <&osc24M>;
 428                 };
 429
 430                 wdt0: watchdog@01c20ca0 {
 431                         compatible = "allwinner,sun6i-a31-wdt";
 432                         reg = <0x01c20ca0 0x20>;
 433                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 434                 };
 435
 436                 uart0: serial@01c28000 {
 437                         compatible = "snps,dw-apb-uart";
 438                         reg = <0x01c28000 0x400>;
 439                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 440                         reg-shift = <2>;
 441                         reg-io-width = <4>;
 442                         clocks = <&bus_gates 112>;
 443                         resets = <&apb2_rst 16>;
 444                         dmas = <&dma 6>, <&dma 6>;
 445                         dma-names = "rx", "tx";
 446                         status = "disabled";
 447                 };
 448
 449                 uart1: serial@01c28400 {
 450                         compatible = "snps,dw-apb-uart";
 451                         reg = <0x01c28400 0x400>;
 452                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 453                         reg-shift = <2>;
 454                         reg-io-width = <4>;
 455                         clocks = <&bus_gates 113>;
 456                         resets = <&apb2_rst 17>;
 457                         dmas = <&dma 7>, <&dma 7>;
 458                         dma-names = "rx", "tx";
 459                         status = "disabled";
 460                 };
 461
 462                 uart2: serial@01c28800 {
 463                         compatible = "snps,dw-apb-uart";
 464                         reg = <0x01c28800 0x400>;
 465                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 466                         reg-shift = <2>;
 467                         reg-io-width = <4>;
 468                         clocks = <&bus_gates 114>;
 469                         resets = <&apb2_rst 18>;
 470                         dmas = <&dma 8>, <&dma 8>;
 471                         dma-names = "rx", "tx";
 472                         status = "disabled";
 473                 };
 474
 475                 uart3: serial@01c28c00 {
 476                         compatible = "snps,dw-apb-uart";
 477                         reg = <0x01c28c00 0x400>;
 478                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 479                         reg-shift = <2>;
 480                         reg-io-width = <4>;
 481                         clocks = <&bus_gates 115>;
 482                         resets = <&apb2_rst 19>;
 483                         dmas = <&dma 9>, <&dma 9>;
 484                         dma-names = "rx", "tx";
 485                         status = "disabled";
 486                 };
 487
 488                 gic: interrupt-controller@01c81000 {
 489                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 490                         reg = <0x01c81000 0x1000>,
 491                               <0x01c82000 0x1000>,
 492                               <0x01c84000 0x2000>,
 493                               <0x01c86000 0x2000>;
 494                         interrupt-controller;
 495                         #interrupt-cells = <3>;
 496                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 497                 };
 498
 499                 rtc: rtc@01f00000 {
 500                         compatible = "allwinner,sun6i-a31-rtc";
 501                         reg = <0x01f00000 0x54>;
 502                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 503                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 504                 };
 505         };
 506 };