2 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include "skeleton.dtsi"
45 #include <dt-bindings/clock/sun8i-h3-ccu.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/sun4i-a10.h>
48 #include <dt-bindings/reset/sun8i-h3-ccu.h>
51 interrupt-parent = <&gic>;
58 compatible = "arm,cortex-a7";
64 compatible = "arm,cortex-a7";
70 compatible = "arm,cortex-a7";
76 compatible = "arm,cortex-a7";
83 compatible = "arm,armv7-timer";
84 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
85 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
86 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
87 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
97 compatible = "fixed-clock";
98 clock-frequency = <24000000>;
99 clock-output-names = "osc24M";
104 compatible = "fixed-clock";
105 clock-frequency = <32768>;
106 clock-output-names = "osc32k";
110 compatible = "fixed-factor-clock";
115 clock-output-names = "apb0";
118 apb0_gates: clk@01f01428 {
119 compatible = "allwinner,sun8i-h3-apb0-gates-clk",
120 "allwinner,sun4i-a10-gates-clk";
121 reg = <0x01f01428 0x4>;
124 clock-indices = <0>, <1>;
125 clock-output-names = "apb0_pio", "apb0_ir";
128 ir_clk: ir_clk@01f01454 {
129 compatible = "allwinner,sun4i-a10-mod0-clk";
130 reg = <0x01f01454 0x4>;
132 clocks = <&osc32k>, <&osc24M>;
133 clock-output-names = "ir";
138 compatible = "simple-bus";
139 #address-cells = <1>;
143 dma: dma-controller@01c02000 {
144 compatible = "allwinner,sun8i-h3-dma";
145 reg = <0x01c02000 0x1000>;
146 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
147 clocks = <&ccu CLK_BUS_DMA>;
148 resets = <&ccu RST_BUS_DMA>;
153 compatible = "allwinner,sun7i-a20-mmc";
154 reg = <0x01c0f000 0x1000>;
155 clocks = <&ccu CLK_BUS_MMC0>,
157 <&ccu CLK_MMC0_OUTPUT>,
158 <&ccu CLK_MMC0_SAMPLE>;
163 resets = <&ccu RST_BUS_MMC0>;
165 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
167 #address-cells = <1>;
172 compatible = "allwinner,sun7i-a20-mmc";
173 reg = <0x01c10000 0x1000>;
174 clocks = <&ccu CLK_BUS_MMC1>,
176 <&ccu CLK_MMC1_OUTPUT>,
177 <&ccu CLK_MMC1_SAMPLE>;
182 resets = <&ccu RST_BUS_MMC1>;
184 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
186 #address-cells = <1>;
191 compatible = "allwinner,sun7i-a20-mmc";
192 reg = <0x01c11000 0x1000>;
193 clocks = <&ccu CLK_BUS_MMC2>,
195 <&ccu CLK_MMC2_OUTPUT>,
196 <&ccu CLK_MMC2_SAMPLE>;
201 resets = <&ccu RST_BUS_MMC2>;
203 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
205 #address-cells = <1>;
209 usbphy: phy@01c19400 {
210 compatible = "allwinner,sun8i-h3-usb-phy";
211 reg = <0x01c19400 0x2c>,
216 reg-names = "phy_ctrl",
221 clocks = <&ccu CLK_USB_PHY0>,
225 clock-names = "usb0_phy",
229 resets = <&ccu RST_USB_PHY0>,
233 reset-names = "usb0_reset",
241 ehci1: usb@01c1b000 {
242 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
243 reg = <0x01c1b000 0x100>;
244 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
246 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
252 ohci1: usb@01c1b400 {
253 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
254 reg = <0x01c1b400 0x100>;
255 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
257 <&ccu CLK_USB_OHCI1>;
258 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
264 ehci2: usb@01c1c000 {
265 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
266 reg = <0x01c1c000 0x100>;
267 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
269 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
275 ohci2: usb@01c1c400 {
276 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
277 reg = <0x01c1c400 0x100>;
278 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
280 <&ccu CLK_USB_OHCI2>;
281 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
287 ehci3: usb@01c1d000 {
288 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
289 reg = <0x01c1d000 0x100>;
290 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
291 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
292 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
298 ohci3: usb@01c1d400 {
299 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
300 reg = <0x01c1d400 0x100>;
301 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
302 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
303 <&ccu CLK_USB_OHCI3>;
304 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
310 ccu: clock@01c20000 {
311 compatible = "allwinner,sun8i-h3-ccu";
312 reg = <0x01c20000 0x400>;
313 clocks = <&osc24M>, <&osc32k>;
314 clock-names = "hosc", "losc";
319 pio: pinctrl@01c20800 {
320 compatible = "allwinner,sun8i-h3-pinctrl";
321 reg = <0x01c20800 0x400>;
322 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
325 clock-names = "apb", "hosc", "losc";
328 interrupt-controller;
329 #interrupt-cells = <3>;
332 allwinner,pins = "PA11", "PA12";
333 allwinner,function = "i2c0";
334 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
335 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
339 allwinner,pins = "PA18", "PA19";
340 allwinner,function = "i2c1";
341 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
342 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
346 allwinner,pins = "PE12", "PE13";
347 allwinner,function = "i2c2";
348 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
349 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
352 mmc0_pins_a: mmc0@0 {
353 allwinner,pins = "PF0", "PF1", "PF2", "PF3",
355 allwinner,function = "mmc0";
356 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
357 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
360 mmc0_cd_pin: mmc0_cd_pin@0 {
361 allwinner,pins = "PF6";
362 allwinner,function = "gpio_in";
363 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
364 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
367 mmc1_pins_a: mmc1@0 {
368 allwinner,pins = "PG0", "PG1", "PG2", "PG3",
370 allwinner,function = "mmc1";
371 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
372 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
375 mmc2_8bit_pins: mmc2_8bit {
376 allwinner,pins = "PC5", "PC6", "PC8",
377 "PC9", "PC10", "PC11",
378 "PC12", "PC13", "PC14",
380 allwinner,function = "mmc2";
381 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
382 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
386 allwinner,pins = "PC0", "PC1", "PC2", "PC3";
387 allwinner,function = "spi0";
388 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
389 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
393 allwinner,pins = "PA15", "PA16", "PA14", "PA13";
394 allwinner,function = "spi1";
395 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
396 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
399 uart0_pins_a: uart0@0 {
400 allwinner,pins = "PA4", "PA5";
401 allwinner,function = "uart0";
402 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
403 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
407 allwinner,pins = "PG6", "PG7";
408 allwinner,function = "uart1";
409 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
410 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
413 uart1_rts_cts_pins: uart1_rts_cts {
414 allwinner,pins = "PG8", "PG9";
415 allwinner,function = "uart1";
416 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
417 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
421 allwinner,pins = "PA0", "PA1";
422 allwinner,function = "uart2";
423 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
424 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
428 allwinner,pins = "PA13", "PA14";
429 allwinner,function = "uart3";
430 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
431 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
436 compatible = "allwinner,sun4i-a10-timer";
437 reg = <0x01c20c00 0xa0>;
438 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
444 compatible = "allwinner,sun8i-h3-spi";
445 reg = <0x01c68000 0x1000>;
446 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
447 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
448 clock-names = "ahb", "mod";
449 dmas = <&dma 23>, <&dma 23>;
450 dma-names = "rx", "tx";
451 pinctrl-names = "default";
452 pinctrl-0 = <&spi0_pins>;
453 resets = <&ccu RST_BUS_SPI0>;
455 #address-cells = <1>;
460 compatible = "allwinner,sun8i-h3-spi";
461 reg = <0x01c69000 0x1000>;
462 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
464 clock-names = "ahb", "mod";
465 dmas = <&dma 24>, <&dma 24>;
466 dma-names = "rx", "tx";
467 pinctrl-names = "default";
468 pinctrl-0 = <&spi1_pins>;
469 resets = <&ccu RST_BUS_SPI1>;
471 #address-cells = <1>;
475 wdt0: watchdog@01c20ca0 {
476 compatible = "allwinner,sun6i-a31-wdt";
477 reg = <0x01c20ca0 0x20>;
478 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
482 compatible = "allwinner,sun8i-h3-pwm";
483 reg = <0x01c21400 0x8>;
489 uart0: serial@01c28000 {
490 compatible = "snps,dw-apb-uart";
491 reg = <0x01c28000 0x400>;
492 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
495 clocks = <&ccu CLK_BUS_UART0>;
496 resets = <&ccu RST_BUS_UART0>;
497 dmas = <&dma 6>, <&dma 6>;
498 dma-names = "rx", "tx";
502 uart1: serial@01c28400 {
503 compatible = "snps,dw-apb-uart";
504 reg = <0x01c28400 0x400>;
505 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&ccu CLK_BUS_UART1>;
509 resets = <&ccu RST_BUS_UART1>;
510 dmas = <&dma 7>, <&dma 7>;
511 dma-names = "rx", "tx";
515 uart2: serial@01c28800 {
516 compatible = "snps,dw-apb-uart";
517 reg = <0x01c28800 0x400>;
518 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&ccu CLK_BUS_UART2>;
522 resets = <&ccu RST_BUS_UART2>;
523 dmas = <&dma 8>, <&dma 8>;
524 dma-names = "rx", "tx";
528 uart3: serial@01c28c00 {
529 compatible = "snps,dw-apb-uart";
530 reg = <0x01c28c00 0x400>;
531 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
534 clocks = <&ccu CLK_BUS_UART3>;
535 resets = <&ccu RST_BUS_UART3>;
536 dmas = <&dma 9>, <&dma 9>;
537 dma-names = "rx", "tx";
542 compatible = "allwinner,sun6i-a31-i2c";
543 reg = <0x01c2ac00 0x400>;
544 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&ccu CLK_BUS_I2C0>;
546 resets = <&ccu RST_BUS_I2C0>;
547 pinctrl-names = "default";
548 pinctrl-0 = <&i2c0_pins>;
550 #address-cells = <1>;
555 compatible = "allwinner,sun6i-a31-i2c";
556 reg = <0x01c2b000 0x400>;
557 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
558 clocks = <&ccu CLK_BUS_I2C1>;
559 resets = <&ccu RST_BUS_I2C1>;
560 pinctrl-names = "default";
561 pinctrl-0 = <&i2c1_pins>;
563 #address-cells = <1>;
568 compatible = "allwinner,sun6i-a31-i2c";
569 reg = <0x01c2b000 0x400>;
570 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&ccu CLK_BUS_I2C2>;
572 resets = <&ccu RST_BUS_I2C2>;
573 pinctrl-names = "default";
574 pinctrl-0 = <&i2c2_pins>;
576 #address-cells = <1>;
580 gic: interrupt-controller@01c81000 {
581 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
582 reg = <0x01c81000 0x1000>,
586 interrupt-controller;
587 #interrupt-cells = <3>;
588 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
592 compatible = "allwinner,sun6i-a31-rtc";
593 reg = <0x01f00000 0x54>;
594 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
595 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
598 apb0_reset: reset@01f014b0 {
599 reg = <0x01f014b0 0x4>;
600 compatible = "allwinner,sun6i-a31-clock-reset";
605 compatible = "allwinner,sun5i-a13-ir";
606 clocks = <&apb0_gates 1>, <&ir_clk>;
607 clock-names = "apb", "ir";
608 resets = <&apb0_reset 1>;
609 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
610 reg = <0x01f02000 0x40>;
614 r_pio: pinctrl@01f02c00 {
615 compatible = "allwinner,sun8i-h3-r-pinctrl";
616 reg = <0x01f02c00 0x400>;
617 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
618 clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
619 clock-names = "apb", "hosc", "losc";
620 resets = <&apb0_reset 0>;
623 interrupt-controller;
624 #interrupt-cells = <3>;
627 allwinner,pins = "PL11";
628 allwinner,function = "s_cir_rx";
629 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
630 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;