2 * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 interrupt-parent = <&gic>;
55 compatible = "arm,cortex-a7";
63 compatible = "arm,armv7-timer";
64 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
65 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
66 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
67 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
77 compatible = "fixed-clock";
78 clock-frequency = <24000000>;
79 clock-output-names = "osc24M";
84 compatible = "fixed-clock";
85 clock-frequency = <32768>;
86 clock-output-names = "osc32k";
91 compatible = "simple-bus";
97 compatible = "allwinner,sun7i-a20-mmc";
98 reg = <0x01c0f000 0x1000>;
109 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
111 #address-cells = <1>;
116 compatible = "allwinner,sun7i-a20-mmc";
117 reg = <0x01c10000 0x1000>;
128 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
130 #address-cells = <1>;
135 compatible = "allwinner,sun7i-a20-mmc";
136 reg = <0x01c11000 0x1000>;
147 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
149 #address-cells = <1>;
153 usb_otg: usb@01c19000 {
154 compatible = "allwinner,sun8i-h3-musb";
155 reg = <0x01c19000 0x0400>;
158 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
159 interrupt-names = "mc";
162 extcon = <&usbphy 0>;
166 usbphy: phy@01c19400 {
167 compatible = "allwinner,sun8i-v3s-usb-phy";
168 reg = <0x01c19400 0x2c>,
170 reg-names = "phy_ctrl",
173 clock-names = "usb0_phy";
175 reset-names = "usb0_reset";
180 ccu: clock@01c20000 {
181 compatible = "allwinner,sun8i-v3s-ccu";
182 reg = <0x01c20000 0x400>;
183 clocks = <&osc24M>, <&osc32k>;
184 clock-names = "hosc", "losc";
190 compatible = "allwinner,sun6i-a31-rtc";
191 reg = <0x01c20400 0x54>;
192 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
196 pio: pinctrl@01c20800 {
197 compatible = "allwinner,sun8i-v3s-pinctrl";
198 reg = <0x01c20800 0x400>;
199 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
201 clocks = <&ccu 37>, <&osc24M>, <&osc32k>;
202 clock-names = "apb", "hosc", "losc";
205 interrupt-controller;
206 #interrupt-cells = <3>;
213 uart0_pins_a: uart0@0 {
218 mmc0_pins_a: mmc0@0 {
219 pins = "PF0", "PF1", "PF2", "PF3",
222 drive-strength = <30>;
228 compatible = "allwinner,sun4i-a10-timer";
229 reg = <0x01c20c00 0xa0>;
230 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
235 wdt0: watchdog@01c20ca0 {
236 compatible = "allwinner,sun6i-a31-wdt";
237 reg = <0x01c20ca0 0x20>;
238 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
241 uart0: serial@01c28000 {
242 compatible = "snps,dw-apb-uart";
243 reg = <0x01c28000 0x400>;
244 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
252 uart1: serial@01c28400 {
253 compatible = "snps,dw-apb-uart";
254 reg = <0x01c28400 0x400>;
255 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
263 uart2: serial@01c28800 {
264 compatible = "snps,dw-apb-uart";
265 reg = <0x01c28800 0x400>;
266 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
275 compatible = "allwinner,sun6i-a31-i2c";
276 reg = <0x01c2ac00 0x400>;
277 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
280 pinctrl-names = "default";
281 pinctrl-0 = <&i2c0_pins>;
283 #address-cells = <1>;
288 compatible = "allwinner,sun6i-a31-i2c";
289 reg = <0x01c2b000 0x400>;
290 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
294 #address-cells = <1>;
298 gic: interrupt-controller@01c81000 {
299 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
300 reg = <0x01c81000 0x1000>,
304 interrupt-controller;
305 #interrupt-cells = <3>;
306 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;