arch/arm/boot/dts/sun9i-a80.dtsi

   1 /*
   2  * Copyright 2014 Chen-Yu Tsai
   3  *
   4  * Chen-Yu Tsai <wens@csie.org>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include "skeleton64.dtsi"
  46
  47 #include <dt-bindings/interrupt-controller/arm-gic.h>
  48
  49 #include <dt-bindings/pinctrl/sun4i-a10.h>
  50
  51 #include <dt-bindings/clock/sun9i-a80-ccu.h>
  52 #include <dt-bindings/clock/sun9i-a80-de.h>
  53 #include <dt-bindings/clock/sun9i-a80-usb.h>
  54 #include <dt-bindings/reset/sun9i-a80-ccu.h>
  55 #include <dt-bindings/reset/sun9i-a80-de.h>
  56 #include <dt-bindings/reset/sun9i-a80-usb.h>
  57
  58 / {
  59         interrupt-parent = <&gic>;
  60
  61         cpus {
  62                 #address-cells = <1>;
  63                 #size-cells = <0>;
  64
  65                 cpu0: cpu@0 {
  66                         compatible = "arm,cortex-a7";
  67                         device_type = "cpu";
  68                         reg = <0x0>;
  69                 };
  70
  71                 cpu1: cpu@1 {
  72                         compatible = "arm,cortex-a7";
  73                         device_type = "cpu";
  74                         reg = <0x1>;
  75                 };
  76
  77                 cpu2: cpu@2 {
  78                         compatible = "arm,cortex-a7";
  79                         device_type = "cpu";
  80                         reg = <0x2>;
  81                 };
  82
  83                 cpu3: cpu@3 {
  84                         compatible = "arm,cortex-a7";
  85                         device_type = "cpu";
  86                         reg = <0x3>;
  87                 };
  88
  89                 cpu4: cpu@100 {
  90                         compatible = "arm,cortex-a15";
  91                         device_type = "cpu";
  92                         reg = <0x100>;
  93                 };
  94
  95                 cpu5: cpu@101 {
  96                         compatible = "arm,cortex-a15";
  97                         device_type = "cpu";
  98                         reg = <0x101>;
  99                 };
 100
 101                 cpu6: cpu@102 {
 102                         compatible = "arm,cortex-a15";
 103                         device_type = "cpu";
 104                         reg = <0x102>;
 105                 };
 106
 107                 cpu7: cpu@103 {
 108                         compatible = "arm,cortex-a15";
 109                         device_type = "cpu";
 110                         reg = <0x103>;
 111                 };
 112         };
 113
 114         memory {
 115                 /* 8GB max. with LPAE */
 116                 reg = <0 0x20000000 0x02 0>;
 117         };
 118
 119         timer {
 120                 compatible = "arm,armv7-timer";
 121                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 122                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 123                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 124                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 125                 clock-frequency = <24000000>;
 126                 arm,cpu-registers-not-fw-configured;
 127         };
 128
 129         clocks {
 130                 #address-cells = <1>;
 131                 #size-cells = <1>;
 132                 /*
 133                  * map 64 bit address range down to 32 bits,
 134                  * as the peripherals are all under 512MB.
 135                  */
 136                 ranges = <0 0 0 0x20000000>;
 137
 138                 /*
 139                  * This clock is actually configurable from the PRCM address
 140                  * space. The external 24M oscillator can be turned off, and
 141                  * the clock switched to an internal 16M RC oscillator. Under
 142                  * normal operation there's no reason to do this, and the
 143                  * default is to use the external good one, so just model this
 144                  * as a fixed clock. Also it is not entirely clear if the
 145                  * osc24M mux in the PRCM affects the entire clock tree, which
 146                  * would also throw all the PLL clock rates off, or just the
 147                  * downstream clocks in the PRCM.
 148                  */
 149                 osc24M: osc24M_clk {
 150                         #clock-cells = <0>;
 151                         compatible = "fixed-clock";
 152                         clock-frequency = <24000000>;
 153                         clock-output-names = "osc24M";
 154                 };
 155
 156                 /*
 157                  * The 32k clock is from an external source, normally the
 158                  * AC100 codec/RTC chip. This serves as a placeholder for
 159                  * board dts files to specify the source.
 160                  */
 161                 osc32k: osc32k_clk {
 162                         #clock-cells = <0>;
 163                         compatible = "fixed-factor-clock";
 164                         clock-div = <1>;
 165                         clock-mult = <1>;
 166                         clock-output-names = "osc32k";
 167                 };
 168
 169                 cpus_clk: clk@08001410 {
 170                         compatible = "allwinner,sun9i-a80-cpus-clk";
 171                         reg = <0x08001410 0x4>;
 172                         #clock-cells = <0>;
 173                         clocks = <&osc32k>, <&osc24M>,
 174                                  <&ccu CLK_PLL_PERIPH0>,
 175                                  <&ccu CLK_PLL_AUDIO>;
 176                         clock-output-names = "cpus";
 177                 };
 178
 179                 ahbs: ahbs_clk {
 180                         compatible = "fixed-factor-clock";
 181                         #clock-cells = <0>;
 182                         clock-div = <1>;
 183                         clock-mult = <1>;
 184                         clocks = <&cpus_clk>;
 185                         clock-output-names = "ahbs";
 186                 };
 187
 188                 apbs: clk@0800141c {
 189                         compatible = "allwinner,sun8i-a23-apb0-clk";
 190                         reg = <0x0800141c 0x4>;
 191                         #clock-cells = <0>;
 192                         clocks = <&ahbs>;
 193                         clock-output-names = "apbs";
 194                 };
 195
 196                 apbs_gates: clk@08001428 {
 197                         compatible = "allwinner,sun9i-a80-apbs-gates-clk";
 198                         reg = <0x08001428 0x4>;
 199                         #clock-cells = <1>;
 200                         clocks = <&apbs>;
 201                         clock-indices = <0>, <1>,
 202                                         <2>, <3>,
 203                                         <4>, <5>,
 204                                         <6>, <7>,
 205                                         <12>, <13>,
 206                                         <16>, <17>,
 207                                         <18>, <20>;
 208                         clock-output-names = "apbs_pio", "apbs_ir",
 209                                         "apbs_timer", "apbs_rsb",
 210                                         "apbs_uart", "apbs_1wire",
 211                                         "apbs_i2c0", "apbs_i2c1",
 212                                         "apbs_ps2_0", "apbs_ps2_1",
 213                                         "apbs_dma", "apbs_i2s0",
 214                                         "apbs_i2s1", "apbs_twd";
 215                 };
 216
 217                 r_1wire_clk: clk@08001450 {
 218                         reg = <0x08001450 0x4>;
 219                         #clock-cells = <0>;
 220                         compatible = "allwinner,sun4i-a10-mod0-clk";
 221                         clocks = <&osc32k>, <&osc24M>;
 222                         clock-output-names = "r_1wire";
 223                 };
 224
 225                 r_ir_clk: clk@08001454 {
 226                         reg = <0x08001454 0x4>;
 227                         #clock-cells = <0>;
 228                         compatible = "allwinner,sun4i-a10-mod0-clk";
 229                         clocks = <&osc32k>, <&osc24M>;
 230                         clock-output-names = "r_ir";
 231                 };
 232         };
 233
 234         soc {
 235                 compatible = "simple-bus";
 236                 #address-cells = <1>;
 237                 #size-cells = <1>;
 238                 /*
 239                  * map 64 bit address range down to 32 bits,
 240                  * as the peripherals are all under 512MB.
 241                  */
 242                 ranges = <0 0 0 0x20000000>;
 243
 244                 ehci0: usb@00a00000 {
 245                         compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
 246                         reg = <0x00a00000 0x100>;
 247                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 248                         clocks = <&usb_clocks CLK_BUS_HCI0>;
 249                         resets = <&usb_clocks RST_USB0_HCI>;
 250                         phys = <&usbphy1>;
 251                         phy-names = "usb";
 252                         status = "disabled";
 253                 };
 254
 255                 ohci0: usb@00a00400 {
 256                         compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
 257                         reg = <0x00a00400 0x100>;
 258                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 259                         clocks = <&usb_clocks CLK_BUS_HCI0>,
 260                                  <&usb_clocks CLK_USB_OHCI0>;
 261                         resets = <&usb_clocks RST_USB0_HCI>;
 262                         phys = <&usbphy1>;
 263                         phy-names = "usb";
 264                         status = "disabled";
 265                 };
 266
 267                 usbphy1: phy@00a00800 {
 268                         compatible = "allwinner,sun9i-a80-usb-phy";
 269                         reg = <0x00a00800 0x4>;
 270                         clocks = <&usb_clocks CLK_USB0_PHY>;
 271                         clock-names = "phy";
 272                         resets = <&usb_clocks RST_USB0_PHY>;
 273                         reset-names = "phy";
 274                         status = "disabled";
 275                         #phy-cells = <0>;
 276                 };
 277
 278                 ehci1: usb@00a01000 {
 279                         compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
 280                         reg = <0x00a01000 0x100>;
 281                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 282                         clocks = <&usb_clocks CLK_BUS_HCI1>;
 283                         resets = <&usb_clocks RST_USB1_HCI>;
 284                         phys = <&usbphy2>;
 285                         phy-names = "usb";
 286                         status = "disabled";
 287                 };
 288
 289                 usbphy2: phy@00a01800 {
 290                         compatible = "allwinner,sun9i-a80-usb-phy";
 291                         reg = <0x00a01800 0x4>;
 292                         clocks = <&usb_clocks CLK_USB1_HSIC>,
 293                                  <&usb_clocks CLK_USB_HSIC>,
 294                                  <&usb_clocks CLK_USB1_PHY>;
 295                         clock-names = "hsic_480M",
 296                                       "hsic_12M",
 297                                       "phy";
 298                         resets = <&usb_clocks RST_USB1_HSIC>,
 299                                  <&usb_clocks RST_USB1_PHY>;
 300                         reset-names = "hsic",
 301                                       "phy";
 302                         status = "disabled";
 303                         #phy-cells = <0>;
 304                         /* usb1 is always used with HSIC */
 305                         phy_type = "hsic";
 306                 };
 307
 308                 ehci2: usb@00a02000 {
 309                         compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
 310                         reg = <0x00a02000 0x100>;
 311                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 312                         clocks = <&usb_clocks CLK_BUS_HCI2>;
 313                         resets = <&usb_clocks RST_USB2_HCI>;
 314                         phys = <&usbphy3>;
 315                         phy-names = "usb";
 316                         status = "disabled";
 317                 };
 318
 319                 ohci2: usb@00a02400 {
 320                         compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
 321                         reg = <0x00a02400 0x100>;
 322                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 323                         clocks = <&usb_clocks CLK_BUS_HCI2>,
 324                                  <&usb_clocks CLK_USB_OHCI2>;
 325                         resets = <&usb_clocks RST_USB2_HCI>;
 326                         phys = <&usbphy3>;
 327                         phy-names = "usb";
 328                         status = "disabled";
 329                 };
 330
 331                 usbphy3: phy@00a02800 {
 332                         compatible = "allwinner,sun9i-a80-usb-phy";
 333                         reg = <0x00a02800 0x4>;
 334                         clocks = <&usb_clocks CLK_USB2_HSIC>,
 335                                  <&usb_clocks CLK_USB_HSIC>,
 336                                  <&usb_clocks CLK_USB2_PHY>;
 337                         clock-names = "hsic_480M",
 338                                       "hsic_12M",
 339                                       "phy";
 340                         resets = <&usb_clocks RST_USB2_HSIC>,
 341                                  <&usb_clocks RST_USB2_PHY>;
 342                         reset-names = "hsic",
 343                                       "phy";
 344                         status = "disabled";
 345                         #phy-cells = <0>;
 346                 };
 347
 348                 usb_clocks: clock@00a08000 {
 349                         compatible = "allwinner,sun9i-a80-usb-clks";
 350                         reg = <0x00a08000 0x8>;
 351                         clocks = <&ccu CLK_BUS_USB>, <&osc24M>;
 352                         clock-names = "bus", "hosc";
 353                         #clock-cells = <1>;
 354                         #reset-cells = <1>;
 355                 };
 356
 357                 mmc0: mmc@01c0f000 {
 358                         compatible = "allwinner,sun9i-a80-mmc";
 359                         reg = <0x01c0f000 0x1000>;
 360                         clocks = <&mmc_config_clk 0>, <&ccu CLK_MMC0>,
 361                                  <&ccu CLK_MMC0_OUTPUT>,
 362                                  <&ccu CLK_MMC0_SAMPLE>;
 363                         clock-names = "ahb", "mmc", "output", "sample";
 364                         resets = <&mmc_config_clk 0>;
 365                         reset-names = "ahb";
 366                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 367                         status = "disabled";
 368                         #address-cells = <1>;
 369                         #size-cells = <0>;
 370                 };
 371
 372                 mmc1: mmc@01c10000 {
 373                         compatible = "allwinner,sun9i-a80-mmc";
 374                         reg = <0x01c10000 0x1000>;
 375                         clocks = <&mmc_config_clk 1>, <&ccu CLK_MMC1>,
 376                                  <&ccu CLK_MMC1_OUTPUT>,
 377                                  <&ccu CLK_MMC1_SAMPLE>;
 378                         clock-names = "ahb", "mmc", "output", "sample";
 379                         resets = <&mmc_config_clk 1>;
 380                         reset-names = "ahb";
 381                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 382                         status = "disabled";
 383                         #address-cells = <1>;
 384                         #size-cells = <0>;
 385                 };
 386
 387                 mmc2: mmc@01c11000 {
 388                         compatible = "allwinner,sun9i-a80-mmc";
 389                         reg = <0x01c11000 0x1000>;
 390                         clocks = <&mmc_config_clk 2>, <&ccu CLK_MMC2>,
 391                                  <&ccu CLK_MMC2_OUTPUT>,
 392                                  <&ccu CLK_MMC2_SAMPLE>;
 393                         clock-names = "ahb", "mmc", "output", "sample";
 394                         resets = <&mmc_config_clk 2>;
 395                         reset-names = "ahb";
 396                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 397                         status = "disabled";
 398                         #address-cells = <1>;
 399                         #size-cells = <0>;
 400                 };
 401
 402                 mmc3: mmc@01c12000 {
 403                         compatible = "allwinner,sun9i-a80-mmc";
 404                         reg = <0x01c12000 0x1000>;
 405                         clocks = <&mmc_config_clk 3>, <&ccu CLK_MMC3>,
 406                                  <&ccu CLK_MMC3_OUTPUT>,
 407                                  <&ccu CLK_MMC3_SAMPLE>;
 408                         clock-names = "ahb", "mmc", "output", "sample";
 409                         resets = <&mmc_config_clk 3>;
 410                         reset-names = "ahb";
 411                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 412                         status = "disabled";
 413                         #address-cells = <1>;
 414                         #size-cells = <0>;
 415                 };
 416
 417                 mmc_config_clk: clk@01c13000 {
 418                         compatible = "allwinner,sun9i-a80-mmc-config-clk";
 419                         reg = <0x01c13000 0x10>;
 420                         clocks = <&ccu CLK_BUS_MMC>;
 421                         clock-names = "ahb";
 422                         resets = <&ccu RST_BUS_MMC>;
 423                         reset-names = "ahb";
 424                         #clock-cells = <1>;
 425                         #reset-cells = <1>;
 426                         clock-output-names = "mmc0_config", "mmc1_config",
 427                                              "mmc2_config", "mmc3_config";
 428                 };
 429
 430                 gic: interrupt-controller@01c41000 {
 431                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 432                         reg = <0x01c41000 0x1000>,
 433                               <0x01c42000 0x2000>,
 434                               <0x01c44000 0x2000>,
 435                               <0x01c46000 0x2000>;
 436                         interrupt-controller;
 437                         #interrupt-cells = <3>;
 438                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 439                 };
 440
 441                 de_clocks: clock@03000000 {
 442                         compatible = "allwinner,sun9i-a80-de-clks";
 443                         reg = <0x03000000 0x30>;
 444                         clocks = <&ccu CLK_DE>,
 445                                  <&ccu CLK_SDRAM>,
 446                                  <&ccu CLK_BUS_DE>;
 447                         clock-names = "mod",
 448                                       "dram",
 449                                       "bus";
 450                         resets = <&ccu RST_BUS_DE>;
 451                         #clock-cells = <1>;
 452                         #reset-cells = <1>;
 453                 };
 454
 455                 ccu: clock@06000000 {
 456                         compatible = "allwinner,sun9i-a80-ccu";
 457                         reg = <0x06000000 0x800>;
 458                         clocks = <&osc24M>, <&osc32k>;
 459                         clock-names = "hosc", "losc";
 460                         #clock-cells = <1>;
 461                         #reset-cells = <1>;
 462                 };
 463
 464                 timer@06000c00 {
 465                         compatible = "allwinner,sun4i-a10-timer";
 466                         reg = <0x06000c00 0xa0>;
 467                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 468                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 469                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 470                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 471                                      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 472                                      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 473
 474                         clocks = <&osc24M>;
 475                 };
 476
 477                 wdt: watchdog@06000ca0 {
 478                         compatible = "allwinner,sun6i-a31-wdt";
 479                         reg = <0x06000ca0 0x20>;
 480                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 481                 };
 482
 483                 pio: pinctrl@06000800 {
 484                         compatible = "allwinner,sun9i-a80-pinctrl";
 485                         reg = <0x06000800 0x400>;
 486                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 487                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 488                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 489                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 490                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 491                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
 492                         clock-names = "apb", "hosc", "losc";
 493                         gpio-controller;
 494                         interrupt-controller;
 495                         #interrupt-cells = <3>;
 496                         #size-cells = <0>;
 497                         #gpio-cells = <3>;
 498
 499                         i2c3_pins_a: i2c3@0 {
 500                                 pins = "PG10", "PG11";
 501                                 function = "i2c3";
 502                         };
 503
 504                         mmc0_pins: mmc0 {
 505                                 pins = "PF0", "PF1" ,"PF2", "PF3",
 506                                        "PF4", "PF5";
 507                                 function = "mmc0";
 508                                 drive-strength = <30>;
 509                                 bias-pull-up;
 510                         };
 511
 512                         mmc1_pins: mmc1 {
 513                                 pins = "PG0", "PG1" ,"PG2", "PG3",
 514                                                  "PG4", "PG5";
 515                                 function = "mmc1";
 516                                 drive-strength = <30>;
 517                                 bias-pull-up;
 518                         };
 519
 520                         mmc2_8bit_pins: mmc2_8bit {
 521                                 pins = "PC6", "PC7", "PC8", "PC9",
 522                                        "PC10", "PC11", "PC12",
 523                                        "PC13", "PC14", "PC15",
 524                                        "PC16";
 525                                 function = "mmc2";
 526                                 drive-strength = <30>;
 527                                 bias-pull-up;
 528                         };
 529
 530                         uart0_pins_a: uart0@0 {
 531                                 pins = "PH12", "PH13";
 532                                 function = "uart0";
 533                         };
 534
 535                         uart4_pins_a: uart4@0 {
 536                                 pins = "PG12", "PG13", "PG14", "PG15";
 537                                 function = "uart4";
 538                         };
 539                 };
 540
 541                 uart0: serial@07000000 {
 542                         compatible = "snps,dw-apb-uart";
 543                         reg = <0x07000000 0x400>;
 544                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 545                         reg-shift = <2>;
 546                         reg-io-width = <4>;
 547                         clocks = <&ccu CLK_BUS_UART0>;
 548                         resets = <&ccu RST_BUS_UART0>;
 549                         status = "disabled";
 550                 };
 551
 552                 uart1: serial@07000400 {
 553                         compatible = "snps,dw-apb-uart";
 554                         reg = <0x07000400 0x400>;
 555                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 556                         reg-shift = <2>;
 557                         reg-io-width = <4>;
 558                         clocks = <&ccu CLK_BUS_UART1>;
 559                         resets = <&ccu RST_BUS_UART1>;
 560                         status = "disabled";
 561                 };
 562
 563                 uart2: serial@07000800 {
 564                         compatible = "snps,dw-apb-uart";
 565                         reg = <0x07000800 0x400>;
 566                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 567                         reg-shift = <2>;
 568                         reg-io-width = <4>;
 569                         clocks = <&ccu CLK_BUS_UART2>;
 570                         resets = <&ccu RST_BUS_UART2>;
 571                         status = "disabled";
 572                 };
 573
 574                 uart3: serial@07000c00 {
 575                         compatible = "snps,dw-apb-uart";
 576                         reg = <0x07000c00 0x400>;
 577                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 578                         reg-shift = <2>;
 579                         reg-io-width = <4>;
 580                         clocks = <&ccu CLK_BUS_UART3>;
 581                         resets = <&ccu RST_BUS_UART3>;
 582                         status = "disabled";
 583                 };
 584
 585                 uart4: serial@07001000 {
 586                         compatible = "snps,dw-apb-uart";
 587                         reg = <0x07001000 0x400>;
 588                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 589                         reg-shift = <2>;
 590                         reg-io-width = <4>;
 591                         clocks = <&ccu CLK_BUS_UART4>;
 592                         resets = <&ccu RST_BUS_UART4>;
 593                         status = "disabled";
 594                 };
 595
 596                 uart5: serial@07001400 {
 597                         compatible = "snps,dw-apb-uart";
 598                         reg = <0x07001400 0x400>;
 599                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 600                         reg-shift = <2>;
 601                         reg-io-width = <4>;
 602                         clocks = <&ccu CLK_BUS_UART5>;
 603                         resets = <&ccu RST_BUS_UART5>;
 604                         status = "disabled";
 605                 };
 606
 607                 i2c0: i2c@07002800 {
 608                         compatible = "allwinner,sun6i-a31-i2c";
 609                         reg = <0x07002800 0x400>;
 610                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 611                         clocks = <&ccu CLK_BUS_I2C0>;
 612                         resets = <&ccu RST_BUS_I2C0>;
 613                         status = "disabled";
 614                         #address-cells = <1>;
 615                         #size-cells = <0>;
 616                 };
 617
 618                 i2c1: i2c@07002c00 {
 619                         compatible = "allwinner,sun6i-a31-i2c";
 620                         reg = <0x07002c00 0x400>;
 621                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 622                         clocks = <&ccu CLK_BUS_I2C1>;
 623                         resets = <&ccu RST_BUS_I2C1>;
 624                         status = "disabled";
 625                         #address-cells = <1>;
 626                         #size-cells = <0>;
 627                 };
 628
 629                 i2c2: i2c@07003000 {
 630                         compatible = "allwinner,sun6i-a31-i2c";
 631                         reg = <0x07003000 0x400>;
 632                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 633                         clocks = <&ccu CLK_BUS_I2C2>;
 634                         resets = <&ccu RST_BUS_I2C2>;
 635                         status = "disabled";
 636                         #address-cells = <1>;
 637                         #size-cells = <0>;
 638                 };
 639
 640                 i2c3: i2c@07003400 {
 641                         compatible = "allwinner,sun6i-a31-i2c";
 642                         reg = <0x07003400 0x400>;
 643                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 644                         clocks = <&ccu CLK_BUS_I2C3>;
 645                         resets = <&ccu RST_BUS_I2C3>;
 646                         status = "disabled";
 647                         #address-cells = <1>;
 648                         #size-cells = <0>;
 649                 };
 650
 651                 i2c4: i2c@07003800 {
 652                         compatible = "allwinner,sun6i-a31-i2c";
 653                         reg = <0x07003800 0x400>;
 654                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 655                         clocks = <&ccu CLK_BUS_I2C4>;
 656                         resets = <&ccu RST_BUS_I2C4>;
 657                         status = "disabled";
 658                         #address-cells = <1>;
 659                         #size-cells = <0>;
 660                 };
 661
 662                 r_wdt: watchdog@08001000 {
 663                         compatible = "allwinner,sun6i-a31-wdt";
 664                         reg = <0x08001000 0x20>;
 665                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 666                 };
 667
 668                 apbs_rst: reset@080014b0 {
 669                         reg = <0x080014b0 0x4>;
 670                         compatible = "allwinner,sun6i-a31-clock-reset";
 671                         #reset-cells = <1>;
 672                 };
 673
 674                 nmi_intc: interrupt-controller@080015a0 {
 675                         compatible = "allwinner,sun9i-a80-nmi";
 676                         interrupt-controller;
 677                         #interrupt-cells = <2>;
 678                         reg = <0x080015a0 0xc>;
 679                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 680                 };
 681
 682                 r_ir: ir@08002000 {
 683                         compatible = "allwinner,sun5i-a13-ir";
 684                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 685                         pinctrl-names = "default";
 686                         pinctrl-0 = <&r_ir_pins>;
 687                         clocks = <&apbs_gates 1>, <&r_ir_clk>;
 688                         clock-names = "apb", "ir";
 689                         resets = <&apbs_rst 1>;
 690                         reg = <0x08002000 0x40>;
 691                         status = "disabled";
 692                 };
 693
 694                 r_uart: serial@08002800 {
 695                         compatible = "snps,dw-apb-uart";
 696                         reg = <0x08002800 0x400>;
 697                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 698                         reg-shift = <2>;
 699                         reg-io-width = <4>;
 700                         clocks = <&apbs_gates 4>;
 701                         resets = <&apbs_rst 4>;
 702                         status = "disabled";
 703                 };
 704
 705                 r_pio: pinctrl@08002c00 {
 706                         compatible = "allwinner,sun9i-a80-r-pinctrl";
 707                         reg = <0x08002c00 0x400>;
 708                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
 709                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 710                         clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>;
 711                         clock-names = "apb", "hosc", "losc";
 712                         resets = <&apbs_rst 0>;
 713                         gpio-controller;
 714                         interrupt-controller;
 715                         #interrupt-cells = <3>;
 716                         #gpio-cells = <3>;
 717
 718                         r_ir_pins: r_ir {
 719                                 pins = "PL6";
 720                                 function = "s_cir_rx";
 721                         };
 722
 723                         r_rsb_pins: r_rsb {
 724                                 pins = "PN0", "PN1";
 725                                 function = "s_rsb";
 726                                 drive-strength = <20>;
 727                                 bias-pull-up;
 728                         };
 729                 };
 730
 731                 r_rsb: i2c@08003400 {
 732                         compatible = "allwinner,sun8i-a23-rsb";
 733                         reg = <0x08003400 0x400>;
 734                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 735                         clocks = <&apbs_gates 3>;
 736                         clock-frequency = <3000000>;
 737                         resets = <&apbs_rst 3>;
 738                         pinctrl-names = "default";
 739                         pinctrl-0 = <&r_rsb_pins>;
 740                         status = "disabled";
 741                         #address-cells = <1>;
 742                         #size-cells = <0>;
 743                 };
 744         };
 745 };