2 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/sun8i-h3-ccu.h>
44 #include <dt-bindings/interrupt-controller/arm-gic.h>
45 #include <dt-bindings/reset/sun8i-h3-ccu.h>
48 interrupt-parent = <&gic>;
59 compatible = "fixed-clock";
60 clock-frequency = <24000000>;
61 clock-output-names = "osc24M";
66 compatible = "fixed-clock";
67 clock-frequency = <32768>;
68 clock-output-names = "osc32k";
71 iosc: internal-osc-clk {
73 compatible = "fixed-clock";
74 clock-frequency = <16000000>;
75 clock-accuracy = <300000000>;
76 clock-output-names = "iosc";
81 compatible = "simple-bus";
86 dma: dma-controller@01c02000 {
87 compatible = "allwinner,sun8i-h3-dma";
88 reg = <0x01c02000 0x1000>;
89 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
90 clocks = <&ccu CLK_BUS_DMA>;
91 resets = <&ccu RST_BUS_DMA>;
96 /* compatible and clocks are in per SoC .dtsi file */
97 reg = <0x01c0f000 0x1000>;
98 resets = <&ccu RST_BUS_MMC0>;
100 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
102 #address-cells = <1>;
107 /* compatible and clocks are in per SoC .dtsi file */
108 reg = <0x01c10000 0x1000>;
109 resets = <&ccu RST_BUS_MMC1>;
111 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
113 #address-cells = <1>;
118 /* compatible and clocks are in per SoC .dtsi file */
119 reg = <0x01c11000 0x1000>;
120 resets = <&ccu RST_BUS_MMC2>;
122 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
124 #address-cells = <1>;
128 usb_otg: usb@01c19000 {
129 compatible = "allwinner,sun8i-h3-musb";
130 reg = <0x01c19000 0x400>;
131 clocks = <&ccu CLK_BUS_OTG>;
132 resets = <&ccu RST_BUS_OTG>;
133 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
134 interrupt-names = "mc";
137 extcon = <&usbphy 0>;
141 usbphy: phy@01c19400 {
142 compatible = "allwinner,sun8i-h3-usb-phy";
143 reg = <0x01c19400 0x2c>,
148 reg-names = "phy_ctrl",
153 clocks = <&ccu CLK_USB_PHY0>,
157 clock-names = "usb0_phy",
161 resets = <&ccu RST_USB_PHY0>,
165 reset-names = "usb0_reset",
173 ehci0: usb@01c1a000 {
174 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
175 reg = <0x01c1a000 0x100>;
176 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
177 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
178 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
182 ohci0: usb@01c1a400 {
183 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
184 reg = <0x01c1a400 0x100>;
185 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
186 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
187 <&ccu CLK_USB_OHCI0>;
188 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
192 ehci1: usb@01c1b000 {
193 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
194 reg = <0x01c1b000 0x100>;
195 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
197 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
203 ohci1: usb@01c1b400 {
204 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
205 reg = <0x01c1b400 0x100>;
206 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
208 <&ccu CLK_USB_OHCI1>;
209 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
215 ehci2: usb@01c1c000 {
216 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
217 reg = <0x01c1c000 0x100>;
218 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
220 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
226 ohci2: usb@01c1c400 {
227 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
228 reg = <0x01c1c400 0x100>;
229 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
231 <&ccu CLK_USB_OHCI2>;
232 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
238 ehci3: usb@01c1d000 {
239 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
240 reg = <0x01c1d000 0x100>;
241 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
243 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
249 ohci3: usb@01c1d400 {
250 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
251 reg = <0x01c1d400 0x100>;
252 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
254 <&ccu CLK_USB_OHCI3>;
255 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
261 ccu: clock@01c20000 {
262 /* compatible is in per SoC .dtsi file */
263 reg = <0x01c20000 0x400>;
264 clocks = <&osc24M>, <&osc32k>;
265 clock-names = "hosc", "losc";
270 pio: pinctrl@01c20800 {
271 /* compatible is in per SoC .dtsi file */
272 reg = <0x01c20800 0x400>;
273 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
275 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
276 clock-names = "apb", "hosc", "losc";
279 interrupt-controller;
280 #interrupt-cells = <3>;
283 pins = "PA11", "PA12";
288 pins = "PA18", "PA19";
293 pins = "PE12", "PE13";
297 mmc0_pins_a: mmc0@0 {
298 pins = "PF0", "PF1", "PF2", "PF3",
301 drive-strength = <30>;
305 mmc0_cd_pin: mmc0_cd_pin@0 {
307 function = "gpio_in";
311 mmc1_pins_a: mmc1@0 {
312 pins = "PG0", "PG1", "PG2", "PG3",
315 drive-strength = <30>;
319 mmc2_8bit_pins: mmc2_8bit {
320 pins = "PC5", "PC6", "PC8",
321 "PC9", "PC10", "PC11",
322 "PC12", "PC13", "PC14",
325 drive-strength = <30>;
329 spdif_tx_pins_a: spdif@0 {
335 pins = "PC0", "PC1", "PC2", "PC3";
340 pins = "PA15", "PA16", "PA14", "PA13";
344 uart0_pins_a: uart0@0 {
354 uart1_rts_cts_pins: uart1_rts_cts {
365 pins = "PA13", "PA14";
371 compatible = "allwinner,sun4i-a10-timer";
372 reg = <0x01c20c00 0xa0>;
373 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
374 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
379 compatible = "allwinner,sun8i-h3-spi";
380 reg = <0x01c68000 0x1000>;
381 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
382 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
383 clock-names = "ahb", "mod";
384 dmas = <&dma 23>, <&dma 23>;
385 dma-names = "rx", "tx";
386 pinctrl-names = "default";
387 pinctrl-0 = <&spi0_pins>;
388 resets = <&ccu RST_BUS_SPI0>;
390 #address-cells = <1>;
395 compatible = "allwinner,sun8i-h3-spi";
396 reg = <0x01c69000 0x1000>;
397 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
399 clock-names = "ahb", "mod";
400 dmas = <&dma 24>, <&dma 24>;
401 dma-names = "rx", "tx";
402 pinctrl-names = "default";
403 pinctrl-0 = <&spi1_pins>;
404 resets = <&ccu RST_BUS_SPI1>;
406 #address-cells = <1>;
410 wdt0: watchdog@01c20ca0 {
411 compatible = "allwinner,sun6i-a31-wdt";
412 reg = <0x01c20ca0 0x20>;
413 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
416 spdif: spdif@01c21000 {
417 #sound-dai-cells = <0>;
418 compatible = "allwinner,sun8i-h3-spdif";
419 reg = <0x01c21000 0x400>;
420 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
422 resets = <&ccu RST_BUS_SPDIF>;
423 clock-names = "apb", "spdif";
430 compatible = "allwinner,sun8i-h3-pwm";
431 reg = <0x01c21400 0x8>;
437 codec: codec@01c22c00 {
438 #sound-dai-cells = <0>;
439 compatible = "allwinner,sun8i-h3-codec";
440 reg = <0x01c22c00 0x400>;
441 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
443 clock-names = "apb", "codec";
444 resets = <&ccu RST_BUS_CODEC>;
445 dmas = <&dma 15>, <&dma 15>;
446 dma-names = "rx", "tx";
447 allwinner,codec-analog-controls = <&codec_analog>;
451 uart0: serial@01c28000 {
452 compatible = "snps,dw-apb-uart";
453 reg = <0x01c28000 0x400>;
454 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&ccu CLK_BUS_UART0>;
458 resets = <&ccu RST_BUS_UART0>;
459 dmas = <&dma 6>, <&dma 6>;
460 dma-names = "rx", "tx";
464 uart1: serial@01c28400 {
465 compatible = "snps,dw-apb-uart";
466 reg = <0x01c28400 0x400>;
467 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
470 clocks = <&ccu CLK_BUS_UART1>;
471 resets = <&ccu RST_BUS_UART1>;
472 dmas = <&dma 7>, <&dma 7>;
473 dma-names = "rx", "tx";
477 uart2: serial@01c28800 {
478 compatible = "snps,dw-apb-uart";
479 reg = <0x01c28800 0x400>;
480 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
483 clocks = <&ccu CLK_BUS_UART2>;
484 resets = <&ccu RST_BUS_UART2>;
485 dmas = <&dma 8>, <&dma 8>;
486 dma-names = "rx", "tx";
490 uart3: serial@01c28c00 {
491 compatible = "snps,dw-apb-uart";
492 reg = <0x01c28c00 0x400>;
493 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&ccu CLK_BUS_UART3>;
497 resets = <&ccu RST_BUS_UART3>;
498 dmas = <&dma 9>, <&dma 9>;
499 dma-names = "rx", "tx";
504 compatible = "allwinner,sun6i-a31-i2c";
505 reg = <0x01c2ac00 0x400>;
506 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
507 clocks = <&ccu CLK_BUS_I2C0>;
508 resets = <&ccu RST_BUS_I2C0>;
509 pinctrl-names = "default";
510 pinctrl-0 = <&i2c0_pins>;
512 #address-cells = <1>;
517 compatible = "allwinner,sun6i-a31-i2c";
518 reg = <0x01c2b000 0x400>;
519 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
520 clocks = <&ccu CLK_BUS_I2C1>;
521 resets = <&ccu RST_BUS_I2C1>;
522 pinctrl-names = "default";
523 pinctrl-0 = <&i2c1_pins>;
525 #address-cells = <1>;
530 compatible = "allwinner,sun6i-a31-i2c";
531 reg = <0x01c2b000 0x400>;
532 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&ccu CLK_BUS_I2C2>;
534 resets = <&ccu RST_BUS_I2C2>;
535 pinctrl-names = "default";
536 pinctrl-0 = <&i2c2_pins>;
538 #address-cells = <1>;
542 gic: interrupt-controller@01c81000 {
543 compatible = "arm,gic-400";
544 reg = <0x01c81000 0x1000>,
548 interrupt-controller;
549 #interrupt-cells = <3>;
550 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
554 compatible = "allwinner,sun6i-a31-rtc";
555 reg = <0x01f00000 0x54>;
556 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
560 r_ccu: clock@1f01400 {
561 compatible = "allwinner,sun8i-h3-r-ccu";
562 reg = <0x01f01400 0x100>;
563 clocks = <&osc24M>, <&osc32k>, <&iosc>,
565 clock-names = "hosc", "losc", "iosc", "pll-periph";
570 codec_analog: codec-analog@01f015c0 {
571 compatible = "allwinner,sun8i-h3-codec-analog";
572 reg = <0x01f015c0 0x4>;
576 compatible = "allwinner,sun5i-a13-ir";
577 clocks = <&r_ccu 4>, <&r_ccu 11>;
578 clock-names = "apb", "ir";
580 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
581 reg = <0x01f02000 0x40>;
585 r_pio: pinctrl@01f02c00 {
586 compatible = "allwinner,sun8i-h3-r-pinctrl";
587 reg = <0x01f02c00 0x400>;
588 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
589 clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>;
590 clock-names = "apb", "hosc", "losc";
593 interrupt-controller;
594 #interrupt-cells = <3>;
598 function = "s_cir_rx";