1 #include <dt-bindings/clock/tegra114-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include "skeleton.dtsi"
8 compatible = "nvidia,tegra114";
9 interrupt-parent = <&gic>;
18 gic: interrupt-controller {
19 compatible = "arm,cortex-a15-gic";
20 #interrupt-cells = <3>;
22 reg = <0x50041000 0x1000>,
26 interrupts = <GIC_PPI 9
27 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
31 compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
32 reg = <0x60005000 0x400>;
33 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
34 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
35 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
36 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
37 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
38 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
39 clocks = <&tegra_car TEGRA114_CLK_TIMER>;
43 compatible = "nvidia,tegra114-car";
44 reg = <0x60006000 0x1000>;
50 compatible = "nvidia,tegra114-apbdma";
51 reg = <0x6000a000 0x1400>;
52 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
53 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
54 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
55 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
56 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
57 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
58 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
59 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
62 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
63 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
64 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
65 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
66 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
68 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
69 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
70 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
72 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
73 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
74 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
75 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
77 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
78 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
79 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
84 clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
85 resets = <&tegra_car 34>;
91 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
92 reg = <0x6000c004 0x14c>;
96 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
97 reg = <0x6000d000 0x1000>;
98 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
100 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
101 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
102 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
108 #interrupt-cells = <2>;
109 interrupt-controller;
113 compatible = "nvidia,tegra114-pinmux";
114 reg = <0x70000868 0x148 /* Pad control registers */
115 0x70003000 0x40c>; /* Mux registers */
119 * There are two serial driver i.e. 8250 based simple serial
120 * driver and APB DMA based serial driver for higher baudrate
121 * and performace. To enable the 8250 based driver, the compatible
122 * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
123 * the APB DMA based serial driver, the comptible is
124 * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
126 uarta: serial@70006000 {
127 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
128 reg = <0x70006000 0x40>;
130 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
131 clocks = <&tegra_car TEGRA114_CLK_UARTA>;
132 resets = <&tegra_car 6>;
133 reset-names = "serial";
134 dmas = <&apbdma 8>, <&apbdma 8>;
135 dma-names = "rx", "tx";
139 uartb: serial@70006040 {
140 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
141 reg = <0x70006040 0x40>;
143 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
144 clocks = <&tegra_car TEGRA114_CLK_UARTB>;
145 resets = <&tegra_car 7>;
146 reset-names = "serial";
147 dmas = <&apbdma 9>, <&apbdma 9>;
148 dma-names = "rx", "tx";
152 uartc: serial@70006200 {
153 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
154 reg = <0x70006200 0x100>;
156 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
157 clocks = <&tegra_car TEGRA114_CLK_UARTC>;
158 resets = <&tegra_car 55>;
159 reset-names = "serial";
160 dmas = <&apbdma 10>, <&apbdma 10>;
161 dma-names = "rx", "tx";
165 uartd: serial@70006300 {
166 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
167 reg = <0x70006300 0x100>;
169 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
170 clocks = <&tegra_car TEGRA114_CLK_UARTD>;
171 resets = <&tegra_car 65>;
172 reset-names = "serial";
173 dmas = <&apbdma 19>, <&apbdma 19>;
174 dma-names = "rx", "tx";
179 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
180 reg = <0x7000a000 0x100>;
182 clocks = <&tegra_car TEGRA114_CLK_PWM>;
183 resets = <&tegra_car 17>;
189 compatible = "nvidia,tegra114-i2c";
190 reg = <0x7000c000 0x100>;
191 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
192 #address-cells = <1>;
194 clocks = <&tegra_car TEGRA114_CLK_I2C1>;
195 clock-names = "div-clk";
196 resets = <&tegra_car 12>;
198 dmas = <&apbdma 21>, <&apbdma 21>;
199 dma-names = "rx", "tx";
204 compatible = "nvidia,tegra114-i2c";
205 reg = <0x7000c400 0x100>;
206 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
207 #address-cells = <1>;
209 clocks = <&tegra_car TEGRA114_CLK_I2C2>;
210 clock-names = "div-clk";
211 resets = <&tegra_car 54>;
213 dmas = <&apbdma 22>, <&apbdma 22>;
214 dma-names = "rx", "tx";
219 compatible = "nvidia,tegra114-i2c";
220 reg = <0x7000c500 0x100>;
221 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
222 #address-cells = <1>;
224 clocks = <&tegra_car TEGRA114_CLK_I2C3>;
225 clock-names = "div-clk";
226 resets = <&tegra_car 67>;
228 dmas = <&apbdma 23>, <&apbdma 23>;
229 dma-names = "rx", "tx";
234 compatible = "nvidia,tegra114-i2c";
235 reg = <0x7000c700 0x100>;
236 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
237 #address-cells = <1>;
239 clocks = <&tegra_car TEGRA114_CLK_I2C4>;
240 clock-names = "div-clk";
241 resets = <&tegra_car 103>;
243 dmas = <&apbdma 26>, <&apbdma 26>;
244 dma-names = "rx", "tx";
249 compatible = "nvidia,tegra114-i2c";
250 reg = <0x7000d000 0x100>;
251 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
252 #address-cells = <1>;
254 clocks = <&tegra_car TEGRA114_CLK_I2C5>;
255 clock-names = "div-clk";
256 resets = <&tegra_car 47>;
258 dmas = <&apbdma 24>, <&apbdma 24>;
259 dma-names = "rx", "tx";
264 compatible = "nvidia,tegra114-spi";
265 reg = <0x7000d400 0x200>;
266 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
267 #address-cells = <1>;
269 clocks = <&tegra_car TEGRA114_CLK_SBC1>;
271 resets = <&tegra_car 41>;
273 dmas = <&apbdma 15>, <&apbdma 15>;
274 dma-names = "rx", "tx";
279 compatible = "nvidia,tegra114-spi";
280 reg = <0x7000d600 0x200>;
281 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
282 #address-cells = <1>;
284 clocks = <&tegra_car TEGRA114_CLK_SBC2>;
286 resets = <&tegra_car 44>;
288 dmas = <&apbdma 16>, <&apbdma 16>;
289 dma-names = "rx", "tx";
294 compatible = "nvidia,tegra114-spi";
295 reg = <0x7000d800 0x200>;
296 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
297 #address-cells = <1>;
299 clocks = <&tegra_car TEGRA114_CLK_SBC3>;
301 resets = <&tegra_car 46>;
303 dmas = <&apbdma 17>, <&apbdma 17>;
304 dma-names = "rx", "tx";
309 compatible = "nvidia,tegra114-spi";
310 reg = <0x7000da00 0x200>;
311 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
312 #address-cells = <1>;
314 clocks = <&tegra_car TEGRA114_CLK_SBC4>;
316 resets = <&tegra_car 68>;
318 dmas = <&apbdma 18>, <&apbdma 18>;
319 dma-names = "rx", "tx";
324 compatible = "nvidia,tegra114-spi";
325 reg = <0x7000dc00 0x200>;
326 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
327 #address-cells = <1>;
329 clocks = <&tegra_car TEGRA114_CLK_SBC5>;
331 resets = <&tegra_car 104>;
333 dmas = <&apbdma 27>, <&apbdma 27>;
334 dma-names = "rx", "tx";
339 compatible = "nvidia,tegra114-spi";
340 reg = <0x7000de00 0x200>;
341 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
342 #address-cells = <1>;
344 clocks = <&tegra_car TEGRA114_CLK_SBC6>;
346 resets = <&tegra_car 105>;
348 dmas = <&apbdma 28>, <&apbdma 28>;
349 dma-names = "rx", "tx";
354 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
355 reg = <0x7000e000 0x100>;
356 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&tegra_car TEGRA114_CLK_RTC>;
361 compatible = "nvidia,tegra114-kbc";
362 reg = <0x7000e200 0x100>;
363 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
364 clocks = <&tegra_car TEGRA114_CLK_KBC>;
365 resets = <&tegra_car 36>;
371 compatible = "nvidia,tegra114-pmc";
372 reg = <0x7000e400 0x400>;
373 clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
374 clock-names = "pclk", "clk32k_in";
378 compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
379 reg = <0x70019010 0x02c
383 dma-window = <0 0x40000000>;
384 nvidia,swgroups = <0x18659fe>;
389 compatible = "nvidia,tegra114-ahub";
390 reg = <0x70080000 0x200>,
393 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
394 clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
395 <&tegra_car TEGRA114_CLK_APBIF>;
396 clock-names = "d_audio", "apbif";
397 resets = <&tegra_car 106>, /* d_audio */
398 <&tegra_car 107>, /* apbif */
399 <&tegra_car 30>, /* i2s0 */
400 <&tegra_car 11>, /* i2s1 */
401 <&tegra_car 18>, /* i2s2 */
402 <&tegra_car 101>, /* i2s3 */
403 <&tegra_car 102>, /* i2s4 */
404 <&tegra_car 108>, /* dam0 */
405 <&tegra_car 109>, /* dam1 */
406 <&tegra_car 110>, /* dam2 */
407 <&tegra_car 10>, /* spdif */
408 <&tegra_car 153>, /* amx */
409 <&tegra_car 154>; /* adx */
410 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
411 "i2s3", "i2s4", "dam0", "dam1", "dam2",
412 "spdif", "amx", "adx";
413 dmas = <&apbdma 1>, <&apbdma 1>,
414 <&apbdma 2>, <&apbdma 2>,
415 <&apbdma 3>, <&apbdma 3>,
416 <&apbdma 4>, <&apbdma 4>,
417 <&apbdma 6>, <&apbdma 6>,
418 <&apbdma 7>, <&apbdma 7>,
419 <&apbdma 12>, <&apbdma 12>,
420 <&apbdma 13>, <&apbdma 13>,
421 <&apbdma 14>, <&apbdma 14>,
422 <&apbdma 29>, <&apbdma 29>;
423 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
424 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
425 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
428 #address-cells = <1>;
431 tegra_i2s0: i2s@70080300 {
432 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
433 reg = <0x70080300 0x100>;
434 nvidia,ahub-cif-ids = <4 4>;
435 clocks = <&tegra_car TEGRA114_CLK_I2S0>;
436 resets = <&tegra_car 30>;
441 tegra_i2s1: i2s@70080400 {
442 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
443 reg = <0x70080400 0x100>;
444 nvidia,ahub-cif-ids = <5 5>;
445 clocks = <&tegra_car TEGRA114_CLK_I2S1>;
446 resets = <&tegra_car 11>;
451 tegra_i2s2: i2s@70080500 {
452 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
453 reg = <0x70080500 0x100>;
454 nvidia,ahub-cif-ids = <6 6>;
455 clocks = <&tegra_car TEGRA114_CLK_I2S2>;
456 resets = <&tegra_car 18>;
461 tegra_i2s3: i2s@70080600 {
462 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
463 reg = <0x70080600 0x100>;
464 nvidia,ahub-cif-ids = <7 7>;
465 clocks = <&tegra_car TEGRA114_CLK_I2S3>;
466 resets = <&tegra_car 101>;
471 tegra_i2s4: i2s@70080700 {
472 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
473 reg = <0x70080700 0x100>;
474 nvidia,ahub-cif-ids = <8 8>;
475 clocks = <&tegra_car TEGRA114_CLK_I2S4>;
476 resets = <&tegra_car 102>;
483 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
484 reg = <0x78000000 0x200>;
485 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
486 clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
487 resets = <&tegra_car 14>;
488 reset-names = "sdhci";
493 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
494 reg = <0x78000200 0x200>;
495 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
497 resets = <&tegra_car 9>;
498 reset-names = "sdhci";
503 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
504 reg = <0x78000400 0x200>;
505 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
506 clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
507 resets = <&tegra_car 69>;
508 reset-names = "sdhci";
513 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
514 reg = <0x78000600 0x200>;
515 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
516 clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
517 resets = <&tegra_car 15>;
518 reset-names = "sdhci";
523 compatible = "nvidia,tegra30-ehci", "usb-ehci";
524 reg = <0x7d000000 0x4000>;
525 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
527 clocks = <&tegra_car TEGRA114_CLK_USBD>;
528 resets = <&tegra_car 22>;
530 nvidia,phy = <&phy1>;
534 phy1: usb-phy@7d000000 {
535 compatible = "nvidia,tegra30-usb-phy";
536 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
538 clocks = <&tegra_car TEGRA114_CLK_USBD>,
539 <&tegra_car TEGRA114_CLK_PLL_U>,
540 <&tegra_car TEGRA114_CLK_USBD>;
541 clock-names = "reg", "pll_u", "utmi-pads";
542 nvidia,hssync-start-delay = <0>;
543 nvidia,idle-wait-delay = <17>;
544 nvidia,elastic-limit = <16>;
545 nvidia,term-range-adj = <6>;
546 nvidia,xcvr-setup = <9>;
547 nvidia,xcvr-lsfslew = <0>;
548 nvidia,xcvr-lsrslew = <3>;
549 nvidia,hssquelch-level = <2>;
550 nvidia,hsdiscon-level = <5>;
551 nvidia,xcvr-hsslew = <12>;
556 compatible = "nvidia,tegra30-ehci", "usb-ehci";
557 reg = <0x7d008000 0x4000>;
558 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
560 clocks = <&tegra_car TEGRA114_CLK_USB3>;
561 resets = <&tegra_car 59>;
563 nvidia,phy = <&phy3>;
567 phy3: usb-phy@7d008000 {
568 compatible = "nvidia,tegra30-usb-phy";
569 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
571 clocks = <&tegra_car TEGRA114_CLK_USB3>,
572 <&tegra_car TEGRA114_CLK_PLL_U>,
573 <&tegra_car TEGRA114_CLK_USBD>;
574 clock-names = "reg", "pll_u", "utmi-pads";
575 nvidia,hssync-start-delay = <0>;
576 nvidia,idle-wait-delay = <17>;
577 nvidia,elastic-limit = <16>;
578 nvidia,term-range-adj = <6>;
579 nvidia,xcvr-setup = <9>;
580 nvidia,xcvr-lsfslew = <0>;
581 nvidia,xcvr-lsrslew = <3>;
582 nvidia,hssquelch-level = <2>;
583 nvidia,hsdiscon-level = <5>;
584 nvidia,xcvr-hsslew = <12>;
589 #address-cells = <1>;
594 compatible = "arm,cortex-a15";
600 compatible = "arm,cortex-a15";
606 compatible = "arm,cortex-a15";
612 compatible = "arm,cortex-a15";
618 compatible = "arm,armv7-timer";
621 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
623 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
625 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
627 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;