1 #include <dt-bindings/gpio/tegra-gpio.h>
2 #include <dt-bindings/interrupt-controller/arm-gic.h>
4 #include "skeleton.dtsi"
7 compatible = "nvidia,tegra124";
8 interrupt-parent = <&gic>;
10 gic: interrupt-controller@50041000 {
11 compatible = "arm,cortex-a15-gic";
12 #interrupt-cells = <3>;
14 reg = <0x50041000 0x1000>,
18 interrupts = <GIC_PPI 9
19 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
23 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
24 reg = <0x60005000 0x400>;
25 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
26 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
27 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
28 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
29 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
30 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
34 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
35 reg = <0x6000d000 0x1000>;
36 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
37 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
38 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
39 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
40 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
41 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
42 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
43 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
46 #interrupt-cells = <2>;
51 * There are two serial driver i.e. 8250 based simple serial
52 * driver and APB DMA based serial driver for higher baudrate
53 * and performace. To enable the 8250 based driver, the compatible
54 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
55 * the APB DMA based serial driver, the comptible is
56 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
59 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
60 reg = <0x70006000 0x40>;
62 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
67 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
68 reg = <0x70006040 0x40>;
70 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
75 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
76 reg = <0x70006200 0x40>;
78 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
83 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
84 reg = <0x70006300 0x40>;
86 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
91 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
92 reg = <0x70006400 0x40>;
94 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
99 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
100 reg = <0x7000e000 0x100>;
101 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
105 compatible = "nvidia,tegra124-pmc";
106 reg = <0x7000e400 0x400>;
110 #address-cells = <1>;
115 compatible = "arm,cortex-a15";
121 compatible = "arm,cortex-a15";
127 compatible = "arm,cortex-a15";
133 compatible = "arm,cortex-a15";
139 compatible = "arm,armv7-timer";
140 interrupts = <GIC_PPI 13
141 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
143 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
145 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
147 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;