1 #include <dt-bindings/clock/tegra20-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include "skeleton.dtsi"
9 compatible = "nvidia,tegra20";
10 interrupt-parent = <&intc>;
21 compatible = "nvidia,tegra20-host1x", "simple-bus";
22 reg = <0x50000000 0x00024000>;
23 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
24 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
25 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
26 resets = <&tegra_car 28>;
27 reset-names = "host1x";
32 ranges = <0x54000000 0x54000000 0x04000000>;
35 compatible = "nvidia,tegra20-mpe";
36 reg = <0x54040000 0x00040000>;
37 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
38 clocks = <&tegra_car TEGRA20_CLK_MPE>;
39 resets = <&tegra_car 60>;
44 compatible = "nvidia,tegra20-vi";
45 reg = <0x54080000 0x00040000>;
46 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
47 clocks = <&tegra_car TEGRA20_CLK_VI>;
48 resets = <&tegra_car 20>;
53 compatible = "nvidia,tegra20-epp";
54 reg = <0x540c0000 0x00040000>;
55 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
56 clocks = <&tegra_car TEGRA20_CLK_EPP>;
57 resets = <&tegra_car 19>;
62 compatible = "nvidia,tegra20-isp";
63 reg = <0x54100000 0x00040000>;
64 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
65 clocks = <&tegra_car TEGRA20_CLK_ISP>;
66 resets = <&tegra_car 23>;
71 compatible = "nvidia,tegra20-gr2d";
72 reg = <0x54140000 0x00040000>;
73 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
74 clocks = <&tegra_car TEGRA20_CLK_GR2D>;
75 resets = <&tegra_car 21>;
80 compatible = "nvidia,tegra20-gr3d";
81 reg = <0x54140000 0x00040000>;
82 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
83 resets = <&tegra_car 24>;
88 compatible = "nvidia,tegra20-dc";
89 reg = <0x54200000 0x00040000>;
90 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
91 clocks = <&tegra_car TEGRA20_CLK_DISP1>,
92 <&tegra_car TEGRA20_CLK_PLL_P>;
93 clock-names = "dc", "parent";
94 resets = <&tegra_car 27>;
103 compatible = "nvidia,tegra20-dc";
104 reg = <0x54240000 0x00040000>;
105 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
106 clocks = <&tegra_car TEGRA20_CLK_DISP2>,
107 <&tegra_car TEGRA20_CLK_PLL_P>;
108 clock-names = "dc", "parent";
109 resets = <&tegra_car 26>;
118 compatible = "nvidia,tegra20-hdmi";
119 reg = <0x54280000 0x00040000>;
120 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
121 clocks = <&tegra_car TEGRA20_CLK_HDMI>,
122 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
123 clock-names = "hdmi", "parent";
124 resets = <&tegra_car 51>;
125 reset-names = "hdmi";
130 compatible = "nvidia,tegra20-tvo";
131 reg = <0x542c0000 0x00040000>;
132 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
133 clocks = <&tegra_car TEGRA20_CLK_TVO>;
138 compatible = "nvidia,tegra20-dsi";
139 reg = <0x542c0000 0x00040000>;
140 clocks = <&tegra_car TEGRA20_CLK_DSI>;
141 resets = <&tegra_car 48>;
148 compatible = "arm,cortex-a9-twd-timer";
149 reg = <0x50040600 0x20>;
150 interrupts = <GIC_PPI 13
151 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
152 clocks = <&tegra_car TEGRA20_CLK_TWD>;
155 intc: interrupt-controller@50041000 {
156 compatible = "arm,cortex-a9-gic";
157 reg = <0x50041000 0x1000
159 interrupt-controller;
160 #interrupt-cells = <3>;
163 cache-controller@50043000 {
164 compatible = "arm,pl310-cache";
165 reg = <0x50043000 0x1000>;
166 arm,data-latency = <5 5 2>;
167 arm,tag-latency = <4 4 2>;
173 compatible = "nvidia,tegra20-timer";
174 reg = <0x60005000 0x60>;
175 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
179 clocks = <&tegra_car TEGRA20_CLK_TIMER>;
182 tegra_car: clock@60006000 {
183 compatible = "nvidia,tegra20-car";
184 reg = <0x60006000 0x1000>;
189 apbdma: dma@6000a000 {
190 compatible = "nvidia,tegra20-apbdma";
191 reg = <0x6000a000 0x1200>;
192 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
208 clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
209 resets = <&tegra_car 34>;
215 compatible = "nvidia,tegra20-ahb";
216 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
219 gpio: gpio@6000d000 {
220 compatible = "nvidia,tegra20-gpio";
221 reg = <0x6000d000 0x1000>;
222 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
225 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
231 #interrupt-cells = <2>;
232 interrupt-controller;
235 pinmux: pinmux@70000014 {
236 compatible = "nvidia,tegra20-pinmux";
237 reg = <0x70000014 0x10 /* Tri-state registers */
238 0x70000080 0x20 /* Mux registers */
239 0x700000a0 0x14 /* Pull-up/down registers */
240 0x70000868 0xa8>; /* Pad control registers */
244 compatible = "nvidia,tegra20-das";
245 reg = <0x70000c00 0x80>;
248 tegra_ac97: ac97@70002000 {
249 compatible = "nvidia,tegra20-ac97";
250 reg = <0x70002000 0x200>;
251 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&tegra_car TEGRA20_CLK_AC97>;
253 resets = <&tegra_car 3>;
254 reset-names = "ac97";
255 dmas = <&apbdma 12>, <&apbdma 12>;
256 dma-names = "rx", "tx";
260 tegra_i2s1: i2s@70002800 {
261 compatible = "nvidia,tegra20-i2s";
262 reg = <0x70002800 0x200>;
263 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&tegra_car TEGRA20_CLK_I2S1>;
265 resets = <&tegra_car 11>;
267 dmas = <&apbdma 2>, <&apbdma 2>;
268 dma-names = "rx", "tx";
272 tegra_i2s2: i2s@70002a00 {
273 compatible = "nvidia,tegra20-i2s";
274 reg = <0x70002a00 0x200>;
275 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
276 clocks = <&tegra_car TEGRA20_CLK_I2S2>;
277 resets = <&tegra_car 18>;
279 dmas = <&apbdma 1>, <&apbdma 1>;
280 dma-names = "rx", "tx";
285 * There are two serial driver i.e. 8250 based simple serial
286 * driver and APB DMA based serial driver for higher baudrate
287 * and performace. To enable the 8250 based driver, the compatible
288 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
289 * driver, the comptible is "nvidia,tegra20-hsuart".
291 uarta: serial@70006000 {
292 compatible = "nvidia,tegra20-uart";
293 reg = <0x70006000 0x40>;
295 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
296 clocks = <&tegra_car TEGRA20_CLK_UARTA>;
297 resets = <&tegra_car 6>;
298 reset-names = "serial";
299 dmas = <&apbdma 8>, <&apbdma 8>;
300 dma-names = "rx", "tx";
304 uartb: serial@70006040 {
305 compatible = "nvidia,tegra20-uart";
306 reg = <0x70006040 0x40>;
308 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&tegra_car TEGRA20_CLK_UARTB>;
310 resets = <&tegra_car 7>;
311 reset-names = "serial";
312 dmas = <&apbdma 9>, <&apbdma 9>;
313 dma-names = "rx", "tx";
317 uartc: serial@70006200 {
318 compatible = "nvidia,tegra20-uart";
319 reg = <0x70006200 0x100>;
321 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&tegra_car TEGRA20_CLK_UARTC>;
323 resets = <&tegra_car 55>;
324 reset-names = "serial";
325 dmas = <&apbdma 10>, <&apbdma 10>;
326 dma-names = "rx", "tx";
330 uartd: serial@70006300 {
331 compatible = "nvidia,tegra20-uart";
332 reg = <0x70006300 0x100>;
334 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
335 clocks = <&tegra_car TEGRA20_CLK_UARTD>;
336 resets = <&tegra_car 65>;
337 reset-names = "serial";
338 dmas = <&apbdma 19>, <&apbdma 19>;
339 dma-names = "rx", "tx";
343 uarte: serial@70006400 {
344 compatible = "nvidia,tegra20-uart";
345 reg = <0x70006400 0x100>;
347 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&tegra_car TEGRA20_CLK_UARTE>;
349 resets = <&tegra_car 66>;
350 reset-names = "serial";
351 dmas = <&apbdma 20>, <&apbdma 20>;
352 dma-names = "rx", "tx";
357 compatible = "nvidia,tegra20-pwm";
358 reg = <0x7000a000 0x100>;
360 clocks = <&tegra_car TEGRA20_CLK_PWM>;
361 resets = <&tegra_car 17>;
367 compatible = "nvidia,tegra20-rtc";
368 reg = <0x7000e000 0x100>;
369 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&tegra_car TEGRA20_CLK_RTC>;
374 compatible = "nvidia,tegra20-i2c";
375 reg = <0x7000c000 0x100>;
376 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
377 #address-cells = <1>;
379 clocks = <&tegra_car TEGRA20_CLK_I2C1>,
380 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
381 clock-names = "div-clk", "fast-clk";
382 resets = <&tegra_car 12>;
384 dmas = <&apbdma 21>, <&apbdma 21>;
385 dma-names = "rx", "tx";
390 compatible = "nvidia,tegra20-sflash";
391 reg = <0x7000c380 0x80>;
392 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
393 #address-cells = <1>;
395 clocks = <&tegra_car TEGRA20_CLK_SPI>;
396 resets = <&tegra_car 43>;
398 dmas = <&apbdma 11>, <&apbdma 11>;
399 dma-names = "rx", "tx";
404 compatible = "nvidia,tegra20-i2c";
405 reg = <0x7000c400 0x100>;
406 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
407 #address-cells = <1>;
409 clocks = <&tegra_car TEGRA20_CLK_I2C2>,
410 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
411 clock-names = "div-clk", "fast-clk";
412 resets = <&tegra_car 54>;
414 dmas = <&apbdma 22>, <&apbdma 22>;
415 dma-names = "rx", "tx";
420 compatible = "nvidia,tegra20-i2c";
421 reg = <0x7000c500 0x100>;
422 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
423 #address-cells = <1>;
425 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
426 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
427 clock-names = "div-clk", "fast-clk";
428 resets = <&tegra_car 67>;
430 dmas = <&apbdma 23>, <&apbdma 23>;
431 dma-names = "rx", "tx";
436 compatible = "nvidia,tegra20-i2c-dvc";
437 reg = <0x7000d000 0x200>;
438 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
439 #address-cells = <1>;
441 clocks = <&tegra_car TEGRA20_CLK_DVC>,
442 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
443 clock-names = "div-clk", "fast-clk";
444 resets = <&tegra_car 47>;
446 dmas = <&apbdma 24>, <&apbdma 24>;
447 dma-names = "rx", "tx";
452 compatible = "nvidia,tegra20-slink";
453 reg = <0x7000d400 0x200>;
454 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
455 #address-cells = <1>;
457 clocks = <&tegra_car TEGRA20_CLK_SBC1>;
458 resets = <&tegra_car 41>;
460 dmas = <&apbdma 15>, <&apbdma 15>;
461 dma-names = "rx", "tx";
466 compatible = "nvidia,tegra20-slink";
467 reg = <0x7000d600 0x200>;
468 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
469 #address-cells = <1>;
471 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
472 resets = <&tegra_car 44>;
474 dmas = <&apbdma 16>, <&apbdma 16>;
475 dma-names = "rx", "tx";
480 compatible = "nvidia,tegra20-slink";
481 reg = <0x7000d800 0x200>;
482 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
483 #address-cells = <1>;
485 clocks = <&tegra_car TEGRA20_CLK_SBC3>;
486 resets = <&tegra_car 46>;
488 dmas = <&apbdma 17>, <&apbdma 17>;
489 dma-names = "rx", "tx";
494 compatible = "nvidia,tegra20-slink";
495 reg = <0x7000da00 0x200>;
496 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
497 #address-cells = <1>;
499 clocks = <&tegra_car TEGRA20_CLK_SBC4>;
500 resets = <&tegra_car 68>;
502 dmas = <&apbdma 18>, <&apbdma 18>;
503 dma-names = "rx", "tx";
508 compatible = "nvidia,tegra20-kbc";
509 reg = <0x7000e200 0x100>;
510 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&tegra_car TEGRA20_CLK_KBC>;
512 resets = <&tegra_car 36>;
518 compatible = "nvidia,tegra20-pmc";
519 reg = <0x7000e400 0x400>;
520 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
521 clock-names = "pclk", "clk32k_in";
524 memory-controller@7000f000 {
525 compatible = "nvidia,tegra20-mc";
526 reg = <0x7000f000 0x024
528 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
532 compatible = "nvidia,tegra20-gart";
533 reg = <0x7000f024 0x00000018 /* controller registers */
534 0x58000000 0x02000000>; /* GART aperture */
537 memory-controller@7000f400 {
538 compatible = "nvidia,tegra20-emc";
539 reg = <0x7000f400 0x200>;
540 #address-cells = <1>;
544 pcie-controller@80003000 {
545 compatible = "nvidia,tegra20-pcie";
547 reg = <0x80003000 0x00000800 /* PADS registers */
548 0x80003800 0x00000200 /* AFI registers */
549 0x90000000 0x10000000>; /* configuration space */
550 reg-names = "pads", "afi", "cs";
551 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
552 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
553 interrupt-names = "intr", "msi";
555 bus-range = <0x00 0xff>;
556 #address-cells = <3>;
559 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
560 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
561 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
562 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */
563 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
565 clocks = <&tegra_car TEGRA20_CLK_PEX>,
566 <&tegra_car TEGRA20_CLK_AFI>,
567 <&tegra_car TEGRA20_CLK_PLL_E>;
568 clock-names = "pex", "afi", "pll_e";
569 resets = <&tegra_car 70>,
572 reset-names = "pex", "afi", "pcie_x";
577 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
578 reg = <0x000800 0 0 0 0>;
581 #address-cells = <3>;
585 nvidia,num-lanes = <2>;
590 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
591 reg = <0x001000 0 0 0 0>;
594 #address-cells = <3>;
598 nvidia,num-lanes = <2>;
603 compatible = "nvidia,tegra20-ehci", "usb-ehci";
604 reg = <0xc5000000 0x4000>;
605 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
607 nvidia,has-legacy-mode;
608 clocks = <&tegra_car TEGRA20_CLK_USBD>;
609 resets = <&tegra_car 22>;
611 nvidia,needs-double-reset;
612 nvidia,phy = <&phy1>;
616 phy1: usb-phy@c5000000 {
617 compatible = "nvidia,tegra20-usb-phy";
618 reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
620 clocks = <&tegra_car TEGRA20_CLK_USBD>,
621 <&tegra_car TEGRA20_CLK_PLL_U>,
622 <&tegra_car TEGRA20_CLK_CLK_M>,
623 <&tegra_car TEGRA20_CLK_USBD>;
624 clock-names = "reg", "pll_u", "timer", "utmi-pads";
625 nvidia,has-legacy-mode;
626 nvidia,hssync-start-delay = <9>;
627 nvidia,idle-wait-delay = <17>;
628 nvidia,elastic-limit = <16>;
629 nvidia,term-range-adj = <6>;
630 nvidia,xcvr-setup = <9>;
631 nvidia,xcvr-lsfslew = <1>;
632 nvidia,xcvr-lsrslew = <1>;
637 compatible = "nvidia,tegra20-ehci", "usb-ehci";
638 reg = <0xc5004000 0x4000>;
639 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
641 clocks = <&tegra_car TEGRA20_CLK_USB2>;
642 resets = <&tegra_car 58>;
644 nvidia,phy = <&phy2>;
648 phy2: usb-phy@c5004000 {
649 compatible = "nvidia,tegra20-usb-phy";
650 reg = <0xc5004000 0x4000>;
652 clocks = <&tegra_car TEGRA20_CLK_USB2>,
653 <&tegra_car TEGRA20_CLK_PLL_U>,
654 <&tegra_car TEGRA20_CLK_CDEV2>;
655 clock-names = "reg", "pll_u", "ulpi-link";
660 compatible = "nvidia,tegra20-ehci", "usb-ehci";
661 reg = <0xc5008000 0x4000>;
662 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
664 clocks = <&tegra_car TEGRA20_CLK_USB3>;
665 resets = <&tegra_car 59>;
667 nvidia,phy = <&phy3>;
671 phy3: usb-phy@c5008000 {
672 compatible = "nvidia,tegra20-usb-phy";
673 reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
675 clocks = <&tegra_car TEGRA20_CLK_USB3>,
676 <&tegra_car TEGRA20_CLK_PLL_U>,
677 <&tegra_car TEGRA20_CLK_CLK_M>,
678 <&tegra_car TEGRA20_CLK_USBD>;
679 clock-names = "reg", "pll_u", "timer", "utmi-pads";
680 nvidia,hssync-start-delay = <9>;
681 nvidia,idle-wait-delay = <17>;
682 nvidia,elastic-limit = <16>;
683 nvidia,term-range-adj = <6>;
684 nvidia,xcvr-setup = <9>;
685 nvidia,xcvr-lsfslew = <2>;
686 nvidia,xcvr-lsrslew = <2>;
691 compatible = "nvidia,tegra20-sdhci";
692 reg = <0xc8000000 0x200>;
693 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
694 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
695 resets = <&tegra_car 14>;
696 reset-names = "sdhci";
701 compatible = "nvidia,tegra20-sdhci";
702 reg = <0xc8000200 0x200>;
703 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
704 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
705 resets = <&tegra_car 9>;
706 reset-names = "sdhci";
711 compatible = "nvidia,tegra20-sdhci";
712 reg = <0xc8000400 0x200>;
713 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
714 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
715 resets = <&tegra_car 69>;
716 reset-names = "sdhci";
721 compatible = "nvidia,tegra20-sdhci";
722 reg = <0xc8000600 0x200>;
723 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
724 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
725 resets = <&tegra_car 15>;
726 reset-names = "sdhci";
731 #address-cells = <1>;
736 compatible = "arm,cortex-a9";
742 compatible = "arm,cortex-a9";
748 compatible = "arm,cortex-a9-pmu";
749 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;