1 /include/ "skeleton.dtsi"
4 compatible = "nvidia,tegra20";
5 interrupt-parent = <&intc>;
16 compatible = "nvidia,tegra20-host1x", "simple-bus";
17 reg = <0x50000000 0x00024000>;
18 interrupts = <0 65 0x04 /* mpcore syncpt */
19 0 67 0x04>; /* mpcore general */
20 clocks = <&tegra_car 28>;
25 ranges = <0x54000000 0x54000000 0x04000000>;
28 compatible = "nvidia,tegra20-mpe";
29 reg = <0x54040000 0x00040000>;
30 interrupts = <0 68 0x04>;
31 clocks = <&tegra_car 60>;
35 compatible = "nvidia,tegra20-vi";
36 reg = <0x54080000 0x00040000>;
37 interrupts = <0 69 0x04>;
38 clocks = <&tegra_car 100>;
42 compatible = "nvidia,tegra20-epp";
43 reg = <0x540c0000 0x00040000>;
44 interrupts = <0 70 0x04>;
45 clocks = <&tegra_car 19>;
49 compatible = "nvidia,tegra20-isp";
50 reg = <0x54100000 0x00040000>;
51 interrupts = <0 71 0x04>;
52 clocks = <&tegra_car 23>;
56 compatible = "nvidia,tegra20-gr2d";
57 reg = <0x54140000 0x00040000>;
58 interrupts = <0 72 0x04>;
59 clocks = <&tegra_car 21>;
63 compatible = "nvidia,tegra20-gr3d";
64 reg = <0x54180000 0x00040000>;
65 clocks = <&tegra_car 24>;
69 compatible = "nvidia,tegra20-dc";
70 reg = <0x54200000 0x00040000>;
71 interrupts = <0 73 0x04>;
72 clocks = <&tegra_car 27>, <&tegra_car 121>;
73 clock-names = "disp1", "parent";
81 compatible = "nvidia,tegra20-dc";
82 reg = <0x54240000 0x00040000>;
83 interrupts = <0 74 0x04>;
84 clocks = <&tegra_car 26>, <&tegra_car 121>;
85 clock-names = "disp2", "parent";
93 compatible = "nvidia,tegra20-hdmi";
94 reg = <0x54280000 0x00040000>;
95 interrupts = <0 75 0x04>;
96 clocks = <&tegra_car 51>, <&tegra_car 117>;
97 clock-names = "hdmi", "parent";
102 compatible = "nvidia,tegra20-tvo";
103 reg = <0x542c0000 0x00040000>;
104 interrupts = <0 76 0x04>;
105 clocks = <&tegra_car 102>;
110 compatible = "nvidia,tegra20-dsi";
111 reg = <0x54300000 0x00040000>;
112 clocks = <&tegra_car 48>;
118 compatible = "arm,cortex-a9-twd-timer";
119 reg = <0x50040600 0x20>;
120 interrupts = <1 13 0x304>;
121 clocks = <&tegra_car 132>;
124 intc: interrupt-controller {
125 compatible = "arm,cortex-a9-gic";
126 reg = <0x50041000 0x1000
128 interrupt-controller;
129 #interrupt-cells = <3>;
133 compatible = "arm,pl310-cache";
134 reg = <0x50043000 0x1000>;
135 arm,data-latency = <5 5 2>;
136 arm,tag-latency = <4 4 2>;
142 compatible = "nvidia,tegra20-timer";
143 reg = <0x60005000 0x60>;
144 interrupts = <0 0 0x04
148 clocks = <&tegra_car 5>;
152 compatible = "nvidia,tegra20-car";
153 reg = <0x60006000 0x1000>;
158 compatible = "nvidia,tegra20-apbdma";
159 reg = <0x6000a000 0x1200>;
160 interrupts = <0 104 0x04
176 clocks = <&tegra_car 34>;
180 compatible = "nvidia,tegra20-ahb";
181 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
185 compatible = "nvidia,tegra20-gpio";
186 reg = <0x6000d000 0x1000>;
187 interrupts = <0 32 0x04
196 #interrupt-cells = <2>;
197 interrupt-controller;
201 compatible = "nvidia,tegra20-pinmux";
202 reg = <0x70000014 0x10 /* Tri-state registers */
203 0x70000080 0x20 /* Mux registers */
204 0x700000a0 0x14 /* Pull-up/down registers */
205 0x70000868 0xa8>; /* Pad control registers */
209 compatible = "nvidia,tegra20-das";
210 reg = <0x70000c00 0x80>;
214 compatible = "nvidia,tegra20-ac97";
215 reg = <0x70002000 0x200>;
216 interrupts = <0 81 0x04>;
217 nvidia,dma-request-selector = <&apbdma 12>;
218 clocks = <&tegra_car 3>;
222 tegra_i2s1: i2s@70002800 {
223 compatible = "nvidia,tegra20-i2s";
224 reg = <0x70002800 0x200>;
225 interrupts = <0 13 0x04>;
226 nvidia,dma-request-selector = <&apbdma 2>;
227 clocks = <&tegra_car 11>;
231 tegra_i2s2: i2s@70002a00 {
232 compatible = "nvidia,tegra20-i2s";
233 reg = <0x70002a00 0x200>;
234 interrupts = <0 3 0x04>;
235 nvidia,dma-request-selector = <&apbdma 1>;
236 clocks = <&tegra_car 18>;
241 * There are two serial driver i.e. 8250 based simple serial
242 * driver and APB DMA based serial driver for higher baudrate
243 * and performace. To enable the 8250 based driver, the compatible
244 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
245 * driver, the comptible is "nvidia,tegra20-hsuart".
247 uarta: serial@70006000 {
248 compatible = "nvidia,tegra20-uart";
249 reg = <0x70006000 0x40>;
251 interrupts = <0 36 0x04>;
252 nvidia,dma-request-selector = <&apbdma 8>;
253 clocks = <&tegra_car 6>;
257 uartb: serial@70006040 {
258 compatible = "nvidia,tegra20-uart";
259 reg = <0x70006040 0x40>;
261 interrupts = <0 37 0x04>;
262 nvidia,dma-request-selector = <&apbdma 9>;
263 clocks = <&tegra_car 96>;
267 uartc: serial@70006200 {
268 compatible = "nvidia,tegra20-uart";
269 reg = <0x70006200 0x100>;
271 interrupts = <0 46 0x04>;
272 nvidia,dma-request-selector = <&apbdma 10>;
273 clocks = <&tegra_car 55>;
277 uartd: serial@70006300 {
278 compatible = "nvidia,tegra20-uart";
279 reg = <0x70006300 0x100>;
281 interrupts = <0 90 0x04>;
282 nvidia,dma-request-selector = <&apbdma 19>;
283 clocks = <&tegra_car 65>;
287 uarte: serial@70006400 {
288 compatible = "nvidia,tegra20-uart";
289 reg = <0x70006400 0x100>;
291 interrupts = <0 91 0x04>;
292 nvidia,dma-request-selector = <&apbdma 20>;
293 clocks = <&tegra_car 66>;
298 compatible = "nvidia,tegra20-pwm";
299 reg = <0x7000a000 0x100>;
301 clocks = <&tegra_car 17>;
305 compatible = "nvidia,tegra20-rtc";
306 reg = <0x7000e000 0x100>;
307 interrupts = <0 2 0x04>;
308 clocks = <&tegra_car 4>;
312 compatible = "nvidia,tegra20-i2c";
313 reg = <0x7000c000 0x100>;
314 interrupts = <0 38 0x04>;
315 #address-cells = <1>;
317 clocks = <&tegra_car 12>, <&tegra_car 124>;
318 clock-names = "div-clk", "fast-clk";
323 compatible = "nvidia,tegra20-sflash";
324 reg = <0x7000c380 0x80>;
325 interrupts = <0 39 0x04>;
326 nvidia,dma-request-selector = <&apbdma 11>;
327 #address-cells = <1>;
329 clocks = <&tegra_car 43>;
334 compatible = "nvidia,tegra20-i2c";
335 reg = <0x7000c400 0x100>;
336 interrupts = <0 84 0x04>;
337 #address-cells = <1>;
339 clocks = <&tegra_car 54>, <&tegra_car 124>;
340 clock-names = "div-clk", "fast-clk";
345 compatible = "nvidia,tegra20-i2c";
346 reg = <0x7000c500 0x100>;
347 interrupts = <0 92 0x04>;
348 #address-cells = <1>;
350 clocks = <&tegra_car 67>, <&tegra_car 124>;
351 clock-names = "div-clk", "fast-clk";
356 compatible = "nvidia,tegra20-i2c-dvc";
357 reg = <0x7000d000 0x200>;
358 interrupts = <0 53 0x04>;
359 #address-cells = <1>;
361 clocks = <&tegra_car 47>, <&tegra_car 124>;
362 clock-names = "div-clk", "fast-clk";
367 compatible = "nvidia,tegra20-slink";
368 reg = <0x7000d400 0x200>;
369 interrupts = <0 59 0x04>;
370 nvidia,dma-request-selector = <&apbdma 15>;
371 #address-cells = <1>;
373 clocks = <&tegra_car 41>;
378 compatible = "nvidia,tegra20-slink";
379 reg = <0x7000d600 0x200>;
380 interrupts = <0 82 0x04>;
381 nvidia,dma-request-selector = <&apbdma 16>;
382 #address-cells = <1>;
384 clocks = <&tegra_car 44>;
389 compatible = "nvidia,tegra20-slink";
390 reg = <0x7000d800 0x200>;
391 interrupts = <0 83 0x04>;
392 nvidia,dma-request-selector = <&apbdma 17>;
393 #address-cells = <1>;
395 clocks = <&tegra_car 46>;
400 compatible = "nvidia,tegra20-slink";
401 reg = <0x7000da00 0x200>;
402 interrupts = <0 93 0x04>;
403 nvidia,dma-request-selector = <&apbdma 18>;
404 #address-cells = <1>;
406 clocks = <&tegra_car 68>;
411 compatible = "nvidia,tegra20-kbc";
412 reg = <0x7000e200 0x100>;
413 interrupts = <0 85 0x04>;
414 clocks = <&tegra_car 36>;
419 compatible = "nvidia,tegra20-pmc";
420 reg = <0x7000e400 0x400>;
421 clocks = <&tegra_car 110>, <&clk32k_in>;
422 clock-names = "pclk", "clk32k_in";
425 memory-controller@7000f000 {
426 compatible = "nvidia,tegra20-mc";
427 reg = <0x7000f000 0x024
429 interrupts = <0 77 0x04>;
433 compatible = "nvidia,tegra20-gart";
434 reg = <0x7000f024 0x00000018 /* controller registers */
435 0x58000000 0x02000000>; /* GART aperture */
438 memory-controller@7000f400 {
439 compatible = "nvidia,tegra20-emc";
440 reg = <0x7000f400 0x200>;
441 #address-cells = <1>;
445 phy1: usb-phy@c5000400 {
446 compatible = "nvidia,tegra20-usb-phy";
447 reg = <0xc5000400 0x3c00>;
449 nvidia,has-legacy-mode;
450 clocks = <&tegra_car 22>, <&tegra_car 127>;
451 clock-names = "phy", "pll_u";
454 phy2: usb-phy@c5004400 {
455 compatible = "nvidia,tegra20-usb-phy";
456 reg = <0xc5004400 0x3c00>;
458 clocks = <&tegra_car 94>, <&tegra_car 127>;
459 clock-names = "phy", "pll_u";
462 phy3: usb-phy@c5008400 {
463 compatible = "nvidia,tegra20-usb-phy";
464 reg = <0xc5008400 0x3C00>;
466 clocks = <&tegra_car 22>, <&tegra_car 127>;
467 clock-names = "phy", "pll_u";
471 compatible = "nvidia,tegra20-ehci", "usb-ehci";
472 reg = <0xc5000000 0x4000>;
473 interrupts = <0 20 0x04>;
475 nvidia,has-legacy-mode;
476 clocks = <&tegra_car 22>;
477 nvidia,needs-double-reset;
478 nvidia,phy = <&phy1>;
483 compatible = "nvidia,tegra20-ehci", "usb-ehci";
484 reg = <0xc5004000 0x4000>;
485 interrupts = <0 21 0x04>;
487 clocks = <&tegra_car 58>;
488 nvidia,phy = <&phy2>;
493 compatible = "nvidia,tegra20-ehci", "usb-ehci";
494 reg = <0xc5008000 0x4000>;
495 interrupts = <0 97 0x04>;
497 clocks = <&tegra_car 59>;
498 nvidia,phy = <&phy3>;
503 compatible = "nvidia,tegra20-sdhci";
504 reg = <0xc8000000 0x200>;
505 interrupts = <0 14 0x04>;
506 clocks = <&tegra_car 14>;
511 compatible = "nvidia,tegra20-sdhci";
512 reg = <0xc8000200 0x200>;
513 interrupts = <0 15 0x04>;
514 clocks = <&tegra_car 9>;
519 compatible = "nvidia,tegra20-sdhci";
520 reg = <0xc8000400 0x200>;
521 interrupts = <0 19 0x04>;
522 clocks = <&tegra_car 69>;
527 compatible = "nvidia,tegra20-sdhci";
528 reg = <0xc8000600 0x200>;
529 interrupts = <0 31 0x04>;
530 clocks = <&tegra_car 15>;
535 #address-cells = <1>;
540 compatible = "arm,cortex-a9";
546 compatible = "arm,cortex-a9";
552 compatible = "arm,cortex-a9-pmu";
553 interrupts = <0 56 0x04