1 #include <dt-bindings/clock/tegra20-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include "skeleton.dtsi"
9 compatible = "nvidia,tegra20";
10 interrupt-parent = <&lic>;
13 compatible = "nvidia,tegra20-host1x", "simple-bus";
14 reg = <0x50000000 0x00024000>;
15 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
16 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
17 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
18 resets = <&tegra_car 28>;
19 reset-names = "host1x";
24 ranges = <0x54000000 0x54000000 0x04000000>;
27 compatible = "nvidia,tegra20-mpe";
28 reg = <0x54040000 0x00040000>;
29 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
30 clocks = <&tegra_car TEGRA20_CLK_MPE>;
31 resets = <&tegra_car 60>;
36 compatible = "nvidia,tegra20-vi";
37 reg = <0x54080000 0x00040000>;
38 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
39 clocks = <&tegra_car TEGRA20_CLK_VI>;
40 resets = <&tegra_car 20>;
45 compatible = "nvidia,tegra20-epp";
46 reg = <0x540c0000 0x00040000>;
47 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
48 clocks = <&tegra_car TEGRA20_CLK_EPP>;
49 resets = <&tegra_car 19>;
54 compatible = "nvidia,tegra20-isp";
55 reg = <0x54100000 0x00040000>;
56 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
57 clocks = <&tegra_car TEGRA20_CLK_ISP>;
58 resets = <&tegra_car 23>;
63 compatible = "nvidia,tegra20-gr2d";
64 reg = <0x54140000 0x00040000>;
65 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
66 clocks = <&tegra_car TEGRA20_CLK_GR2D>;
67 resets = <&tegra_car 21>;
72 compatible = "nvidia,tegra20-gr3d";
73 reg = <0x54180000 0x00040000>;
74 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
75 resets = <&tegra_car 24>;
80 compatible = "nvidia,tegra20-dc";
81 reg = <0x54200000 0x00040000>;
82 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
83 clocks = <&tegra_car TEGRA20_CLK_DISP1>,
84 <&tegra_car TEGRA20_CLK_PLL_P>;
85 clock-names = "dc", "parent";
86 resets = <&tegra_car 27>;
97 compatible = "nvidia,tegra20-dc";
98 reg = <0x54240000 0x00040000>;
99 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
100 clocks = <&tegra_car TEGRA20_CLK_DISP2>,
101 <&tegra_car TEGRA20_CLK_PLL_P>;
102 clock-names = "dc", "parent";
103 resets = <&tegra_car 26>;
114 compatible = "nvidia,tegra20-hdmi";
115 reg = <0x54280000 0x00040000>;
116 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
117 clocks = <&tegra_car TEGRA20_CLK_HDMI>,
118 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
119 clock-names = "hdmi", "parent";
120 resets = <&tegra_car 51>;
121 reset-names = "hdmi";
126 compatible = "nvidia,tegra20-tvo";
127 reg = <0x542c0000 0x00040000>;
128 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
129 clocks = <&tegra_car TEGRA20_CLK_TVO>;
134 compatible = "nvidia,tegra20-dsi";
135 reg = <0x54300000 0x00040000>;
136 clocks = <&tegra_car TEGRA20_CLK_DSI>;
137 resets = <&tegra_car 48>;
144 compatible = "arm,cortex-a9-twd-timer";
145 interrupt-parent = <&intc>;
146 reg = <0x50040600 0x20>;
147 interrupts = <GIC_PPI 13
148 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
149 clocks = <&tegra_car TEGRA20_CLK_TWD>;
152 intc: interrupt-controller@50041000 {
153 compatible = "arm,cortex-a9-gic";
154 reg = <0x50041000 0x1000
156 interrupt-controller;
157 #interrupt-cells = <3>;
158 interrupt-parent = <&intc>;
161 cache-controller@50043000 {
162 compatible = "arm,pl310-cache";
163 reg = <0x50043000 0x1000>;
164 arm,data-latency = <5 5 2>;
165 arm,tag-latency = <4 4 2>;
170 lic: interrupt-controller@60004000 {
171 compatible = "nvidia,tegra20-ictlr";
172 reg = <0x60004000 0x100>,
176 interrupt-controller;
177 #interrupt-cells = <3>;
178 interrupt-parent = <&intc>;
182 compatible = "nvidia,tegra20-timer";
183 reg = <0x60005000 0x60>;
184 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
188 clocks = <&tegra_car TEGRA20_CLK_TIMER>;
191 tegra_car: clock@60006000 {
192 compatible = "nvidia,tegra20-car";
193 reg = <0x60006000 0x1000>;
198 flow-controller@60007000 {
199 compatible = "nvidia,tegra20-flowctrl";
200 reg = <0x60007000 0x1000>;
203 apbdma: dma@6000a000 {
204 compatible = "nvidia,tegra20-apbdma";
205 reg = <0x6000a000 0x1200>;
206 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
223 resets = <&tegra_car 34>;
229 compatible = "nvidia,tegra20-ahb";
230 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
233 gpio: gpio@6000d000 {
234 compatible = "nvidia,tegra20-gpio";
235 reg = <0x6000d000 0x1000>;
236 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
242 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
245 #interrupt-cells = <2>;
246 interrupt-controller;
250 compatible = "nvidia,tegra20-apbmisc";
251 reg = <0x70000800 0x64 /* Chip revision */
252 0x70000008 0x04>; /* Strapping options */
255 pinmux: pinmux@70000014 {
256 compatible = "nvidia,tegra20-pinmux";
257 reg = <0x70000014 0x10 /* Tri-state registers */
258 0x70000080 0x20 /* Mux registers */
259 0x700000a0 0x14 /* Pull-up/down registers */
260 0x70000868 0xa8>; /* Pad control registers */
264 compatible = "nvidia,tegra20-das";
265 reg = <0x70000c00 0x80>;
268 tegra_ac97: ac97@70002000 {
269 compatible = "nvidia,tegra20-ac97";
270 reg = <0x70002000 0x200>;
271 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
272 clocks = <&tegra_car TEGRA20_CLK_AC97>;
273 resets = <&tegra_car 3>;
274 reset-names = "ac97";
275 dmas = <&apbdma 12>, <&apbdma 12>;
276 dma-names = "rx", "tx";
280 tegra_i2s1: i2s@70002800 {
281 compatible = "nvidia,tegra20-i2s";
282 reg = <0x70002800 0x200>;
283 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
284 clocks = <&tegra_car TEGRA20_CLK_I2S1>;
285 resets = <&tegra_car 11>;
287 dmas = <&apbdma 2>, <&apbdma 2>;
288 dma-names = "rx", "tx";
292 tegra_i2s2: i2s@70002a00 {
293 compatible = "nvidia,tegra20-i2s";
294 reg = <0x70002a00 0x200>;
295 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
296 clocks = <&tegra_car TEGRA20_CLK_I2S2>;
297 resets = <&tegra_car 18>;
299 dmas = <&apbdma 1>, <&apbdma 1>;
300 dma-names = "rx", "tx";
305 * There are two serial driver i.e. 8250 based simple serial
306 * driver and APB DMA based serial driver for higher baudrate
307 * and performace. To enable the 8250 based driver, the compatible
308 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
309 * driver, the comptible is "nvidia,tegra20-hsuart".
311 uarta: serial@70006000 {
312 compatible = "nvidia,tegra20-uart";
313 reg = <0x70006000 0x40>;
315 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&tegra_car TEGRA20_CLK_UARTA>;
317 resets = <&tegra_car 6>;
318 reset-names = "serial";
319 dmas = <&apbdma 8>, <&apbdma 8>;
320 dma-names = "rx", "tx";
324 uartb: serial@70006040 {
325 compatible = "nvidia,tegra20-uart";
326 reg = <0x70006040 0x40>;
328 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&tegra_car TEGRA20_CLK_UARTB>;
330 resets = <&tegra_car 7>;
331 reset-names = "serial";
332 dmas = <&apbdma 9>, <&apbdma 9>;
333 dma-names = "rx", "tx";
337 uartc: serial@70006200 {
338 compatible = "nvidia,tegra20-uart";
339 reg = <0x70006200 0x100>;
341 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&tegra_car TEGRA20_CLK_UARTC>;
343 resets = <&tegra_car 55>;
344 reset-names = "serial";
345 dmas = <&apbdma 10>, <&apbdma 10>;
346 dma-names = "rx", "tx";
350 uartd: serial@70006300 {
351 compatible = "nvidia,tegra20-uart";
352 reg = <0x70006300 0x100>;
354 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&tegra_car TEGRA20_CLK_UARTD>;
356 resets = <&tegra_car 65>;
357 reset-names = "serial";
358 dmas = <&apbdma 19>, <&apbdma 19>;
359 dma-names = "rx", "tx";
363 uarte: serial@70006400 {
364 compatible = "nvidia,tegra20-uart";
365 reg = <0x70006400 0x100>;
367 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&tegra_car TEGRA20_CLK_UARTE>;
369 resets = <&tegra_car 66>;
370 reset-names = "serial";
371 dmas = <&apbdma 20>, <&apbdma 20>;
372 dma-names = "rx", "tx";
377 compatible = "nvidia,tegra20-pwm";
378 reg = <0x7000a000 0x100>;
380 clocks = <&tegra_car TEGRA20_CLK_PWM>;
381 resets = <&tegra_car 17>;
387 compatible = "nvidia,tegra20-rtc";
388 reg = <0x7000e000 0x100>;
389 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&tegra_car TEGRA20_CLK_RTC>;
394 compatible = "nvidia,tegra20-i2c";
395 reg = <0x7000c000 0x100>;
396 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
397 #address-cells = <1>;
399 clocks = <&tegra_car TEGRA20_CLK_I2C1>,
400 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
401 clock-names = "div-clk", "fast-clk";
402 resets = <&tegra_car 12>;
404 dmas = <&apbdma 21>, <&apbdma 21>;
405 dma-names = "rx", "tx";
410 compatible = "nvidia,tegra20-sflash";
411 reg = <0x7000c380 0x80>;
412 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
413 #address-cells = <1>;
415 clocks = <&tegra_car TEGRA20_CLK_SPI>;
416 resets = <&tegra_car 43>;
418 dmas = <&apbdma 11>, <&apbdma 11>;
419 dma-names = "rx", "tx";
424 compatible = "nvidia,tegra20-i2c";
425 reg = <0x7000c400 0x100>;
426 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
427 #address-cells = <1>;
429 clocks = <&tegra_car TEGRA20_CLK_I2C2>,
430 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
431 clock-names = "div-clk", "fast-clk";
432 resets = <&tegra_car 54>;
434 dmas = <&apbdma 22>, <&apbdma 22>;
435 dma-names = "rx", "tx";
440 compatible = "nvidia,tegra20-i2c";
441 reg = <0x7000c500 0x100>;
442 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
443 #address-cells = <1>;
445 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
446 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
447 clock-names = "div-clk", "fast-clk";
448 resets = <&tegra_car 67>;
450 dmas = <&apbdma 23>, <&apbdma 23>;
451 dma-names = "rx", "tx";
456 compatible = "nvidia,tegra20-i2c-dvc";
457 reg = <0x7000d000 0x200>;
458 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
459 #address-cells = <1>;
461 clocks = <&tegra_car TEGRA20_CLK_DVC>,
462 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
463 clock-names = "div-clk", "fast-clk";
464 resets = <&tegra_car 47>;
466 dmas = <&apbdma 24>, <&apbdma 24>;
467 dma-names = "rx", "tx";
472 compatible = "nvidia,tegra20-slink";
473 reg = <0x7000d400 0x200>;
474 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
475 #address-cells = <1>;
477 clocks = <&tegra_car TEGRA20_CLK_SBC1>;
478 resets = <&tegra_car 41>;
480 dmas = <&apbdma 15>, <&apbdma 15>;
481 dma-names = "rx", "tx";
486 compatible = "nvidia,tegra20-slink";
487 reg = <0x7000d600 0x200>;
488 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
489 #address-cells = <1>;
491 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
492 resets = <&tegra_car 44>;
494 dmas = <&apbdma 16>, <&apbdma 16>;
495 dma-names = "rx", "tx";
500 compatible = "nvidia,tegra20-slink";
501 reg = <0x7000d800 0x200>;
502 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
503 #address-cells = <1>;
505 clocks = <&tegra_car TEGRA20_CLK_SBC3>;
506 resets = <&tegra_car 46>;
508 dmas = <&apbdma 17>, <&apbdma 17>;
509 dma-names = "rx", "tx";
514 compatible = "nvidia,tegra20-slink";
515 reg = <0x7000da00 0x200>;
516 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
517 #address-cells = <1>;
519 clocks = <&tegra_car TEGRA20_CLK_SBC4>;
520 resets = <&tegra_car 68>;
522 dmas = <&apbdma 18>, <&apbdma 18>;
523 dma-names = "rx", "tx";
528 compatible = "nvidia,tegra20-kbc";
529 reg = <0x7000e200 0x100>;
530 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&tegra_car TEGRA20_CLK_KBC>;
532 resets = <&tegra_car 36>;
538 compatible = "nvidia,tegra20-pmc";
539 reg = <0x7000e400 0x400>;
540 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
541 clock-names = "pclk", "clk32k_in";
544 memory-controller@7000f000 {
545 compatible = "nvidia,tegra20-mc";
546 reg = <0x7000f000 0x024
548 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
552 compatible = "nvidia,tegra20-gart";
553 reg = <0x7000f024 0x00000018 /* controller registers */
554 0x58000000 0x02000000>; /* GART aperture */
557 memory-controller@7000f400 {
558 compatible = "nvidia,tegra20-emc";
559 reg = <0x7000f400 0x200>;
560 #address-cells = <1>;
565 compatible = "nvidia,tegra20-efuse";
566 reg = <0x7000f800 0x400>;
567 clocks = <&tegra_car TEGRA20_CLK_FUSE>;
568 clock-names = "fuse";
569 resets = <&tegra_car 39>;
570 reset-names = "fuse";
573 pcie-controller@80003000 {
574 compatible = "nvidia,tegra20-pcie";
576 reg = <0x80003000 0x00000800 /* PADS registers */
577 0x80003800 0x00000200 /* AFI registers */
578 0x90000000 0x10000000>; /* configuration space */
579 reg-names = "pads", "afi", "cs";
580 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
581 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
582 interrupt-names = "intr", "msi";
584 #interrupt-cells = <1>;
585 interrupt-map-mask = <0 0 0 0>;
586 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
588 bus-range = <0x00 0xff>;
589 #address-cells = <3>;
592 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
593 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
594 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
595 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */
596 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
598 clocks = <&tegra_car TEGRA20_CLK_PEX>,
599 <&tegra_car TEGRA20_CLK_AFI>,
600 <&tegra_car TEGRA20_CLK_PLL_E>;
601 clock-names = "pex", "afi", "pll_e";
602 resets = <&tegra_car 70>,
605 reset-names = "pex", "afi", "pcie_x";
610 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
611 reg = <0x000800 0 0 0 0>;
614 #address-cells = <3>;
618 nvidia,num-lanes = <2>;
623 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
624 reg = <0x001000 0 0 0 0>;
627 #address-cells = <3>;
631 nvidia,num-lanes = <2>;
636 compatible = "nvidia,tegra20-ehci", "usb-ehci";
637 reg = <0xc5000000 0x4000>;
638 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
640 nvidia,has-legacy-mode;
641 clocks = <&tegra_car TEGRA20_CLK_USBD>;
642 resets = <&tegra_car 22>;
644 nvidia,needs-double-reset;
645 nvidia,phy = <&phy1>;
649 phy1: usb-phy@c5000000 {
650 compatible = "nvidia,tegra20-usb-phy";
651 reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
653 clocks = <&tegra_car TEGRA20_CLK_USBD>,
654 <&tegra_car TEGRA20_CLK_PLL_U>,
655 <&tegra_car TEGRA20_CLK_CLK_M>,
656 <&tegra_car TEGRA20_CLK_USBD>;
657 clock-names = "reg", "pll_u", "timer", "utmi-pads";
658 resets = <&tegra_car 22>, <&tegra_car 22>;
659 reset-names = "usb", "utmi-pads";
660 nvidia,has-legacy-mode;
661 nvidia,hssync-start-delay = <9>;
662 nvidia,idle-wait-delay = <17>;
663 nvidia,elastic-limit = <16>;
664 nvidia,term-range-adj = <6>;
665 nvidia,xcvr-setup = <9>;
666 nvidia,xcvr-lsfslew = <1>;
667 nvidia,xcvr-lsrslew = <1>;
668 nvidia,has-utmi-pad-registers;
673 compatible = "nvidia,tegra20-ehci", "usb-ehci";
674 reg = <0xc5004000 0x4000>;
675 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
677 clocks = <&tegra_car TEGRA20_CLK_USB2>;
678 resets = <&tegra_car 58>;
680 nvidia,phy = <&phy2>;
684 phy2: usb-phy@c5004000 {
685 compatible = "nvidia,tegra20-usb-phy";
686 reg = <0xc5004000 0x4000>;
688 clocks = <&tegra_car TEGRA20_CLK_USB2>,
689 <&tegra_car TEGRA20_CLK_PLL_U>,
690 <&tegra_car TEGRA20_CLK_CDEV2>;
691 clock-names = "reg", "pll_u", "ulpi-link";
692 resets = <&tegra_car 58>, <&tegra_car 22>;
693 reset-names = "usb", "utmi-pads";
698 compatible = "nvidia,tegra20-ehci", "usb-ehci";
699 reg = <0xc5008000 0x4000>;
700 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
702 clocks = <&tegra_car TEGRA20_CLK_USB3>;
703 resets = <&tegra_car 59>;
705 nvidia,phy = <&phy3>;
709 phy3: usb-phy@c5008000 {
710 compatible = "nvidia,tegra20-usb-phy";
711 reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
713 clocks = <&tegra_car TEGRA20_CLK_USB3>,
714 <&tegra_car TEGRA20_CLK_PLL_U>,
715 <&tegra_car TEGRA20_CLK_CLK_M>,
716 <&tegra_car TEGRA20_CLK_USBD>;
717 clock-names = "reg", "pll_u", "timer", "utmi-pads";
718 resets = <&tegra_car 59>, <&tegra_car 22>;
719 reset-names = "usb", "utmi-pads";
720 nvidia,hssync-start-delay = <9>;
721 nvidia,idle-wait-delay = <17>;
722 nvidia,elastic-limit = <16>;
723 nvidia,term-range-adj = <6>;
724 nvidia,xcvr-setup = <9>;
725 nvidia,xcvr-lsfslew = <2>;
726 nvidia,xcvr-lsrslew = <2>;
731 compatible = "nvidia,tegra20-sdhci";
732 reg = <0xc8000000 0x200>;
733 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
734 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
735 resets = <&tegra_car 14>;
736 reset-names = "sdhci";
741 compatible = "nvidia,tegra20-sdhci";
742 reg = <0xc8000200 0x200>;
743 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
745 resets = <&tegra_car 9>;
746 reset-names = "sdhci";
751 compatible = "nvidia,tegra20-sdhci";
752 reg = <0xc8000400 0x200>;
753 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
754 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
755 resets = <&tegra_car 69>;
756 reset-names = "sdhci";
761 compatible = "nvidia,tegra20-sdhci";
762 reg = <0xc8000600 0x200>;
763 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
764 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
765 resets = <&tegra_car 15>;
766 reset-names = "sdhci";
771 #address-cells = <1>;
776 compatible = "arm,cortex-a9";
782 compatible = "arm,cortex-a9";
788 compatible = "arm,cortex-a9-pmu";
789 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
790 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;