1 #include "tegra30.dtsi"
4 * This file contains common DT entry for all fab version of Cardhu.
5 * There is multiple fab version of Cardhu starting from A01 to A07.
6 * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
7 * A02 will have different sets of GPIOs for fixed regulator compare to
8 * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
9 * compatible with fab version A04. Based on Cardhu fab version, the
10 * related dts file need to be chosen like for Cardhu fab version A02,
11 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
12 * tegra30-cardhu-a04.dts.
13 * The identification of board is done in two ways, by looking the sticker
14 * on PCB and by reading board id eeprom.
15 * The stciker will have number like 600-81291-1000-002 C.3. In this 4th
16 * number is the fab version like here it is 002 and hence fab version A02.
17 * The (downstream internal) U-Boot of Cardhu display the board-id as
19 * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
20 * In this Fab version is 02 i.e. A02.
21 * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
22 * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
27 model = "NVIDIA Tegra30 Cardhu evaluation board";
28 compatible = "nvidia,cardhu", "nvidia,tegra30";
31 reg = <0x80000000 0x40000000>;
36 pex-clk-supply = <&pex_hvdd_3v3_reg>;
37 vdd-supply = <&ldo1_reg>;
38 avdd-supply = <&ldo2_reg>;
41 nvidia,num-lanes = <4>;
45 nvidia,num-lanes = <1>;
50 nvidia,num-lanes = <1>;
55 pinctrl-names = "default";
56 pinctrl-0 = <&state_default>;
58 state_default: pinmux {
60 nvidia,pins = "sdmmc1_clk_pz0";
61 nvidia,function = "sdmmc1";
63 nvidia,tristate = <0>;
66 nvidia,pins = "sdmmc1_cmd_pz1",
71 nvidia,function = "sdmmc1";
73 nvidia,tristate = <0>;
76 nvidia,pins = "sdmmc3_clk_pa6";
77 nvidia,function = "sdmmc3";
79 nvidia,tristate = <0>;
82 nvidia,pins = "sdmmc3_cmd_pa7",
87 nvidia,function = "sdmmc3";
89 nvidia,tristate = <0>;
92 nvidia,pins = "sdmmc4_clk_pcc4",
94 nvidia,function = "sdmmc4";
96 nvidia,tristate = <0>;
99 nvidia,pins = "sdmmc4_dat0_paa0",
107 nvidia,function = "sdmmc4";
109 nvidia,tristate = <0>;
112 nvidia,pins = "dap2_fs_pa2",
116 nvidia,function = "i2s1";
118 nvidia,tristate = <0>;
121 nvidia,pins = "drive_sdio3";
122 nvidia,high-speed-mode = <0>;
123 nvidia,schmitt = <0>;
124 nvidia,pull-down-strength = <46>;
125 nvidia,pull-up-strength = <42>;
126 nvidia,slew-rate-rising = <1>;
127 nvidia,slew-rate-falling = <1>;
130 nvidia,pins = "uart3_txd_pw6",
134 nvidia,function = "uartc";
136 nvidia,tristate = <0>;
146 compatible = "nvidia,tegra30-hsuart";
152 clock-frequency = <100000>;
157 clock-frequency = <100000>;
162 clock-frequency = <100000>;
164 /* ALS and Proximity sensor */
166 compatible = "isil,isl29028";
168 interrupt-parent = <&gpio>;
169 interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
175 clock-frequency = <100000>;
180 clock-frequency = <100000>;
183 compatible = "wlf,wm8903";
185 interrupt-parent = <&gpio>;
186 interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
192 micdet-delay = <100>;
193 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
197 compatible = "ti,tps65911";
200 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
201 #interrupt-cells = <2>;
202 interrupt-controller;
204 ti,system-power-controller;
209 vcc1-supply = <&vdd_ac_bat_reg>;
210 vcc2-supply = <&vdd_ac_bat_reg>;
211 vcc3-supply = <&vio_reg>;
212 vcc4-supply = <&vdd_5v0_reg>;
213 vcc5-supply = <&vdd_ac_bat_reg>;
214 vcc6-supply = <&vdd2_reg>;
215 vcc7-supply = <&vdd_ac_bat_reg>;
216 vccio-supply = <&vdd_ac_bat_reg>;
220 regulator-name = "vddio_ddr_1v2";
221 regulator-min-microvolt = <1200000>;
222 regulator-max-microvolt = <1200000>;
227 regulator-name = "vdd_1v5_gen";
228 regulator-min-microvolt = <1500000>;
229 regulator-max-microvolt = <1500000>;
233 vddctrl_reg: vddctrl {
234 regulator-name = "vdd_cpu,vdd_sys";
235 regulator-min-microvolt = <1000000>;
236 regulator-max-microvolt = <1000000>;
241 regulator-name = "vdd_1v8_gen";
242 regulator-min-microvolt = <1800000>;
243 regulator-max-microvolt = <1800000>;
248 regulator-name = "vdd_pexa,vdd_pexb";
249 regulator-min-microvolt = <1050000>;
250 regulator-max-microvolt = <1050000>;
254 regulator-name = "vdd_sata,avdd_plle";
255 regulator-min-microvolt = <1050000>;
256 regulator-max-microvolt = <1050000>;
259 /* LDO3 is not connected to anything */
262 regulator-name = "vdd_rtc";
263 regulator-min-microvolt = <1200000>;
264 regulator-max-microvolt = <1200000>;
269 regulator-name = "vddio_sdmmc,avdd_vdac";
270 regulator-min-microvolt = <3300000>;
271 regulator-max-microvolt = <3300000>;
276 regulator-name = "avdd_dsi_csi,pwrdet_mipi";
277 regulator-min-microvolt = <1200000>;
278 regulator-max-microvolt = <1200000>;
282 regulator-name = "vdd_pllm,x,u,a_p_c_s";
283 regulator-min-microvolt = <1200000>;
284 regulator-max-microvolt = <1200000>;
289 regulator-name = "vdd_ddr_hs";
290 regulator-min-microvolt = <1000000>;
291 regulator-max-microvolt = <1000000>;
297 temperature-sensor@4c {
298 compatible = "onnn,nct1008";
300 vcc-supply = <&sys_3v3_reg>;
301 interrupt-parent = <&gpio>;
302 interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
306 compatible = "ti,tps62361";
309 regulator-name = "tps62361-vout";
310 regulator-min-microvolt = <500000>;
311 regulator-max-microvolt = <1500000>;
321 spi-max-frequency = <25000000>;
323 compatible = "winbond,w25q32";
325 spi-max-frequency = <20000000>;
337 nvidia,invert-interrupt;
338 nvidia,suspend-mode = <1>;
339 nvidia,cpu-pwr-good-time = <2000>;
340 nvidia,cpu-pwr-off-time = <200>;
341 nvidia,core-pwr-good-time = <3845 3845>;
342 nvidia,core-pwr-off-time = <0>;
343 nvidia,core-power-req-active-high;
344 nvidia,sys-clock-req-active-high;
349 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
350 wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
351 power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
366 vbus-supply = <&usb3_vbus_reg>;
371 compatible = "simple-bus";
372 #address-cells = <1>;
376 compatible = "fixed-clock";
379 clock-frequency = <32768>;
384 compatible = "simple-bus";
385 #address-cells = <1>;
388 vdd_ac_bat_reg: regulator@0 {
389 compatible = "regulator-fixed";
391 regulator-name = "vdd_ac_bat";
392 regulator-min-microvolt = <5000000>;
393 regulator-max-microvolt = <5000000>;
397 cam_1v8_reg: regulator@1 {
398 compatible = "regulator-fixed";
400 regulator-name = "cam_1v8";
401 regulator-min-microvolt = <1800000>;
402 regulator-max-microvolt = <1800000>;
404 gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
405 vin-supply = <&vio_reg>;
408 cp_5v_reg: regulator@2 {
409 compatible = "regulator-fixed";
411 regulator-name = "cp_5v";
412 regulator-min-microvolt = <5000000>;
413 regulator-max-microvolt = <5000000>;
417 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
420 emmc_3v3_reg: regulator@3 {
421 compatible = "regulator-fixed";
423 regulator-name = "emmc_3v3";
424 regulator-min-microvolt = <3300000>;
425 regulator-max-microvolt = <3300000>;
429 gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
430 vin-supply = <&sys_3v3_reg>;
433 modem_3v3_reg: regulator@4 {
434 compatible = "regulator-fixed";
436 regulator-name = "modem_3v3";
437 regulator-min-microvolt = <3300000>;
438 regulator-max-microvolt = <3300000>;
440 gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
443 pex_hvdd_3v3_reg: regulator@5 {
444 compatible = "regulator-fixed";
446 regulator-name = "pex_hvdd_3v3";
447 regulator-min-microvolt = <3300000>;
448 regulator-max-microvolt = <3300000>;
450 gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
451 vin-supply = <&sys_3v3_reg>;
454 vdd_cam1_ldo_reg: regulator@6 {
455 compatible = "regulator-fixed";
457 regulator-name = "vdd_cam1_ldo";
458 regulator-min-microvolt = <2800000>;
459 regulator-max-microvolt = <2800000>;
461 gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
462 vin-supply = <&sys_3v3_reg>;
465 vdd_cam2_ldo_reg: regulator@7 {
466 compatible = "regulator-fixed";
468 regulator-name = "vdd_cam2_ldo";
469 regulator-min-microvolt = <2800000>;
470 regulator-max-microvolt = <2800000>;
472 gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
473 vin-supply = <&sys_3v3_reg>;
476 vdd_cam3_ldo_reg: regulator@8 {
477 compatible = "regulator-fixed";
479 regulator-name = "vdd_cam3_ldo";
480 regulator-min-microvolt = <3300000>;
481 regulator-max-microvolt = <3300000>;
483 gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
484 vin-supply = <&sys_3v3_reg>;
487 vdd_com_reg: regulator@9 {
488 compatible = "regulator-fixed";
490 regulator-name = "vdd_com";
491 regulator-min-microvolt = <3300000>;
492 regulator-max-microvolt = <3300000>;
496 gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
497 vin-supply = <&sys_3v3_reg>;
500 vdd_fuse_3v3_reg: regulator@10 {
501 compatible = "regulator-fixed";
503 regulator-name = "vdd_fuse_3v3";
504 regulator-min-microvolt = <3300000>;
505 regulator-max-microvolt = <3300000>;
507 gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
508 vin-supply = <&sys_3v3_reg>;
511 vdd_pnl1_reg: regulator@11 {
512 compatible = "regulator-fixed";
514 regulator-name = "vdd_pnl1";
515 regulator-min-microvolt = <3300000>;
516 regulator-max-microvolt = <3300000>;
520 gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
521 vin-supply = <&sys_3v3_reg>;
524 vdd_vid_reg: regulator@12 {
525 compatible = "regulator-fixed";
527 regulator-name = "vddio_vid";
528 regulator-min-microvolt = <5000000>;
529 regulator-max-microvolt = <5000000>;
531 gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
533 vin-supply = <&vdd_5v0_reg>;
538 compatible = "nvidia,tegra-audio-wm8903-cardhu",
539 "nvidia,tegra-audio-wm8903";
540 nvidia,model = "NVIDIA Tegra Cardhu";
542 nvidia,audio-routing =
543 "Headphone Jack", "HPOUTR",
544 "Headphone Jack", "HPOUTL",
549 "Mic Jack", "MICBIAS",
552 nvidia,i2s-controller = <&tegra_i2s1>;
553 nvidia,audio-codec = <&wm8903>;
555 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
556 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
559 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
560 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
561 <&tegra_car TEGRA30_CLK_EXTERN1>;
562 clock-names = "pll_a", "pll_a_out0", "mclk";