arch/arm/boot/dts/tegra30.dtsi

   1 #include <dt-bindings/clock/tegra30-car.h>
   2 #include <dt-bindings/gpio/tegra-gpio.h>
   3 #include <dt-bindings/interrupt-controller/arm-gic.h>
   4
   5 #include "skeleton.dtsi"
   6
   7 / {
   8         compatible = "nvidia,tegra30";
   9         interrupt-parent = <&intc>;
  10
  11         aliases {
  12                 serial0 = &uarta;
  13                 serial1 = &uartb;
  14                 serial2 = &uartc;
  15                 serial3 = &uartd;
  16                 serial4 = &uarte;
  17         };
  18
  19         pcie-controller {
  20                 compatible = "nvidia,tegra30-pcie";
  21                 device_type = "pci";
  22                 reg = <0x00003000 0x00000800   /* PADS registers */
  23                        0x00003800 0x00000200   /* AFI registers */
  24                        0x10000000 0x10000000>; /* configuration space */
  25                 reg-names = "pads", "afi", "cs";
  26                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH   /* controller interrupt */
  27                               GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
  28                 interrupt-names = "intr", "msi";
  29
  30                 bus-range = <0x00 0xff>;
  31                 #address-cells = <3>;
  32                 #size-cells = <2>;
  33
  34                 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000   /* port 0 configuration space */
  35                           0x82000000 0 0x00001000 0x00001000 0 0x00001000   /* port 1 configuration space */
  36                           0x82000000 0 0x00004000 0x00004000 0 0x00001000   /* port 2 configuration space */
  37                           0x81000000 0 0          0x02000000 0 0x00010000   /* downstream I/O */
  38                           0x82000000 0 0x20000000 0x20000000 0 0x08000000   /* non-prefetchable memory */
  39                           0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
  40
  41                 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
  42                          <&tegra_car TEGRA30_CLK_AFI>,
  43                          <&tegra_car TEGRA30_CLK_PLL_E>,
  44                          <&tegra_car TEGRA30_CLK_CML0>;
  45                 clock-names = "pex", "afi", "pll_e", "cml";
  46                 resets = <&tegra_car 70>,
  47                          <&tegra_car 72>,
  48                          <&tegra_car 74>;
  49                 reset-names = "pex", "afi", "pcie_x";
  50                 status = "disabled";
  51
  52                 pci@1,0 {
  53                         device_type = "pci";
  54                         assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
  55                         reg = <0x000800 0 0 0 0>;
  56                         status = "disabled";
  57
  58                         #address-cells = <3>;
  59                         #size-cells = <2>;
  60                         ranges;
  61
  62                         nvidia,num-lanes = <2>;
  63                 };
  64
  65                 pci@2,0 {
  66                         device_type = "pci";
  67                         assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
  68                         reg = <0x001000 0 0 0 0>;
  69                         status = "disabled";
  70
  71                         #address-cells = <3>;
  72                         #size-cells = <2>;
  73                         ranges;
  74
  75                         nvidia,num-lanes = <2>;
  76                 };
  77
  78                 pci@3,0 {
  79                         device_type = "pci";
  80                         assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
  81                         reg = <0x001800 0 0 0 0>;
  82                         status = "disabled";
  83
  84                         #address-cells = <3>;
  85                         #size-cells = <2>;
  86                         ranges;
  87
  88                         nvidia,num-lanes = <2>;
  89                 };
  90         };
  91
  92         host1x {
  93                 compatible = "nvidia,tegra30-host1x", "simple-bus";
  94                 reg = <0x50000000 0x00024000>;
  95                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  96                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  97                 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
  98                 resets = <&tegra_car 28>;
  99                 reset-names = "host1x";
 100
 101                 #address-cells = <1>;
 102                 #size-cells = <1>;
 103
 104                 ranges = <0x54000000 0x54000000 0x04000000>;
 105
 106                 mpe {
 107                         compatible = "nvidia,tegra30-mpe";
 108                         reg = <0x54040000 0x00040000>;
 109                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 110                         clocks = <&tegra_car TEGRA30_CLK_MPE>;
 111                         resets = <&tegra_car 60>;
 112                         reset-names = "mpe";
 113                 };
 114
 115                 vi {
 116                         compatible = "nvidia,tegra30-vi";
 117                         reg = <0x54080000 0x00040000>;
 118                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 119                         clocks = <&tegra_car TEGRA30_CLK_VI>;
 120                         resets = <&tegra_car 20>;
 121                         reset-names = "vi";
 122                 };
 123
 124                 epp {
 125                         compatible = "nvidia,tegra30-epp";
 126                         reg = <0x540c0000 0x00040000>;
 127                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 128                         clocks = <&tegra_car TEGRA30_CLK_EPP>;
 129                         resets = <&tegra_car 19>;
 130                         reset-names = "epp";
 131                 };
 132
 133                 isp {
 134                         compatible = "nvidia,tegra30-isp";
 135                         reg = <0x54100000 0x00040000>;
 136                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 137                         clocks = <&tegra_car TEGRA30_CLK_ISP>;
 138                         resets = <&tegra_car 23>;
 139                         reset-names = "isp";
 140                 };
 141
 142                 gr2d {
 143                         compatible = "nvidia,tegra30-gr2d";
 144                         reg = <0x54140000 0x00040000>;
 145                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 146                         resets = <&tegra_car 21>;
 147                         reset-names = "2d";
 148                         clocks = <&tegra_car TEGRA30_CLK_GR2D>;
 149                 };
 150
 151                 gr3d {
 152                         compatible = "nvidia,tegra30-gr3d";
 153                         reg = <0x54180000 0x00040000>;
 154                         clocks = <&tegra_car TEGRA30_CLK_GR3D
 155                                   &tegra_car TEGRA30_CLK_GR3D2>;
 156                         clock-names = "3d", "3d2";
 157                         resets = <&tegra_car 24>,
 158                                  <&tegra_car 98>;
 159                         reset-names = "3d", "3d2";
 160                 };
 161
 162                 dc@54200000 {
 163                         compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
 164                         reg = <0x54200000 0x00040000>;
 165                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 166                         clocks = <&tegra_car TEGRA30_CLK_DISP1>,
 167                                  <&tegra_car TEGRA30_CLK_PLL_P>;
 168                         clock-names = "dc", "parent";
 169                         resets = <&tegra_car 27>;
 170                         reset-names = "dc";
 171
 172                         rgb {
 173                                 status = "disabled";
 174                         };
 175                 };
 176
 177                 dc@54240000 {
 178                         compatible = "nvidia,tegra30-dc";
 179                         reg = <0x54240000 0x00040000>;
 180                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 181                         clocks = <&tegra_car TEGRA30_CLK_DISP2>,
 182                                  <&tegra_car TEGRA30_CLK_PLL_P>;
 183                         clock-names = "dc", "parent";
 184                         resets = <&tegra_car 26>;
 185                         reset-names = "dc";
 186
 187                         rgb {
 188                                 status = "disabled";
 189                         };
 190                 };
 191
 192                 hdmi {
 193                         compatible = "nvidia,tegra30-hdmi";
 194                         reg = <0x54280000 0x00040000>;
 195                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 196                         clocks = <&tegra_car TEGRA30_CLK_HDMI>,
 197                                  <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
 198                         clock-names = "hdmi", "parent";
 199                         resets = <&tegra_car 51>;
 200                         reset-names = "hdmi";
 201                         status = "disabled";
 202                 };
 203
 204                 tvo {
 205                         compatible = "nvidia,tegra30-tvo";
 206                         reg = <0x542c0000 0x00040000>;
 207                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 208                         clocks = <&tegra_car TEGRA30_CLK_TVO>;
 209                         status = "disabled";
 210                 };
 211
 212                 dsi {
 213                         compatible = "nvidia,tegra30-dsi";
 214                         reg = <0x54300000 0x00040000>;
 215                         clocks = <&tegra_car TEGRA30_CLK_DSIA>;
 216                         resets = <&tegra_car 48>;
 217                         reset-names = "dsi";
 218                         status = "disabled";
 219                 };
 220         };
 221
 222         timer@50004600 {
 223                 compatible = "arm,cortex-a9-twd-timer";
 224                 reg = <0x50040600 0x20>;
 225                 interrupts = <GIC_PPI 13
 226                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 227                 clocks = <&tegra_car TEGRA30_CLK_TWD>;
 228         };
 229
 230         intc: interrupt-controller {
 231                 compatible = "arm,cortex-a9-gic";
 232                 reg = <0x50041000 0x1000
 233                        0x50040100 0x0100>;
 234                 interrupt-controller;
 235                 #interrupt-cells = <3>;
 236         };
 237
 238         cache-controller {
 239                 compatible = "arm,pl310-cache";
 240                 reg = <0x50043000 0x1000>;
 241                 arm,data-latency = <6 6 2>;
 242                 arm,tag-latency = <5 5 2>;
 243                 cache-unified;
 244                 cache-level = <2>;
 245         };
 246
 247         timer@60005000 {
 248                 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
 249                 reg = <0x60005000 0x400>;
 250                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 251                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 252                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 253                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 254                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 255                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 256                 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
 257         };
 258
 259         tegra_car: clock {
 260                 compatible = "nvidia,tegra30-car";
 261                 reg = <0x60006000 0x1000>;
 262                 #clock-cells = <1>;
 263                 #reset-cells = <1>;
 264         };
 265
 266         apbdma: dma {
 267                 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
 268                 reg = <0x6000a000 0x1400>;
 269                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 270                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 271                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 272                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 273                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 274                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 275                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 276                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 277                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 278                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 279                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 280                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 281                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 282                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 283                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 284                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 285                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 286                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 287                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 288                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 289                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 290                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 291                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 292                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 293                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 294                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 295                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 296                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 297                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 298                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 299                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 300                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 301                 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
 302                 resets = <&tegra_car 34>;
 303                 reset-names = "dma";
 304                 #dma-cells = <1>;
 305         };
 306
 307         ahb: ahb {
 308                 compatible = "nvidia,tegra30-ahb";
 309                 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
 310         };
 311
 312         gpio: gpio {
 313                 compatible = "nvidia,tegra30-gpio";
 314                 reg = <0x6000d000 0x1000>;
 315                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 316                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 317                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 318                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 319                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 320                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 321                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 322                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 323                 #gpio-cells = <2>;
 324                 gpio-controller;
 325                 #interrupt-cells = <2>;
 326                 interrupt-controller;
 327         };
 328
 329         pinmux: pinmux {
 330                 compatible = "nvidia,tegra30-pinmux";
 331                 reg = <0x70000868 0xd4    /* Pad control registers */
 332                        0x70003000 0x3e4>; /* Mux registers */
 333         };
 334
 335         /*
 336          * There are two serial driver i.e. 8250 based simple serial
 337          * driver and APB DMA based serial driver for higher baudrate
 338          * and performace. To enable the 8250 based driver, the compatible
 339          * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
 340          * the APB DMA based serial driver, the comptible is
 341          * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
 342          */
 343         uarta: serial@70006000 {
 344                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 345                 reg = <0x70006000 0x40>;
 346                 reg-shift = <2>;
 347                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 348                 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
 349                 resets = <&tegra_car 6>;
 350                 reset-names = "serial";
 351                 dmas = <&apbdma 8>, <&apbdma 8>;
 352                 dma-names = "rx", "tx";
 353                 status = "disabled";
 354         };
 355
 356         uartb: serial@70006040 {
 357                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 358                 reg = <0x70006040 0x40>;
 359                 reg-shift = <2>;
 360                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 361                 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
 362                 resets = <&tegra_car 7>;
 363                 reset-names = "serial";
 364                 dmas = <&apbdma 9>, <&apbdma 9>;
 365                 dma-names = "rx", "tx";
 366                 status = "disabled";
 367         };
 368
 369         uartc: serial@70006200 {
 370                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 371                 reg = <0x70006200 0x100>;
 372                 reg-shift = <2>;
 373                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 374                 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
 375                 resets = <&tegra_car 55>;
 376                 reset-names = "serial";
 377                 dmas = <&apbdma 10>, <&apbdma 10>;
 378                 dma-names = "rx", "tx";
 379                 status = "disabled";
 380         };
 381
 382         uartd: serial@70006300 {
 383                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 384                 reg = <0x70006300 0x100>;
 385                 reg-shift = <2>;
 386                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 387                 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
 388                 resets = <&tegra_car 65>;
 389                 reset-names = "serial";
 390                 dmas = <&apbdma 19>, <&apbdma 19>;
 391                 dma-names = "rx", "tx";
 392                 status = "disabled";
 393         };
 394
 395         uarte: serial@70006400 {
 396                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 397                 reg = <0x70006400 0x100>;
 398                 reg-shift = <2>;
 399                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 400                 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
 401                 resets = <&tegra_car 66>;
 402                 reset-names = "serial";
 403                 dmas = <&apbdma 20>, <&apbdma 20>;
 404                 dma-names = "rx", "tx";
 405                 status = "disabled";
 406         };
 407
 408         pwm: pwm {
 409                 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
 410                 reg = <0x7000a000 0x100>;
 411                 #pwm-cells = <2>;
 412                 clocks = <&tegra_car TEGRA30_CLK_PWM>;
 413                 resets = <&tegra_car 17>;
 414                 reset-names = "pwm";
 415                 status = "disabled";
 416         };
 417
 418         rtc {
 419                 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
 420                 reg = <0x7000e000 0x100>;
 421                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 422                 clocks = <&tegra_car TEGRA30_CLK_RTC>;
 423         };
 424
 425         i2c@7000c000 {
 426                 compatible =  "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 427                 reg = <0x7000c000 0x100>;
 428                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 429                 #address-cells = <1>;
 430                 #size-cells = <0>;
 431                 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
 432                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 433                 clock-names = "div-clk", "fast-clk";
 434                 resets = <&tegra_car 12>;
 435                 reset-names = "i2c";
 436                 dmas = <&apbdma 21>, <&apbdma 21>;
 437                 dma-names = "rx", "tx";
 438                 status = "disabled";
 439         };
 440
 441         i2c@7000c400 {
 442                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 443                 reg = <0x7000c400 0x100>;
 444                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 445                 #address-cells = <1>;
 446                 #size-cells = <0>;
 447                 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
 448                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 449                 clock-names = "div-clk", "fast-clk";
 450                 resets = <&tegra_car 54>;
 451                 reset-names = "i2c";
 452                 dmas = <&apbdma 22>, <&apbdma 22>;
 453                 dma-names = "rx", "tx";
 454                 status = "disabled";
 455         };
 456
 457         i2c@7000c500 {
 458                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 459                 reg = <0x7000c500 0x100>;
 460                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 461                 #address-cells = <1>;
 462                 #size-cells = <0>;
 463                 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
 464                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 465                 clock-names = "div-clk", "fast-clk";
 466                 resets = <&tegra_car 67>;
 467                 reset-names = "i2c";
 468                 dmas = <&apbdma 23>, <&apbdma 23>;
 469                 dma-names = "rx", "tx";
 470                 status = "disabled";
 471         };
 472
 473         i2c@7000c700 {
 474                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 475                 reg = <0x7000c700 0x100>;
 476                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 477                 #address-cells = <1>;
 478                 #size-cells = <0>;
 479                 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
 480                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 481                 resets = <&tegra_car 103>;
 482                 reset-names = "i2c";
 483                 clock-names = "div-clk", "fast-clk";
 484                 dmas = <&apbdma 26>, <&apbdma 26>;
 485                 dma-names = "rx", "tx";
 486                 status = "disabled";
 487         };
 488
 489         i2c@7000d000 {
 490                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 491                 reg = <0x7000d000 0x100>;
 492                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 493                 #address-cells = <1>;
 494                 #size-cells = <0>;
 495                 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
 496                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 497                 clock-names = "div-clk", "fast-clk";
 498                 resets = <&tegra_car 47>;
 499                 reset-names = "i2c";
 500                 dmas = <&apbdma 24>, <&apbdma 24>;
 501                 dma-names = "rx", "tx";
 502                 status = "disabled";
 503         };
 504
 505         spi@7000d400 {
 506                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 507                 reg = <0x7000d400 0x200>;
 508                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 509                 #address-cells = <1>;
 510                 #size-cells = <0>;
 511                 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
 512                 resets = <&tegra_car 41>;
 513                 reset-names = "spi";
 514                 dmas = <&apbdma 15>, <&apbdma 15>;
 515                 dma-names = "rx", "tx";
 516                 status = "disabled";
 517         };
 518
 519         spi@7000d600 {
 520                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 521                 reg = <0x7000d600 0x200>;
 522                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 523                 #address-cells = <1>;
 524                 #size-cells = <0>;
 525                 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
 526                 resets = <&tegra_car 44>;
 527                 reset-names = "spi";
 528                 dmas = <&apbdma 16>, <&apbdma 16>;
 529                 dma-names = "rx", "tx";
 530                 status = "disabled";
 531         };
 532
 533         spi@7000d800 {
 534                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 535                 reg = <0x7000d800 0x200>;
 536                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 537                 #address-cells = <1>;
 538                 #size-cells = <0>;
 539                 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
 540                 resets = <&tegra_car 46>;
 541                 reset-names = "spi";
 542                 dmas = <&apbdma 17>, <&apbdma 17>;
 543                 dma-names = "rx", "tx";
 544                 status = "disabled";
 545         };
 546
 547         spi@7000da00 {
 548                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 549                 reg = <0x7000da00 0x200>;
 550                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 551                 #address-cells = <1>;
 552                 #size-cells = <0>;
 553                 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
 554                 resets = <&tegra_car 68>;
 555                 reset-names = "spi";
 556                 dmas = <&apbdma 18>, <&apbdma 18>;
 557                 dma-names = "rx", "tx";
 558                 status = "disabled";
 559         };
 560
 561         spi@7000dc00 {
 562                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 563                 reg = <0x7000dc00 0x200>;
 564                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 565                 #address-cells = <1>;
 566                 #size-cells = <0>;
 567                 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
 568                 resets = <&tegra_car 104>;
 569                 reset-names = "spi";
 570                 dmas = <&apbdma 27>, <&apbdma 27>;
 571                 dma-names = "rx", "tx";
 572                 status = "disabled";
 573         };
 574
 575         spi@7000de00 {
 576                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 577                 reg = <0x7000de00 0x200>;
 578                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 579                 #address-cells = <1>;
 580                 #size-cells = <0>;
 581                 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
 582                 resets = <&tegra_car 106>;
 583                 reset-names = "spi";
 584                 dmas = <&apbdma 28>, <&apbdma 28>;
 585                 dma-names = "rx", "tx";
 586                 status = "disabled";
 587         };
 588
 589         kbc {
 590                 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
 591                 reg = <0x7000e200 0x100>;
 592                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 593                 clocks = <&tegra_car TEGRA30_CLK_KBC>;
 594                 resets = <&tegra_car 36>;
 595                 reset-names = "kbc";
 596                 status = "disabled";
 597         };
 598
 599         pmc {
 600                 compatible = "nvidia,tegra30-pmc";
 601                 reg = <0x7000e400 0x400>;
 602                 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
 603                 clock-names = "pclk", "clk32k_in";
 604         };
 605
 606         memory-controller {
 607                 compatible = "nvidia,tegra30-mc";
 608                 reg = <0x7000f000 0x010
 609                        0x7000f03c 0x1b4
 610                        0x7000f200 0x028
 611                        0x7000f284 0x17c>;
 612                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 613         };
 614
 615         iommu {
 616                 compatible = "nvidia,tegra30-smmu";
 617                 reg = <0x7000f010 0x02c
 618                        0x7000f1f0 0x010
 619                        0x7000f228 0x05c>;
 620                 nvidia,#asids = <4>;            /* # of ASIDs */
 621                 dma-window = <0 0x40000000>;    /* IOVA start & length */
 622                 nvidia,ahb = <&ahb>;
 623         };
 624
 625         ahub {
 626                 compatible = "nvidia,tegra30-ahub";
 627                 reg = <0x70080000 0x200
 628                        0x70080200 0x100>;
 629                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 630                 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
 631                          <&tegra_car TEGRA30_CLK_APBIF>;
 632                 clock-names = "d_audio", "apbif";
 633                 resets = <&tegra_car 106>, /* d_audio */
 634                          <&tegra_car 107>, /* apbif */
 635                          <&tegra_car 30>,  /* i2s0 */
 636                          <&tegra_car 11>,  /* i2s1 */
 637                          <&tegra_car 18>,  /* i2s2 */
 638                          <&tegra_car 101>, /* i2s3 */
 639                          <&tegra_car 102>, /* i2s4 */
 640                          <&tegra_car 108>, /* dam0 */
 641                          <&tegra_car 109>, /* dam1 */
 642                          <&tegra_car 110>, /* dam2 */
 643                          <&tegra_car 10>;  /* spdif */
 644                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 645                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 646                               "spdif";
 647                 dmas = <&apbdma 1>, <&apbdma 1>,
 648                        <&apbdma 2>, <&apbdma 2>,
 649                        <&apbdma 3>, <&apbdma 3>,
 650                        <&apbdma 4>, <&apbdma 4>;
 651                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 652                             "rx3", "tx3";
 653                 ranges;
 654                 #address-cells = <1>;
 655                 #size-cells = <1>;
 656
 657                 tegra_i2s0: i2s@70080300 {
 658                         compatible = "nvidia,tegra30-i2s";
 659                         reg = <0x70080300 0x100>;
 660                         nvidia,ahub-cif-ids = <4 4>;
 661                         clocks = <&tegra_car TEGRA30_CLK_I2S0>;
 662                         resets = <&tegra_car 30>;
 663                         reset-names = "i2s";
 664                         status = "disabled";
 665                 };
 666
 667                 tegra_i2s1: i2s@70080400 {
 668                         compatible = "nvidia,tegra30-i2s";
 669                         reg = <0x70080400 0x100>;
 670                         nvidia,ahub-cif-ids = <5 5>;
 671                         clocks = <&tegra_car TEGRA30_CLK_I2S1>;
 672                         resets = <&tegra_car 11>;
 673                         reset-names = "i2s";
 674                         status = "disabled";
 675                 };
 676
 677                 tegra_i2s2: i2s@70080500 {
 678                         compatible = "nvidia,tegra30-i2s";
 679                         reg = <0x70080500 0x100>;
 680                         nvidia,ahub-cif-ids = <6 6>;
 681                         clocks = <&tegra_car TEGRA30_CLK_I2S2>;
 682                         resets = <&tegra_car 18>;
 683                         reset-names = "i2s";
 684                         status = "disabled";
 685                 };
 686
 687                 tegra_i2s3: i2s@70080600 {
 688                         compatible = "nvidia,tegra30-i2s";
 689                         reg = <0x70080600 0x100>;
 690                         nvidia,ahub-cif-ids = <7 7>;
 691                         clocks = <&tegra_car TEGRA30_CLK_I2S3>;
 692                         resets = <&tegra_car 101>;
 693                         reset-names = "i2s";
 694                         status = "disabled";
 695                 };
 696
 697                 tegra_i2s4: i2s@70080700 {
 698                         compatible = "nvidia,tegra30-i2s";
 699                         reg = <0x70080700 0x100>;
 700                         nvidia,ahub-cif-ids = <8 8>;
 701                         clocks = <&tegra_car TEGRA30_CLK_I2S4>;
 702                         resets = <&tegra_car 102>;
 703                         reset-names = "i2s";
 704                         status = "disabled";
 705                 };
 706         };
 707
 708         sdhci@78000000 {
 709                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 710                 reg = <0x78000000 0x200>;
 711                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 712                 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
 713                 resets = <&tegra_car 14>;
 714                 reset-names = "sdhci";
 715                 status = "disabled";
 716         };
 717
 718         sdhci@78000200 {
 719                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 720                 reg = <0x78000200 0x200>;
 721                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 722                 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
 723                 resets = <&tegra_car 9>;
 724                 reset-names = "sdhci";
 725                 status = "disabled";
 726         };
 727
 728         sdhci@78000400 {
 729                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 730                 reg = <0x78000400 0x200>;
 731                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 732                 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
 733                 resets = <&tegra_car 69>;
 734                 reset-names = "sdhci";
 735                 status = "disabled";
 736         };
 737
 738         sdhci@78000600 {
 739                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 740                 reg = <0x78000600 0x200>;
 741                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 742                 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
 743                 resets = <&tegra_car 15>;
 744                 reset-names = "sdhci";
 745                 status = "disabled";
 746         };
 747
 748         usb@7d000000 {
 749                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 750                 reg = <0x7d000000 0x4000>;
 751                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 752                 phy_type = "utmi";
 753                 clocks = <&tegra_car TEGRA30_CLK_USBD>;
 754                 resets = <&tegra_car 22>;
 755                 reset-names = "usb";
 756                 nvidia,needs-double-reset;
 757                 nvidia,phy = <&phy1>;
 758                 status = "disabled";
 759         };
 760
 761         phy1: usb-phy@7d000000 {
 762                 compatible = "nvidia,tegra30-usb-phy";
 763                 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
 764                 phy_type = "utmi";
 765                 clocks = <&tegra_car TEGRA30_CLK_USBD>,
 766                          <&tegra_car TEGRA30_CLK_PLL_U>,
 767                          <&tegra_car TEGRA30_CLK_USBD>;
 768                 clock-names = "reg", "pll_u", "utmi-pads";
 769                 nvidia,hssync-start-delay = <9>;
 770                 nvidia,idle-wait-delay = <17>;
 771                 nvidia,elastic-limit = <16>;
 772                 nvidia,term-range-adj = <6>;
 773                 nvidia,xcvr-setup = <51>;
 774                 nvidia.xcvr-setup-use-fuses;
 775                 nvidia,xcvr-lsfslew = <1>;
 776                 nvidia,xcvr-lsrslew = <1>;
 777                 nvidia,xcvr-hsslew = <32>;
 778                 nvidia,hssquelch-level = <2>;
 779                 nvidia,hsdiscon-level = <5>;
 780                 status = "disabled";
 781         };
 782
 783         usb@7d004000 {
 784                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 785                 reg = <0x7d004000 0x4000>;
 786                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 787                 phy_type = "ulpi";
 788                 clocks = <&tegra_car TEGRA30_CLK_USB2>;
 789                 resets = <&tegra_car 58>;
 790                 reset-names = "usb";
 791                 nvidia,phy = <&phy2>;
 792                 status = "disabled";
 793         };
 794
 795         phy2: usb-phy@7d004000 {
 796                 compatible = "nvidia,tegra30-usb-phy";
 797                 reg = <0x7d004000 0x4000>;
 798                 phy_type = "ulpi";
 799                 clocks = <&tegra_car TEGRA30_CLK_USB2>,
 800                          <&tegra_car TEGRA30_CLK_PLL_U>,
 801                          <&tegra_car TEGRA30_CLK_CDEV2>;
 802                 clock-names = "reg", "pll_u", "ulpi-link";
 803                 status = "disabled";
 804         };
 805
 806         usb@7d008000 {
 807                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 808                 reg = <0x7d008000 0x4000>;
 809                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 810                 phy_type = "utmi";
 811                 clocks = <&tegra_car TEGRA30_CLK_USB3>;
 812                 resets = <&tegra_car 59>;
 813                 reset-names = "usb";
 814                 nvidia,phy = <&phy3>;
 815                 status = "disabled";
 816         };
 817
 818         phy3: usb-phy@7d008000 {
 819                 compatible = "nvidia,tegra30-usb-phy";
 820                 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
 821                 phy_type = "utmi";
 822                 clocks = <&tegra_car TEGRA30_CLK_USB3>,
 823                          <&tegra_car TEGRA30_CLK_PLL_U>,
 824                          <&tegra_car TEGRA30_CLK_USBD>;
 825                 clock-names = "reg", "pll_u", "utmi-pads";
 826                 nvidia,hssync-start-delay = <0>;
 827                 nvidia,idle-wait-delay = <17>;
 828                 nvidia,elastic-limit = <16>;
 829                 nvidia,term-range-adj = <6>;
 830                 nvidia,xcvr-setup = <51>;
 831                 nvidia.xcvr-setup-use-fuses;
 832                 nvidia,xcvr-lsfslew = <2>;
 833                 nvidia,xcvr-lsrslew = <2>;
 834                 nvidia,xcvr-hsslew = <32>;
 835                 nvidia,hssquelch-level = <2>;
 836                 nvidia,hsdiscon-level = <5>;
 837                 status = "disabled";
 838         };
 839
 840         cpus {
 841                 #address-cells = <1>;
 842                 #size-cells = <0>;
 843
 844                 cpu@0 {
 845                         device_type = "cpu";
 846                         compatible = "arm,cortex-a9";
 847                         reg = <0>;
 848                 };
 849
 850                 cpu@1 {
 851                         device_type = "cpu";
 852                         compatible = "arm,cortex-a9";
 853                         reg = <1>;
 854                 };
 855
 856                 cpu@2 {
 857                         device_type = "cpu";
 858                         compatible = "arm,cortex-a9";
 859                         reg = <2>;
 860                 };
 861
 862                 cpu@3 {
 863                         device_type = "cpu";
 864                         compatible = "arm,cortex-a9";
 865                         reg = <3>;
 866                 };
 867         };
 868
 869         pmu {
 870                 compatible = "arm,cortex-a9-pmu";
 871                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
 872                              <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 873                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 874                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 875         };
 876 };