1 #include <dt-bindings/clock/tegra30-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include "skeleton.dtsi"
9 compatible = "nvidia,tegra30";
10 interrupt-parent = <&intc>;
20 pcie-controller@00003000 {
21 compatible = "nvidia,tegra30-pcie";
23 reg = <0x00003000 0x00000800 /* PADS registers */
24 0x00003800 0x00000200 /* AFI registers */
25 0x10000000 0x10000000>; /* configuration space */
26 reg-names = "pads", "afi", "cs";
27 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
28 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
29 interrupt-names = "intr", "msi";
31 bus-range = <0x00 0xff>;
35 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
36 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
37 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
38 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
39 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
40 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
42 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
43 <&tegra_car TEGRA30_CLK_AFI>,
44 <&tegra_car TEGRA30_CLK_PLL_E>,
45 <&tegra_car TEGRA30_CLK_CML0>;
46 clock-names = "pex", "afi", "pll_e", "cml";
47 resets = <&tegra_car 70>,
50 reset-names = "pex", "afi", "pcie_x";
55 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
56 reg = <0x000800 0 0 0 0>;
63 nvidia,num-lanes = <2>;
68 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
69 reg = <0x001000 0 0 0 0>;
76 nvidia,num-lanes = <2>;
81 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
82 reg = <0x001800 0 0 0 0>;
89 nvidia,num-lanes = <2>;
94 compatible = "nvidia,tegra30-host1x", "simple-bus";
95 reg = <0x50000000 0x00024000>;
96 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
97 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
98 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
99 resets = <&tegra_car 28>;
100 reset-names = "host1x";
102 #address-cells = <1>;
105 ranges = <0x54000000 0x54000000 0x04000000>;
108 compatible = "nvidia,tegra30-mpe";
109 reg = <0x54040000 0x00040000>;
110 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
111 clocks = <&tegra_car TEGRA30_CLK_MPE>;
112 resets = <&tegra_car 60>;
117 compatible = "nvidia,tegra30-vi";
118 reg = <0x54080000 0x00040000>;
119 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
120 clocks = <&tegra_car TEGRA30_CLK_VI>;
121 resets = <&tegra_car 20>;
126 compatible = "nvidia,tegra30-epp";
127 reg = <0x540c0000 0x00040000>;
128 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
129 clocks = <&tegra_car TEGRA30_CLK_EPP>;
130 resets = <&tegra_car 19>;
135 compatible = "nvidia,tegra30-isp";
136 reg = <0x54100000 0x00040000>;
137 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
138 clocks = <&tegra_car TEGRA30_CLK_ISP>;
139 resets = <&tegra_car 23>;
144 compatible = "nvidia,tegra30-gr2d";
145 reg = <0x54140000 0x00040000>;
146 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
147 resets = <&tegra_car 21>;
149 clocks = <&tegra_car TEGRA30_CLK_GR2D>;
153 compatible = "nvidia,tegra30-gr3d";
154 reg = <0x54180000 0x00040000>;
155 clocks = <&tegra_car TEGRA30_CLK_GR3D
156 &tegra_car TEGRA30_CLK_GR3D2>;
157 clock-names = "3d", "3d2";
158 resets = <&tegra_car 24>,
160 reset-names = "3d", "3d2";
164 compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
165 reg = <0x54200000 0x00040000>;
166 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
167 clocks = <&tegra_car TEGRA30_CLK_DISP1>,
168 <&tegra_car TEGRA30_CLK_PLL_P>;
169 clock-names = "dc", "parent";
170 resets = <&tegra_car 27>;
179 compatible = "nvidia,tegra30-dc";
180 reg = <0x54240000 0x00040000>;
181 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
182 clocks = <&tegra_car TEGRA30_CLK_DISP2>,
183 <&tegra_car TEGRA30_CLK_PLL_P>;
184 clock-names = "dc", "parent";
185 resets = <&tegra_car 26>;
194 compatible = "nvidia,tegra30-hdmi";
195 reg = <0x54280000 0x00040000>;
196 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&tegra_car TEGRA30_CLK_HDMI>,
198 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
199 clock-names = "hdmi", "parent";
200 resets = <&tegra_car 51>;
201 reset-names = "hdmi";
206 compatible = "nvidia,tegra30-tvo";
207 reg = <0x542c0000 0x00040000>;
208 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&tegra_car TEGRA30_CLK_TVO>;
214 compatible = "nvidia,tegra30-dsi";
215 reg = <0x54300000 0x00040000>;
216 clocks = <&tegra_car TEGRA30_CLK_DSIA>;
217 resets = <&tegra_car 48>;
224 compatible = "arm,cortex-a9-twd-timer";
225 reg = <0x50040600 0x20>;
226 interrupts = <GIC_PPI 13
227 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
228 clocks = <&tegra_car TEGRA30_CLK_TWD>;
231 intc: interrupt-controller@50041000 {
232 compatible = "arm,cortex-a9-gic";
233 reg = <0x50041000 0x1000
235 interrupt-controller;
236 #interrupt-cells = <3>;
239 cache-controller@50043000 {
240 compatible = "arm,pl310-cache";
241 reg = <0x50043000 0x1000>;
242 arm,data-latency = <6 6 2>;
243 arm,tag-latency = <5 5 2>;
249 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
250 reg = <0x60005000 0x400>;
251 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
260 tegra_car: clock@60006000 {
261 compatible = "nvidia,tegra30-car";
262 reg = <0x60006000 0x1000>;
267 apbdma: dma@6000a000 {
268 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
269 reg = <0x6000a000 0x1400>;
270 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
271 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
302 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
303 resets = <&tegra_car 34>;
309 compatible = "nvidia,tegra30-ahb";
310 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
313 gpio: gpio@6000d000 {
314 compatible = "nvidia,tegra30-gpio";
315 reg = <0x6000d000 0x1000>;
316 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
317 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
326 #interrupt-cells = <2>;
327 interrupt-controller;
330 pinmux: pinmux@70000868 {
331 compatible = "nvidia,tegra30-pinmux";
332 reg = <0x70000868 0xd4 /* Pad control registers */
333 0x70003000 0x3e4>; /* Mux registers */
337 * There are two serial driver i.e. 8250 based simple serial
338 * driver and APB DMA based serial driver for higher baudrate
339 * and performace. To enable the 8250 based driver, the compatible
340 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
341 * the APB DMA based serial driver, the comptible is
342 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
344 uarta: serial@70006000 {
345 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
346 reg = <0x70006000 0x40>;
348 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
350 resets = <&tegra_car 6>;
351 reset-names = "serial";
352 dmas = <&apbdma 8>, <&apbdma 8>;
353 dma-names = "rx", "tx";
357 uartb: serial@70006040 {
358 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
359 reg = <0x70006040 0x40>;
361 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
363 resets = <&tegra_car 7>;
364 reset-names = "serial";
365 dmas = <&apbdma 9>, <&apbdma 9>;
366 dma-names = "rx", "tx";
370 uartc: serial@70006200 {
371 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
372 reg = <0x70006200 0x100>;
374 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
375 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
376 resets = <&tegra_car 55>;
377 reset-names = "serial";
378 dmas = <&apbdma 10>, <&apbdma 10>;
379 dma-names = "rx", "tx";
383 uartd: serial@70006300 {
384 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
385 reg = <0x70006300 0x100>;
387 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
389 resets = <&tegra_car 65>;
390 reset-names = "serial";
391 dmas = <&apbdma 19>, <&apbdma 19>;
392 dma-names = "rx", "tx";
396 uarte: serial@70006400 {
397 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
398 reg = <0x70006400 0x100>;
400 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
401 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
402 resets = <&tegra_car 66>;
403 reset-names = "serial";
404 dmas = <&apbdma 20>, <&apbdma 20>;
405 dma-names = "rx", "tx";
410 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
411 reg = <0x7000a000 0x100>;
413 clocks = <&tegra_car TEGRA30_CLK_PWM>;
414 resets = <&tegra_car 17>;
420 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
421 reg = <0x7000e000 0x100>;
422 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
423 clocks = <&tegra_car TEGRA30_CLK_RTC>;
427 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
428 reg = <0x7000c000 0x100>;
429 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
430 #address-cells = <1>;
432 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
433 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
434 clock-names = "div-clk", "fast-clk";
435 resets = <&tegra_car 12>;
437 dmas = <&apbdma 21>, <&apbdma 21>;
438 dma-names = "rx", "tx";
443 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
444 reg = <0x7000c400 0x100>;
445 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
446 #address-cells = <1>;
448 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
449 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
450 clock-names = "div-clk", "fast-clk";
451 resets = <&tegra_car 54>;
453 dmas = <&apbdma 22>, <&apbdma 22>;
454 dma-names = "rx", "tx";
459 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
460 reg = <0x7000c500 0x100>;
461 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
462 #address-cells = <1>;
464 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
465 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
466 clock-names = "div-clk", "fast-clk";
467 resets = <&tegra_car 67>;
469 dmas = <&apbdma 23>, <&apbdma 23>;
470 dma-names = "rx", "tx";
475 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
476 reg = <0x7000c700 0x100>;
477 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
478 #address-cells = <1>;
480 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
481 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
482 resets = <&tegra_car 103>;
484 clock-names = "div-clk", "fast-clk";
485 dmas = <&apbdma 26>, <&apbdma 26>;
486 dma-names = "rx", "tx";
491 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
492 reg = <0x7000d000 0x100>;
493 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
494 #address-cells = <1>;
496 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
497 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
498 clock-names = "div-clk", "fast-clk";
499 resets = <&tegra_car 47>;
501 dmas = <&apbdma 24>, <&apbdma 24>;
502 dma-names = "rx", "tx";
507 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
508 reg = <0x7000d400 0x200>;
509 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
510 #address-cells = <1>;
512 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
513 resets = <&tegra_car 41>;
515 dmas = <&apbdma 15>, <&apbdma 15>;
516 dma-names = "rx", "tx";
521 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
522 reg = <0x7000d600 0x200>;
523 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
524 #address-cells = <1>;
526 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
527 resets = <&tegra_car 44>;
529 dmas = <&apbdma 16>, <&apbdma 16>;
530 dma-names = "rx", "tx";
535 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
536 reg = <0x7000d800 0x200>;
537 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
538 #address-cells = <1>;
540 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
541 resets = <&tegra_car 46>;
543 dmas = <&apbdma 17>, <&apbdma 17>;
544 dma-names = "rx", "tx";
549 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
550 reg = <0x7000da00 0x200>;
551 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
552 #address-cells = <1>;
554 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
555 resets = <&tegra_car 68>;
557 dmas = <&apbdma 18>, <&apbdma 18>;
558 dma-names = "rx", "tx";
563 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
564 reg = <0x7000dc00 0x200>;
565 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
566 #address-cells = <1>;
568 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
569 resets = <&tegra_car 104>;
571 dmas = <&apbdma 27>, <&apbdma 27>;
572 dma-names = "rx", "tx";
577 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
578 reg = <0x7000de00 0x200>;
579 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
580 #address-cells = <1>;
582 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
583 resets = <&tegra_car 106>;
585 dmas = <&apbdma 28>, <&apbdma 28>;
586 dma-names = "rx", "tx";
591 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
592 reg = <0x7000e200 0x100>;
593 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
594 clocks = <&tegra_car TEGRA30_CLK_KBC>;
595 resets = <&tegra_car 36>;
601 compatible = "nvidia,tegra30-pmc";
602 reg = <0x7000e400 0x400>;
603 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
604 clock-names = "pclk", "clk32k_in";
607 memory-controller@7000f000 {
608 compatible = "nvidia,tegra30-mc";
609 reg = <0x7000f000 0x010
613 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
617 compatible = "nvidia,tegra30-smmu";
618 reg = <0x7000f010 0x02c
621 nvidia,#asids = <4>; /* # of ASIDs */
622 dma-window = <0 0x40000000>; /* IOVA start & length */
627 compatible = "nvidia,tegra30-ahub";
628 reg = <0x70080000 0x200
630 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
631 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
632 <&tegra_car TEGRA30_CLK_APBIF>;
633 clock-names = "d_audio", "apbif";
634 resets = <&tegra_car 106>, /* d_audio */
635 <&tegra_car 107>, /* apbif */
636 <&tegra_car 30>, /* i2s0 */
637 <&tegra_car 11>, /* i2s1 */
638 <&tegra_car 18>, /* i2s2 */
639 <&tegra_car 101>, /* i2s3 */
640 <&tegra_car 102>, /* i2s4 */
641 <&tegra_car 108>, /* dam0 */
642 <&tegra_car 109>, /* dam1 */
643 <&tegra_car 110>, /* dam2 */
644 <&tegra_car 10>; /* spdif */
645 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
646 "i2s3", "i2s4", "dam0", "dam1", "dam2",
648 dmas = <&apbdma 1>, <&apbdma 1>,
649 <&apbdma 2>, <&apbdma 2>,
650 <&apbdma 3>, <&apbdma 3>,
651 <&apbdma 4>, <&apbdma 4>;
652 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
655 #address-cells = <1>;
658 tegra_i2s0: i2s@70080300 {
659 compatible = "nvidia,tegra30-i2s";
660 reg = <0x70080300 0x100>;
661 nvidia,ahub-cif-ids = <4 4>;
662 clocks = <&tegra_car TEGRA30_CLK_I2S0>;
663 resets = <&tegra_car 30>;
668 tegra_i2s1: i2s@70080400 {
669 compatible = "nvidia,tegra30-i2s";
670 reg = <0x70080400 0x100>;
671 nvidia,ahub-cif-ids = <5 5>;
672 clocks = <&tegra_car TEGRA30_CLK_I2S1>;
673 resets = <&tegra_car 11>;
678 tegra_i2s2: i2s@70080500 {
679 compatible = "nvidia,tegra30-i2s";
680 reg = <0x70080500 0x100>;
681 nvidia,ahub-cif-ids = <6 6>;
682 clocks = <&tegra_car TEGRA30_CLK_I2S2>;
683 resets = <&tegra_car 18>;
688 tegra_i2s3: i2s@70080600 {
689 compatible = "nvidia,tegra30-i2s";
690 reg = <0x70080600 0x100>;
691 nvidia,ahub-cif-ids = <7 7>;
692 clocks = <&tegra_car TEGRA30_CLK_I2S3>;
693 resets = <&tegra_car 101>;
698 tegra_i2s4: i2s@70080700 {
699 compatible = "nvidia,tegra30-i2s";
700 reg = <0x70080700 0x100>;
701 nvidia,ahub-cif-ids = <8 8>;
702 clocks = <&tegra_car TEGRA30_CLK_I2S4>;
703 resets = <&tegra_car 102>;
710 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
711 reg = <0x78000000 0x200>;
712 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
714 resets = <&tegra_car 14>;
715 reset-names = "sdhci";
720 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
721 reg = <0x78000200 0x200>;
722 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
723 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
724 resets = <&tegra_car 9>;
725 reset-names = "sdhci";
730 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
731 reg = <0x78000400 0x200>;
732 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
733 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
734 resets = <&tegra_car 69>;
735 reset-names = "sdhci";
740 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
741 reg = <0x78000600 0x200>;
742 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
743 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
744 resets = <&tegra_car 15>;
745 reset-names = "sdhci";
750 compatible = "nvidia,tegra30-ehci", "usb-ehci";
751 reg = <0x7d000000 0x4000>;
752 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
754 clocks = <&tegra_car TEGRA30_CLK_USBD>;
755 resets = <&tegra_car 22>;
757 nvidia,needs-double-reset;
758 nvidia,phy = <&phy1>;
762 phy1: usb-phy@7d000000 {
763 compatible = "nvidia,tegra30-usb-phy";
764 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
766 clocks = <&tegra_car TEGRA30_CLK_USBD>,
767 <&tegra_car TEGRA30_CLK_PLL_U>,
768 <&tegra_car TEGRA30_CLK_USBD>;
769 clock-names = "reg", "pll_u", "utmi-pads";
770 nvidia,hssync-start-delay = <9>;
771 nvidia,idle-wait-delay = <17>;
772 nvidia,elastic-limit = <16>;
773 nvidia,term-range-adj = <6>;
774 nvidia,xcvr-setup = <51>;
775 nvidia.xcvr-setup-use-fuses;
776 nvidia,xcvr-lsfslew = <1>;
777 nvidia,xcvr-lsrslew = <1>;
778 nvidia,xcvr-hsslew = <32>;
779 nvidia,hssquelch-level = <2>;
780 nvidia,hsdiscon-level = <5>;
785 compatible = "nvidia,tegra30-ehci", "usb-ehci";
786 reg = <0x7d004000 0x4000>;
787 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
789 clocks = <&tegra_car TEGRA30_CLK_USB2>;
790 resets = <&tegra_car 58>;
792 nvidia,phy = <&phy2>;
796 phy2: usb-phy@7d004000 {
797 compatible = "nvidia,tegra30-usb-phy";
798 reg = <0x7d004000 0x4000 0x7d000000 0x4000>;
800 clocks = <&tegra_car TEGRA30_CLK_USB2>,
801 <&tegra_car TEGRA30_CLK_PLL_U>,
802 <&tegra_car TEGRA30_CLK_USBD>;
803 clock-names = "reg", "pll_u", "utmi-pads";
804 nvidia,hssync-start-delay = <9>;
805 nvidia,idle-wait-delay = <17>;
806 nvidia,elastic-limit = <16>;
807 nvidia,term-range-adj = <6>;
808 nvidia,xcvr-setup = <51>;
809 nvidia.xcvr-setup-use-fuses;
810 nvidia,xcvr-lsfslew = <2>;
811 nvidia,xcvr-lsrslew = <2>;
812 nvidia,xcvr-hsslew = <32>;
813 nvidia,hssquelch-level = <2>;
814 nvidia,hsdiscon-level = <5>;
819 compatible = "nvidia,tegra30-ehci", "usb-ehci";
820 reg = <0x7d008000 0x4000>;
821 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
823 clocks = <&tegra_car TEGRA30_CLK_USB3>;
824 resets = <&tegra_car 59>;
826 nvidia,phy = <&phy3>;
830 phy3: usb-phy@7d008000 {
831 compatible = "nvidia,tegra30-usb-phy";
832 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
834 clocks = <&tegra_car TEGRA30_CLK_USB3>,
835 <&tegra_car TEGRA30_CLK_PLL_U>,
836 <&tegra_car TEGRA30_CLK_USBD>;
837 clock-names = "reg", "pll_u", "utmi-pads";
838 nvidia,hssync-start-delay = <0>;
839 nvidia,idle-wait-delay = <17>;
840 nvidia,elastic-limit = <16>;
841 nvidia,term-range-adj = <6>;
842 nvidia,xcvr-setup = <51>;
843 nvidia.xcvr-setup-use-fuses;
844 nvidia,xcvr-lsfslew = <2>;
845 nvidia,xcvr-lsrslew = <2>;
846 nvidia,xcvr-hsslew = <32>;
847 nvidia,hssquelch-level = <2>;
848 nvidia,hsdiscon-level = <5>;
853 #address-cells = <1>;
858 compatible = "arm,cortex-a9";
864 compatible = "arm,cortex-a9";
870 compatible = "arm,cortex-a9";
876 compatible = "arm,cortex-a9";
882 compatible = "arm,cortex-a9-pmu";
883 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
884 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
885 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
886 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;