arch/arm/boot/dts/uniphier-ph1-sld3.dtsi

   1 /*
   2  * Device Tree Source for UniPhier PH1-sLD3 SoC
   3  *
   4  * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 /include/ "skeleton.dtsi"
  46
  47 / {
  48         compatible = "socionext,ph1-sld3";
  49
  50         cpus {
  51                 #address-cells = <1>;
  52                 #size-cells = <0>;
  53                 enable-method = "socionext,uniphier-smp";
  54
  55                 cpu@0 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a9";
  58                         reg = <0>;
  59                 };
  60
  61                 cpu@1 {
  62                         device_type = "cpu";
  63                         compatible = "arm,cortex-a9";
  64                         reg = <1>;
  65                 };
  66         };
  67
  68         clocks {
  69                 arm_timer_clk: arm_timer_clk {
  70                         #clock-cells = <0>;
  71                         compatible = "fixed-clock";
  72                         clock-frequency = <50000000>;
  73                 };
  74
  75                 uart_clk: uart_clk {
  76                         #clock-cells = <0>;
  77                         compatible = "fixed-clock";
  78                         clock-frequency = <36864000>;
  79                 };
  80         };
  81
  82         soc {
  83                 compatible = "simple-bus";
  84                 #address-cells = <1>;
  85                 #size-cells = <1>;
  86                 ranges;
  87                 interrupt-parent = <&intc>;
  88
  89                 extbus: extbus {
  90                         compatible = "simple-bus";
  91                         #address-cells = <2>;
  92                         #size-cells = <1>;
  93                 };
  94
  95                 timer@20000200 {
  96                         compatible = "arm,cortex-a9-global-timer";
  97                         reg = <0x20000200 0x20>;
  98                         interrupts = <1 11 0x304>;
  99                         clocks = <&arm_timer_clk>;
 100                 };
 101
 102                 timer@20000600 {
 103                         compatible = "arm,cortex-a9-twd-timer";
 104                         reg = <0x20000600 0x20>;
 105                         interrupts = <1 13 0x304>;
 106                         clocks = <&arm_timer_clk>;
 107                 };
 108
 109                 intc: interrupt-controller@20001000 {
 110                         compatible = "arm,cortex-a9-gic";
 111                         #interrupt-cells = <3>;
 112                         interrupt-controller;
 113                         reg = <0x20001000 0x1000>,
 114                               <0x20000100 0x100>;
 115                 };
 116
 117                 serial0: serial@54006800 {
 118                         compatible = "socionext,uniphier-uart";
 119                         status = "disabled";
 120                         reg = <0x54006800 0x40>;
 121                         interrupts = <0 33 4>;
 122                         clocks = <&uart_clk>;
 123                         fifo-size = <64>;
 124                 };
 125
 126                 serial1: serial@54006900 {
 127                         compatible = "socionext,uniphier-uart";
 128                         status = "disabled";
 129                         reg = <0x54006900 0x40>;
 130                         interrupts = <0 35 4>;
 131                         clocks = <&uart_clk>;
 132                         fifo-size = <64>;
 133                 };
 134
 135                 serial2: serial@54006a00 {
 136                         compatible = "socionext,uniphier-uart";
 137                         status = "disabled";
 138                         reg = <0x54006a00 0x40>;
 139                         interrupts = <0 37 4>;
 140                         clocks = <&uart_clk>;
 141                         fifo-size = <64>;
 142                 };
 143
 144                 system-bus-controller-misc@59800000 {
 145                         compatible = "socionext,uniphier-system-bus-controller-misc",
 146                                      "syscon";
 147                         reg = <0x59800000 0x2000>;
 148                 };
 149
 150                 usb0: usb@5a800100 {
 151                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 152                         status = "disabled";
 153                         reg = <0x5a800100 0x100>;
 154                         interrupts = <0 80 4>;
 155                 };
 156
 157                 usb1: usb@5a810100 {
 158                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 159                         status = "disabled";
 160                         reg = <0x5a810100 0x100>;
 161                         interrupts = <0 81 4>;
 162                 };
 163
 164                 usb2: usb@5a820100 {
 165                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 166                         status = "disabled";
 167                         reg = <0x5a820100 0x100>;
 168                         interrupts = <0 82 4>;
 169                 };
 170
 171                 usb3: usb@5a830100 {
 172                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 173                         status = "disabled";
 174                         reg = <0x5a830100 0x100>;
 175                         interrupts = <0 83 4>;
 176                 };
 177         };
 178 };