2 * Device Tree Source for UniPhier PH1-sLD8 SoC
4 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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45 /include/ "skeleton.dtsi"
48 compatible = "socionext,ph1-sld8";
56 compatible = "arm,cortex-a9";
62 arm_timer_clk: arm_timer_clk {
64 compatible = "fixed-clock";
65 clock-frequency = <50000000>;
70 compatible = "fixed-clock";
71 clock-frequency = <80000000>;
76 compatible = "simple-bus";
80 interrupt-parent = <&intc>;
83 compatible = "simple-bus";
88 serial0: serial@54006800 {
89 compatible = "socionext,uniphier-uart";
91 reg = <0x54006800 0x40>;
92 interrupts = <0 33 4>;
97 serial1: serial@54006900 {
98 compatible = "socionext,uniphier-uart";
100 reg = <0x54006900 0x40>;
101 interrupts = <0 35 4>;
102 clocks = <&uart_clk>;
106 serial2: serial@54006a00 {
107 compatible = "socionext,uniphier-uart";
109 reg = <0x54006a00 0x40>;
110 interrupts = <0 37 4>;
111 clocks = <&uart_clk>;
115 serial3: serial@54006b00 {
116 compatible = "socionext,uniphier-uart";
118 reg = <0x54006b00 0x40>;
119 interrupts = <0 29 4>;
120 clocks = <&uart_clk>;
124 system-bus-controller-misc@59800000 {
125 compatible = "socionext,uniphier-system-bus-controller-misc",
127 reg = <0x59800000 0x2000>;
131 compatible = "socionext,uniphier-ehci", "generic-ehci";
133 reg = <0x5a800100 0x100>;
134 interrupts = <0 80 4>;
138 compatible = "socionext,uniphier-ehci", "generic-ehci";
140 reg = <0x5a810100 0x100>;
141 interrupts = <0 81 4>;
145 compatible = "socionext,uniphier-ehci", "generic-ehci";
147 reg = <0x5a820100 0x100>;
148 interrupts = <0 82 4>;
152 compatible = "arm,cortex-a9-global-timer";
153 reg = <0x60000200 0x20>;
154 interrupts = <1 11 0x104>;
155 clocks = <&arm_timer_clk>;
159 compatible = "arm,cortex-a9-twd-timer";
160 reg = <0x60000600 0x20>;
161 interrupts = <1 13 0x104>;
162 clocks = <&arm_timer_clk>;
165 intc: interrupt-controller@60001000 {
166 compatible = "arm,cortex-a9-gic";
167 #interrupt-cells = <3>;
168 interrupt-controller;
169 reg = <0x60001000 0x1000>,