2 * Device Tree Source for UniPhier sLD3 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 compatible = "socionext,uniphier-sld3";
21 compatible = "arm,cortex-a9";
23 enable-method = "psci";
24 next-level-cache = <&l2>;
29 compatible = "arm,cortex-a9";
31 enable-method = "psci";
32 next-level-cache = <&l2>;
37 compatible = "arm,psci-0.2";
44 compatible = "fixed-clock";
45 clock-frequency = <24576000>;
48 arm_timer_clk: arm_timer_clk {
50 compatible = "fixed-clock";
51 clock-frequency = <50000000>;
56 compatible = "simple-bus";
60 interrupt-parent = <&intc>;
63 compatible = "arm,cortex-a9-global-timer";
64 reg = <0x20000200 0x20>;
65 interrupts = <1 11 0x304>;
66 clocks = <&arm_timer_clk>;
70 compatible = "arm,cortex-a9-twd-timer";
71 reg = <0x20000600 0x20>;
72 interrupts = <1 13 0x304>;
73 clocks = <&arm_timer_clk>;
76 intc: interrupt-controller@20001000 {
77 compatible = "arm,cortex-a9-gic";
78 #interrupt-cells = <3>;
80 reg = <0x20001000 0x1000>,
84 l2: l2-cache@500c0000 {
85 compatible = "socionext,uniphier-system-cache";
86 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
88 interrupts = <0 174 4>, <0 175 4>;
90 cache-size = <(512 * 1024)>;
92 cache-line-size = <128>;
96 serial0: serial@54006800 {
97 compatible = "socionext,uniphier-uart";
99 reg = <0x54006800 0x40>;
100 interrupts = <0 33 4>;
101 clocks = <&sys_clk 0>;
104 serial1: serial@54006900 {
105 compatible = "socionext,uniphier-uart";
107 reg = <0x54006900 0x40>;
108 interrupts = <0 35 4>;
109 clocks = <&sys_clk 0>;
112 serial2: serial@54006a00 {
113 compatible = "socionext,uniphier-uart";
115 reg = <0x54006a00 0x40>;
116 interrupts = <0 37 4>;
117 clocks = <&sys_clk 0>;
121 compatible = "socionext,uniphier-i2c";
123 reg = <0x58400000 0x40>;
124 #address-cells = <1>;
126 interrupts = <0 41 1>;
127 clocks = <&sys_clk 1>;
128 clock-frequency = <100000>;
132 compatible = "socionext,uniphier-i2c";
134 reg = <0x58480000 0x40>;
135 #address-cells = <1>;
137 interrupts = <0 42 1>;
138 clocks = <&sys_clk 1>;
139 clock-frequency = <100000>;
143 compatible = "socionext,uniphier-i2c";
145 reg = <0x58500000 0x40>;
146 #address-cells = <1>;
148 interrupts = <0 43 1>;
149 clocks = <&sys_clk 1>;
150 clock-frequency = <100000>;
154 compatible = "socionext,uniphier-i2c";
156 reg = <0x58580000 0x40>;
157 #address-cells = <1>;
159 interrupts = <0 44 1>;
160 clocks = <&sys_clk 1>;
161 clock-frequency = <100000>;
164 /* chip-internal connection for DMD */
166 compatible = "socionext,uniphier-i2c";
167 reg = <0x58600000 0x40>;
168 #address-cells = <1>;
170 interrupts = <0 45 1>;
171 clocks = <&sys_clk 1>;
172 clock-frequency = <400000>;
175 system_bus: system-bus@58c00000 {
176 compatible = "socionext,uniphier-system-bus";
178 reg = <0x58c00000 0x400>;
179 #address-cells = <2>;
184 compatible = "socionext,uniphier-smpctrl";
185 reg = <0x59801000 0x400>;
189 compatible = "socionext,uniphier-sld3-mioctrl",
190 "simple-mfd", "syscon";
191 reg = <0x59810000 0x800>;
194 compatible = "socionext,uniphier-sld3-mio-clock";
199 compatible = "socionext,uniphier-sld3-mio-reset";
205 compatible = "socionext,uniphier-ehci", "generic-ehci";
207 reg = <0x5a800100 0x100>;
208 interrupts = <0 80 4>;
209 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
210 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
215 compatible = "socionext,uniphier-ehci", "generic-ehci";
217 reg = <0x5a810100 0x100>;
218 interrupts = <0 81 4>;
219 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
220 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
225 compatible = "socionext,uniphier-ehci", "generic-ehci";
227 reg = <0x5a820100 0x100>;
228 interrupts = <0 82 4>;
229 clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
230 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
235 compatible = "socionext,uniphier-ehci", "generic-ehci";
237 reg = <0x5a830100 0x100>;
238 interrupts = <0 83 4>;
239 clocks = <&mio_clk 7>, <&mio_clk 11>, <&mio_clk 15>;
240 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 11>,
245 compatible = "socionext,uniphier-sld3-sysctrl",
246 "simple-mfd", "syscon";
247 reg = <0xf1840000 0x10000>;
250 compatible = "socionext,uniphier-sld3-clock";
255 compatible = "socionext,uniphier-sld3-reset";