arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts

   1 /*
   2  * ARM Ltd. Versatile Express
   3  *
   4  * CoreTile Express A15x2 A7x3
   5  * Cortex-A15_A7 MPCore (V2P-CA15_A7)
   6  *
   7  * HBI-0249A
   8  */
   9
  10 /dts-v1/;
  11
  12 / {
  13         model = "V2P-CA15_CA7";
  14         arm,hbi = <0x249>;
  15         arm,vexpress,site = <0xf>;
  16         compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
  17         interrupt-parent = <&gic>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         chosen { };
  22
  23         aliases {
  24                 serial0 = &v2m_serial0;
  25                 serial1 = &v2m_serial1;
  26                 serial2 = &v2m_serial2;
  27                 serial3 = &v2m_serial3;
  28                 i2c0 = &v2m_i2c_dvi;
  29                 i2c1 = &v2m_i2c_pcie;
  30         };
  31
  32         cpus {
  33                 #address-cells = <1>;
  34                 #size-cells = <0>;
  35
  36                 cpu0: cpu@0 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a15";
  39                         reg = <0>;
  40                         cci-control-port = <&cci_control1>;
  41                         cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
  42                 };
  43
  44                 cpu1: cpu@1 {
  45                         device_type = "cpu";
  46                         compatible = "arm,cortex-a15";
  47                         reg = <1>;
  48                         cci-control-port = <&cci_control1>;
  49                         cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
  50                 };
  51
  52                 cpu2: cpu@2 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a7";
  55                         reg = <0x100>;
  56                         cci-control-port = <&cci_control2>;
  57                         cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
  58                 };
  59
  60                 cpu3: cpu@3 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a7";
  63                         reg = <0x101>;
  64                         cci-control-port = <&cci_control2>;
  65                         cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
  66                 };
  67
  68                 cpu4: cpu@4 {
  69                         device_type = "cpu";
  70                         compatible = "arm,cortex-a7";
  71                         reg = <0x102>;
  72                         cci-control-port = <&cci_control2>;
  73                         cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
  74                 };
  75
  76                 idle-states {
  77                         CLUSTER_SLEEP_BIG: cluster-sleep-big {
  78                                 compatible = "arm,idle-state";
  79                                 local-timer-stop;
  80                                 entry-latency-us = <1000>;
  81                                 exit-latency-us = <700>;
  82                                 min-residency-us = <2000>;
  83                         };
  84
  85                         CLUSTER_SLEEP_LITTLE: cluster-sleep-little {
  86                                 compatible = "arm,idle-state";
  87                                 local-timer-stop;
  88                                 entry-latency-us = <1000>;
  89                                 exit-latency-us = <500>;
  90                                 min-residency-us = <2500>;
  91                         };
  92                 };
  93         };
  94
  95         memory@80000000 {
  96                 device_type = "memory";
  97                 reg = <0 0x80000000 0 0x40000000>;
  98         };
  99
 100         wdt@2a490000 {
 101                 compatible = "arm,sp805", "arm,primecell";
 102                 reg = <0 0x2a490000 0 0x1000>;
 103                 interrupts = <0 98 4>;
 104                 clocks = <&oscclk6a>, <&oscclk6a>;
 105                 clock-names = "wdogclk", "apb_pclk";
 106         };
 107
 108         hdlcd@2b000000 {
 109                 compatible = "arm,hdlcd";
 110                 reg = <0 0x2b000000 0 0x1000>;
 111                 interrupts = <0 85 4>;
 112                 clocks = <&oscclk5>;
 113                 clock-names = "pxlclk";
 114         };
 115
 116         memory-controller@2b0a0000 {
 117                 compatible = "arm,pl341", "arm,primecell";
 118                 reg = <0 0x2b0a0000 0 0x1000>;
 119                 clocks = <&oscclk6a>;
 120                 clock-names = "apb_pclk";
 121         };
 122
 123         gic: interrupt-controller@2c001000 {
 124                 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
 125                 #interrupt-cells = <3>;
 126                 #address-cells = <0>;
 127                 interrupt-controller;
 128                 reg = <0 0x2c001000 0 0x1000>,
 129                       <0 0x2c002000 0 0x1000>,
 130                       <0 0x2c004000 0 0x2000>,
 131                       <0 0x2c006000 0 0x2000>;
 132                 interrupts = <1 9 0xf04>;
 133         };
 134
 135         cci@2c090000 {
 136                 compatible = "arm,cci-400";
 137                 #address-cells = <1>;
 138                 #size-cells = <1>;
 139                 reg = <0 0x2c090000 0 0x1000>;
 140                 ranges = <0x0 0x0 0x2c090000 0x10000>;
 141
 142                 cci_control1: slave-if@4000 {
 143                         compatible = "arm,cci-400-ctrl-if";
 144                         interface-type = "ace";
 145                         reg = <0x4000 0x1000>;
 146                 };
 147
 148                 cci_control2: slave-if@5000 {
 149                         compatible = "arm,cci-400-ctrl-if";
 150                         interface-type = "ace";
 151                         reg = <0x5000 0x1000>;
 152                 };
 153         };
 154
 155         memory-controller@7ffd0000 {
 156                 compatible = "arm,pl354", "arm,primecell";
 157                 reg = <0 0x7ffd0000 0 0x1000>;
 158                 interrupts = <0 86 4>,
 159                              <0 87 4>;
 160                 clocks = <&oscclk6a>;
 161                 clock-names = "apb_pclk";
 162         };
 163
 164         dma@7ff00000 {
 165                 compatible = "arm,pl330", "arm,primecell";
 166                 reg = <0 0x7ff00000 0 0x1000>;
 167                 interrupts = <0 92 4>,
 168                              <0 88 4>,
 169                              <0 89 4>,
 170                              <0 90 4>,
 171                              <0 91 4>;
 172                 clocks = <&oscclk6a>;
 173                 clock-names = "apb_pclk";
 174         };
 175
 176         scc@7fff0000 {
 177                 compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
 178                 reg = <0 0x7fff0000 0 0x1000>;
 179                 interrupts = <0 95 4>;
 180         };
 181
 182         timer {
 183                 compatible = "arm,armv7-timer";
 184                 interrupts = <1 13 0xf08>,
 185                              <1 14 0xf08>,
 186                              <1 11 0xf08>,
 187                              <1 10 0xf08>;
 188         };
 189
 190         pmu_a15 {
 191                 compatible = "arm,cortex-a15-pmu";
 192                 interrupts = <0 68 4>,
 193                              <0 69 4>;
 194                 interrupt-affinity = <&cpu0>,
 195                                      <&cpu1>;
 196         };
 197
 198         pmu_a7 {
 199                 compatible = "arm,cortex-a7-pmu";
 200                 interrupts = <0 128 4>,
 201                              <0 129 4>,
 202                              <0 130 4>;
 203                 interrupt-affinity = <&cpu2>,
 204                                      <&cpu3>,
 205                                      <&cpu4>;
 206         };
 207
 208         oscclk6a: oscclk6a {
 209                 /* Reference 24MHz clock */
 210                 compatible = "fixed-clock";
 211                 #clock-cells = <0>;
 212                 clock-frequency = <24000000>;
 213                 clock-output-names = "oscclk6a";
 214         };
 215
 216         dcc {
 217                 compatible = "arm,vexpress,config-bus";
 218                 arm,vexpress,config-bridge = <&v2m_sysreg>;
 219
 220                 osc@0 {
 221                         /* A15 PLL 0 reference clock */
 222                         compatible = "arm,vexpress-osc";
 223                         arm,vexpress-sysreg,func = <1 0>;
 224                         freq-range = <17000000 50000000>;
 225                         #clock-cells = <0>;
 226                         clock-output-names = "oscclk0";
 227                 };
 228
 229                 osc@1 {
 230                         /* A15 PLL 1 reference clock */
 231                         compatible = "arm,vexpress-osc";
 232                         arm,vexpress-sysreg,func = <1 1>;
 233                         freq-range = <17000000 50000000>;
 234                         #clock-cells = <0>;
 235                         clock-output-names = "oscclk1";
 236                 };
 237
 238                 osc@2 {
 239                         /* A7 PLL 0 reference clock */
 240                         compatible = "arm,vexpress-osc";
 241                         arm,vexpress-sysreg,func = <1 2>;
 242                         freq-range = <17000000 50000000>;
 243                         #clock-cells = <0>;
 244                         clock-output-names = "oscclk2";
 245                 };
 246
 247                 osc@3 {
 248                         /* A7 PLL 1 reference clock */
 249                         compatible = "arm,vexpress-osc";
 250                         arm,vexpress-sysreg,func = <1 3>;
 251                         freq-range = <17000000 50000000>;
 252                         #clock-cells = <0>;
 253                         clock-output-names = "oscclk3";
 254                 };
 255
 256                 osc@4 {
 257                         /* External AXI master clock */
 258                         compatible = "arm,vexpress-osc";
 259                         arm,vexpress-sysreg,func = <1 4>;
 260                         freq-range = <20000000 40000000>;
 261                         #clock-cells = <0>;
 262                         clock-output-names = "oscclk4";
 263                 };
 264
 265                 oscclk5: osc@5 {
 266                         /* HDLCD PLL reference clock */
 267                         compatible = "arm,vexpress-osc";
 268                         arm,vexpress-sysreg,func = <1 5>;
 269                         freq-range = <23750000 165000000>;
 270                         #clock-cells = <0>;
 271                         clock-output-names = "oscclk5";
 272                 };
 273
 274                 smbclk: osc@6 {
 275                         /* Static memory controller clock */
 276                         compatible = "arm,vexpress-osc";
 277                         arm,vexpress-sysreg,func = <1 6>;
 278                         freq-range = <20000000 40000000>;
 279                         #clock-cells = <0>;
 280                         clock-output-names = "oscclk6";
 281                 };
 282
 283                 osc@7 {
 284                         /* SYS PLL reference clock */
 285                         compatible = "arm,vexpress-osc";
 286                         arm,vexpress-sysreg,func = <1 7>;
 287                         freq-range = <17000000 50000000>;
 288                         #clock-cells = <0>;
 289                         clock-output-names = "oscclk7";
 290                 };
 291
 292                 osc@8 {
 293                         /* DDR2 PLL reference clock */
 294                         compatible = "arm,vexpress-osc";
 295                         arm,vexpress-sysreg,func = <1 8>;
 296                         freq-range = <20000000 50000000>;
 297                         #clock-cells = <0>;
 298                         clock-output-names = "oscclk8";
 299                 };
 300
 301                 volt@0 {
 302                         /* A15 CPU core voltage */
 303                         compatible = "arm,vexpress-volt";
 304                         arm,vexpress-sysreg,func = <2 0>;
 305                         regulator-name = "A15 Vcore";
 306                         regulator-min-microvolt = <800000>;
 307                         regulator-max-microvolt = <1050000>;
 308                         regulator-always-on;
 309                         label = "A15 Vcore";
 310                 };
 311
 312                 volt@1 {
 313                         /* A7 CPU core voltage */
 314                         compatible = "arm,vexpress-volt";
 315                         arm,vexpress-sysreg,func = <2 1>;
 316                         regulator-name = "A7 Vcore";
 317                         regulator-min-microvolt = <800000>;
 318                         regulator-max-microvolt = <1050000>;
 319                         regulator-always-on;
 320                         label = "A7 Vcore";
 321                 };
 322
 323                 amp@0 {
 324                         /* Total current for the two A15 cores */
 325                         compatible = "arm,vexpress-amp";
 326                         arm,vexpress-sysreg,func = <3 0>;
 327                         label = "A15 Icore";
 328                 };
 329
 330                 amp@1 {
 331                         /* Total current for the three A7 cores */
 332                         compatible = "arm,vexpress-amp";
 333                         arm,vexpress-sysreg,func = <3 1>;
 334                         label = "A7 Icore";
 335                 };
 336
 337                 temp@0 {
 338                         /* DCC internal temperature */
 339                         compatible = "arm,vexpress-temp";
 340                         arm,vexpress-sysreg,func = <4 0>;
 341                         label = "DCC";
 342                 };
 343
 344                 power@0 {
 345                         /* Total power for the two A15 cores */
 346                         compatible = "arm,vexpress-power";
 347                         arm,vexpress-sysreg,func = <12 0>;
 348                         label = "A15 Pcore";
 349                 };
 350
 351                 power@1 {
 352                         /* Total power for the three A7 cores */
 353                         compatible = "arm,vexpress-power";
 354                         arm,vexpress-sysreg,func = <12 1>;
 355                         label = "A7 Pcore";
 356                 };
 357
 358                 energy@0 {
 359                         /* Total energy for the two A15 cores */
 360                         compatible = "arm,vexpress-energy";
 361                         arm,vexpress-sysreg,func = <13 0>, <13 1>;
 362                         label = "A15 Jcore";
 363                 };
 364
 365                 energy@2 {
 366                         /* Total energy for the three A7 cores */
 367                         compatible = "arm,vexpress-energy";
 368                         arm,vexpress-sysreg,func = <13 2>, <13 3>;
 369                         label = "A7 Jcore";
 370                 };
 371         };
 372
 373         etb@0,20010000 {
 374                 compatible = "arm,coresight-etb10", "arm,primecell";
 375                 reg = <0 0x20010000 0 0x1000>;
 376
 377                 clocks = <&oscclk6a>;
 378                 clock-names = "apb_pclk";
 379                 port {
 380                         etb_in_port: endpoint@0 {
 381                                 slave-mode;
 382                                 remote-endpoint = <&replicator_out_port0>;
 383                         };
 384                 };
 385         };
 386
 387         tpiu@0,20030000 {
 388                 compatible = "arm,coresight-tpiu", "arm,primecell";
 389                 reg = <0 0x20030000 0 0x1000>;
 390
 391                 clocks = <&oscclk6a>;
 392                 clock-names = "apb_pclk";
 393                 port {
 394                         tpiu_in_port: endpoint@0 {
 395                                 slave-mode;
 396                                 remote-endpoint = <&replicator_out_port1>;
 397                         };
 398                 };
 399         };
 400
 401         replicator {
 402                 /* non-configurable replicators don't show up on the
 403                  * AMBA bus.  As such no need to add "arm,primecell".
 404                  */
 405                 compatible = "arm,coresight-replicator";
 406
 407                 ports {
 408                         #address-cells = <1>;
 409                         #size-cells = <0>;
 410
 411                         /* replicator output ports */
 412                         port@0 {
 413                                 reg = <0>;
 414                                 replicator_out_port0: endpoint {
 415                                         remote-endpoint = <&etb_in_port>;
 416                                 };
 417                         };
 418
 419                         port@1 {
 420                                 reg = <1>;
 421                                 replicator_out_port1: endpoint {
 422                                         remote-endpoint = <&tpiu_in_port>;
 423                                 };
 424                         };
 425
 426                         /* replicator input port */
 427                         port@2 {
 428                                 reg = <0>;
 429                                 replicator_in_port0: endpoint {
 430                                         slave-mode;
 431                                         remote-endpoint = <&funnel_out_port0>;
 432                                 };
 433                         };
 434                 };
 435         };
 436
 437         funnel@0,20040000 {
 438                 compatible = "arm,coresight-funnel", "arm,primecell";
 439                 reg = <0 0x20040000 0 0x1000>;
 440
 441                 clocks = <&oscclk6a>;
 442                 clock-names = "apb_pclk";
 443                 ports {
 444                         #address-cells = <1>;
 445                         #size-cells = <0>;
 446
 447                         /* funnel output port */
 448                         port@0 {
 449                                 reg = <0>;
 450                                 funnel_out_port0: endpoint {
 451                                         remote-endpoint =
 452                                                 <&replicator_in_port0>;
 453                                 };
 454                         };
 455
 456                         /* funnel input ports */
 457                         port@1 {
 458                                 reg = <0>;
 459                                 funnel_in_port0: endpoint {
 460                                         slave-mode;
 461                                         remote-endpoint = <&ptm0_out_port>;
 462                                 };
 463                         };
 464
 465                         port@2 {
 466                                 reg = <1>;
 467                                 funnel_in_port1: endpoint {
 468                                         slave-mode;
 469                                         remote-endpoint = <&ptm1_out_port>;
 470                                 };
 471                         };
 472
 473                         port@3 {
 474                                 reg = <2>;
 475                                 funnel_in_port2: endpoint {
 476                                         slave-mode;
 477                                         remote-endpoint = <&etm0_out_port>;
 478                                 };
 479                         };
 480
 481                         /* Input port #3 is for ITM, not supported here */
 482
 483                         port@4 {
 484                                 reg = <4>;
 485                                 funnel_in_port4: endpoint {
 486                                         slave-mode;
 487                                         remote-endpoint = <&etm1_out_port>;
 488                                 };
 489                         };
 490
 491                         port@5 {
 492                                 reg = <5>;
 493                                 funnel_in_port5: endpoint {
 494                                         slave-mode;
 495                                         remote-endpoint = <&etm2_out_port>;
 496                                 };
 497                         };
 498                 };
 499         };
 500
 501         ptm@0,2201c000 {
 502                 compatible = "arm,coresight-etm3x", "arm,primecell";
 503                 reg = <0 0x2201c000 0 0x1000>;
 504
 505                 cpu = <&cpu0>;
 506                 clocks = <&oscclk6a>;
 507                 clock-names = "apb_pclk";
 508                 port {
 509                         ptm0_out_port: endpoint {
 510                                 remote-endpoint = <&funnel_in_port0>;
 511                         };
 512                 };
 513         };
 514
 515         ptm@0,2201d000 {
 516                 compatible = "arm,coresight-etm3x", "arm,primecell";
 517                 reg = <0 0x2201d000 0 0x1000>;
 518
 519                 cpu = <&cpu1>;
 520                 clocks = <&oscclk6a>;
 521                 clock-names = "apb_pclk";
 522                 port {
 523                         ptm1_out_port: endpoint {
 524                                 remote-endpoint = <&funnel_in_port1>;
 525                         };
 526                 };
 527         };
 528
 529         etm@0,2203c000 {
 530                 compatible = "arm,coresight-etm3x", "arm,primecell";
 531                 reg = <0 0x2203c000 0 0x1000>;
 532
 533                 cpu = <&cpu2>;
 534                 clocks = <&oscclk6a>;
 535                 clock-names = "apb_pclk";
 536                 port {
 537                         etm0_out_port: endpoint {
 538                                 remote-endpoint = <&funnel_in_port2>;
 539                         };
 540                 };
 541         };
 542
 543         etm@0,2203d000 {
 544                 compatible = "arm,coresight-etm3x", "arm,primecell";
 545                 reg = <0 0x2203d000 0 0x1000>;
 546
 547                 cpu = <&cpu3>;
 548                 clocks = <&oscclk6a>;
 549                 clock-names = "apb_pclk";
 550                 port {
 551                         etm1_out_port: endpoint {
 552                                 remote-endpoint = <&funnel_in_port4>;
 553                         };
 554                 };
 555         };
 556
 557         etm@0,2203e000 {
 558                 compatible = "arm,coresight-etm3x", "arm,primecell";
 559                 reg = <0 0x2203e000 0 0x1000>;
 560
 561                 cpu = <&cpu4>;
 562                 clocks = <&oscclk6a>;
 563                 clock-names = "apb_pclk";
 564                 port {
 565                         etm2_out_port: endpoint {
 566                                 remote-endpoint = <&funnel_in_port5>;
 567                         };
 568                 };
 569         };
 570
 571         smb {
 572                 compatible = "simple-bus";
 573
 574                 #address-cells = <2>;
 575                 #size-cells = <1>;
 576                 ranges = <0 0 0 0x08000000 0x04000000>,
 577                          <1 0 0 0x14000000 0x04000000>,
 578                          <2 0 0 0x18000000 0x04000000>,
 579                          <3 0 0 0x1c000000 0x04000000>,
 580                          <4 0 0 0x0c000000 0x04000000>,
 581                          <5 0 0 0x10000000 0x04000000>;
 582
 583                 #interrupt-cells = <1>;
 584                 interrupt-map-mask = <0 0 63>;
 585                 interrupt-map = <0 0  0 &gic 0  0 4>,
 586                                 <0 0  1 &gic 0  1 4>,
 587                                 <0 0  2 &gic 0  2 4>,
 588                                 <0 0  3 &gic 0  3 4>,
 589                                 <0 0  4 &gic 0  4 4>,
 590                                 <0 0  5 &gic 0  5 4>,
 591                                 <0 0  6 &gic 0  6 4>,
 592                                 <0 0  7 &gic 0  7 4>,
 593                                 <0 0  8 &gic 0  8 4>,
 594                                 <0 0  9 &gic 0  9 4>,
 595                                 <0 0 10 &gic 0 10 4>,
 596                                 <0 0 11 &gic 0 11 4>,
 597                                 <0 0 12 &gic 0 12 4>,
 598                                 <0 0 13 &gic 0 13 4>,
 599                                 <0 0 14 &gic 0 14 4>,
 600                                 <0 0 15 &gic 0 15 4>,
 601                                 <0 0 16 &gic 0 16 4>,
 602                                 <0 0 17 &gic 0 17 4>,
 603                                 <0 0 18 &gic 0 18 4>,
 604                                 <0 0 19 &gic 0 19 4>,
 605                                 <0 0 20 &gic 0 20 4>,
 606                                 <0 0 21 &gic 0 21 4>,
 607                                 <0 0 22 &gic 0 22 4>,
 608                                 <0 0 23 &gic 0 23 4>,
 609                                 <0 0 24 &gic 0 24 4>,
 610                                 <0 0 25 &gic 0 25 4>,
 611                                 <0 0 26 &gic 0 26 4>,
 612                                 <0 0 27 &gic 0 27 4>,
 613                                 <0 0 28 &gic 0 28 4>,
 614                                 <0 0 29 &gic 0 29 4>,
 615                                 <0 0 30 &gic 0 30 4>,
 616                                 <0 0 31 &gic 0 31 4>,
 617                                 <0 0 32 &gic 0 32 4>,
 618                                 <0 0 33 &gic 0 33 4>,
 619                                 <0 0 34 &gic 0 34 4>,
 620                                 <0 0 35 &gic 0 35 4>,
 621                                 <0 0 36 &gic 0 36 4>,
 622                                 <0 0 37 &gic 0 37 4>,
 623                                 <0 0 38 &gic 0 38 4>,
 624                                 <0 0 39 &gic 0 39 4>,
 625                                 <0 0 40 &gic 0 40 4>,
 626                                 <0 0 41 &gic 0 41 4>,
 627                                 <0 0 42 &gic 0 42 4>;
 628
 629                 /include/ "vexpress-v2m-rs1.dtsi"
 630         };
 631 };