arch/arm/boot/dts/vf610-twr.dts

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License
  11  *     version 2 as published by the Free Software Foundation.
  12  *
  13  *     This file is distributed in the hope that it will be useful
  14  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *     GNU General Public License for more details.
  17  *
  18  * Or, alternatively
  19  *
  20  *  b) Permission is hereby granted, free of charge, to any person
  21  *     obtaining a copy of this software and associated documentation
  22  *     files (the "Software"), to deal in the Software without
  23  *     restriction, including without limitation the rights to use
  24  *     copy, modify, merge, publish, distribute, sublicense, and/or
  25  *     sell copies of the Software, and to permit persons to whom the
  26  *     Software is furnished to do so, subject to the following
  27  *     conditions:
  28  *
  29  *     The above copyright notice and this permission notice shall be
  30  *     included in all copies or substantial portions of the Software.
  31  *
  32  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
  33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
  37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  39  *     OTHER DEALINGS IN THE SOFTWARE.
  40  */
  41
  42 /dts-v1/;
  43 #include "vf610.dtsi"
  44
  45 / {
  46         model = "VF610 Tower Board";
  47         compatible = "fsl,vf610-twr", "fsl,vf610";
  48
  49         chosen {
  50                 bootargs = "console=ttyLP1,115200";
  51         };
  52
  53         memory {
  54                 reg = <0x80000000 0x8000000>;
  55         };
  56
  57         audio_ext: mclk_osc {
  58                 compatible = "fixed-clock";
  59                 #clock-cells = <0>;
  60                 clock-frequency = <24576000>;
  61         };
  62
  63         enet_ext: eth_osc {
  64                 compatible = "fixed-clock";
  65                 #clock-cells = <0>;
  66                 clock-frequency = <50000000>;
  67         };
  68
  69         regulators {
  70                 compatible = "simple-bus";
  71                 #address-cells = <1>;
  72                 #size-cells = <0>;
  73
  74                 reg_3p3v: regulator@0 {
  75                         compatible = "regulator-fixed";
  76                         reg = <0>;
  77                         regulator-name = "3P3V";
  78                         regulator-min-microvolt = <3300000>;
  79                         regulator-max-microvolt = <3300000>;
  80                         regulator-always-on;
  81                 };
  82
  83                 reg_vcc_3v3_mcu: regulator@1 {
  84                         compatible = "regulator-fixed";
  85                         reg = <1>;
  86                         regulator-name = "vcc_3v3_mcu";
  87                         regulator-min-microvolt = <3300000>;
  88                         regulator-max-microvolt = <3300000>;
  89                 };
  90         };
  91
  92         sound {
  93                 compatible = "simple-audio-card";
  94                 simple-audio-card,format = "i2s";
  95                 simple-audio-card,widgets =
  96                         "Microphone", "Microphone Jack",
  97                         "Headphone", "Headphone Jack",
  98                         "Speaker", "Speaker Ext",
  99                         "Line", "Line In Jack";
 100                 simple-audio-card,routing =
 101                         "MIC_IN", "Microphone Jack",
 102                         "Microphone Jack", "Mic Bias",
 103                         "LINE_IN", "Line In Jack",
 104                         "Headphone Jack", "HP_OUT",
 105                         "Speaker Ext", "LINE_OUT";
 106
 107                 simple-audio-card,cpu {
 108                         sound-dai = <&sai2>;
 109                         frame-master;
 110                         bitclock-master;
 111                 };
 112
 113                 simple-audio-card,codec {
 114                         sound-dai = <&codec>;
 115                         frame-master;
 116                         bitclock-master;
 117                 };
 118         };
 119 };
 120
 121 &adc0 {
 122         pinctrl-names = "default";
 123         pinctrl-0 = <&pinctrl_adc0_ad5>;
 124         vref-supply = <&reg_vcc_3v3_mcu>;
 125         status = "okay";
 126 };
 127
 128 &clks {
 129         clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>;
 130         clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext";
 131 };
 132
 133 &dspi0 {
 134         bus-num = <0>;
 135         pinctrl-names = "default";
 136         pinctrl-0 = <&pinctrl_dspi0>;
 137         status = "okay";
 138
 139         sflash: at26df081a@0 {
 140                 #address-cells = <1>;
 141                 #size-cells = <1>;
 142                 compatible = "atmel,at26df081a";
 143                 spi-max-frequency = <16000000>;
 144                 spi-cpol;
 145                 spi-cpha;
 146                 reg = <0>;
 147         };
 148 };
 149
 150 &edma0 {
 151         status = "okay";
 152 };
 153
 154 &esdhc1 {
 155         pinctrl-names = "default";
 156         pinctrl-0 = <&pinctrl_esdhc1>;
 157         bus-width = <4>;
 158         cd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
 159         status = "okay";
 160 };
 161
 162 &fec0 {
 163         phy-mode = "rmii";
 164         phy-handle = <&ethphy0>;
 165         pinctrl-names = "default";
 166         pinctrl-0 = <&pinctrl_fec0>;
 167         status = "okay";
 168
 169         mdio {
 170                 #address-cells = <1>;
 171                 #size-cells = <0>;
 172
 173                 ethphy0: ethernet-phy@0 {
 174                         reg = <0>;
 175                 };
 176
 177                 ethphy1: ethernet-phy@1 {
 178                         reg = <1>;
 179                 };
 180         };
 181 };
 182
 183 &fec1 {
 184         phy-mode = "rmii";
 185         phy-handle = <&ethphy1>;
 186         pinctrl-names = "default";
 187         pinctrl-0 = <&pinctrl_fec1>;
 188         status = "okay";
 189 };
 190
 191 &i2c0 {
 192         clock-frequency = <100000>;
 193         pinctrl-names = "default";
 194         pinctrl-0 = <&pinctrl_i2c0>;
 195         status = "okay";
 196
 197         codec: sgtl5000@0a {
 198                #sound-dai-cells = <0>;
 199                compatible = "fsl,sgtl5000";
 200                reg = <0x0a>;
 201                VDDA-supply = <&reg_3p3v>;
 202                VDDIO-supply = <&reg_3p3v>;
 203                clocks = <&clks VF610_CLK_SAI2>;
 204        };
 205 };
 206
 207 &iomuxc {
 208         vf610-twr {
 209                 pinctrl_adc0_ad5: adc0ad5grp {
 210                         fsl,pins = <
 211                                 VF610_PAD_PTC30__ADC0_SE5               0xa1
 212                         >;
 213                 };
 214
 215                 pinctrl_dspi0: dspi0grp {
 216                         fsl,pins = <
 217                                 VF610_PAD_PTB19__DSPI0_CS0              0x1182
 218                                 VF610_PAD_PTB20__DSPI0_SIN              0x1181
 219                                 VF610_PAD_PTB21__DSPI0_SOUT             0x1182
 220                                 VF610_PAD_PTB22__DSPI0_SCK              0x1182
 221                         >;
 222                 };
 223
 224                 pinctrl_esdhc1: esdhc1grp {
 225                         fsl,pins = <
 226                                 VF610_PAD_PTA24__ESDHC1_CLK     0x31ef
 227                                 VF610_PAD_PTA25__ESDHC1_CMD     0x31ef
 228                                 VF610_PAD_PTA26__ESDHC1_DAT0    0x31ef
 229                                 VF610_PAD_PTA27__ESDHC1_DAT1    0x31ef
 230                                 VF610_PAD_PTA28__ESDHC1_DATA2   0x31ef
 231                                 VF610_PAD_PTA29__ESDHC1_DAT3    0x31ef
 232                                 VF610_PAD_PTA7__GPIO_134        0x219d
 233                         >;
 234                 };
 235
 236                 pinctrl_fec0: fec0grp {
 237                         fsl,pins = <
 238                                 VF610_PAD_PTA6__RMII_CLKIN              0x30d1
 239                                 VF610_PAD_PTC0__ENET_RMII0_MDC          0x30d3
 240                                 VF610_PAD_PTC1__ENET_RMII0_MDIO         0x30d1
 241                                 VF610_PAD_PTC2__ENET_RMII0_CRS          0x30d1
 242                                 VF610_PAD_PTC3__ENET_RMII0_RXD1         0x30d1
 243                                 VF610_PAD_PTC4__ENET_RMII0_RXD0         0x30d1
 244                                 VF610_PAD_PTC5__ENET_RMII0_RXER         0x30d1
 245                                 VF610_PAD_PTC6__ENET_RMII0_TXD1         0x30d2
 246                                 VF610_PAD_PTC7__ENET_RMII0_TXD0         0x30d2
 247                                 VF610_PAD_PTC8__ENET_RMII0_TXEN         0x30d2
 248                         >;
 249                 };
 250
 251                 pinctrl_fec1: fec1grp {
 252                         fsl,pins = <
 253                                 VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
 254                                 VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
 255                                 VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
 256                                 VF610_PAD_PTC12__ENET_RMII1_RXD1        0x30d1
 257                                 VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
 258                                 VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
 259                                 VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
 260                                 VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
 261                                 VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
 262                         >;
 263                 };
 264
 265                 pinctrl_i2c0: i2c0grp {
 266                         fsl,pins = <
 267                                 VF610_PAD_PTB14__I2C0_SCL               0x30d3
 268                                 VF610_PAD_PTB15__I2C0_SDA               0x30d3
 269                         >;
 270                 };
 271
 272                 pinctrl_nfc: nfcgrp {
 273                         fsl,pins = <
 274                                 VF610_PAD_PTD31__NF_IO15        0x28df
 275                                 VF610_PAD_PTD30__NF_IO14        0x28df
 276                                 VF610_PAD_PTD29__NF_IO13        0x28df
 277                                 VF610_PAD_PTD28__NF_IO12        0x28df
 278                                 VF610_PAD_PTD27__NF_IO11        0x28df
 279                                 VF610_PAD_PTD26__NF_IO10        0x28df
 280                                 VF610_PAD_PTD25__NF_IO9         0x28df
 281                                 VF610_PAD_PTD24__NF_IO8         0x28df
 282                                 VF610_PAD_PTD23__NF_IO7         0x28df
 283                                 VF610_PAD_PTD22__NF_IO6         0x28df
 284                                 VF610_PAD_PTD21__NF_IO5         0x28df
 285                                 VF610_PAD_PTD20__NF_IO4         0x28df
 286                                 VF610_PAD_PTD19__NF_IO3         0x28df
 287                                 VF610_PAD_PTD18__NF_IO2         0x28df
 288                                 VF610_PAD_PTD17__NF_IO1         0x28df
 289                                 VF610_PAD_PTD16__NF_IO0         0x28df
 290                                 VF610_PAD_PTB24__NF_WE_B        0x28c2
 291                                 VF610_PAD_PTB25__NF_CE0_B       0x28c2
 292                                 VF610_PAD_PTB27__NF_RE_B        0x28c2
 293                                 VF610_PAD_PTC26__NF_RB_B        0x283d
 294                                 VF610_PAD_PTC27__NF_ALE         0x28c2
 295                                 VF610_PAD_PTC28__NF_CLE         0x28c2
 296                         >;
 297                 };
 298
 299                 pinctrl_pwm0: pwm0grp {
 300                         fsl,pins = <
 301                                 VF610_PAD_PTB0__FTM0_CH0                0x1582
 302                                 VF610_PAD_PTB1__FTM0_CH1                0x1582
 303                                 VF610_PAD_PTB2__FTM0_CH2                0x1582
 304                                 VF610_PAD_PTB3__FTM0_CH3                0x1582
 305                         >;
 306                 };
 307
 308                 pinctrl_sai2: sai2grp {
 309                         fsl,pins = <
 310                                 VF610_PAD_PTA16__SAI2_TX_BCLK           0x02ed
 311                                 VF610_PAD_PTA18__SAI2_TX_DATA           0x02ee
 312                                 VF610_PAD_PTA19__SAI2_TX_SYNC           0x02ed
 313                                 VF610_PAD_PTA21__SAI2_RX_BCLK           0x02ed
 314                                 VF610_PAD_PTA22__SAI2_RX_DATA           0x02ed
 315                                 VF610_PAD_PTA23__SAI2_RX_SYNC           0x02ed
 316                                 VF610_PAD_PTB18__EXT_AUDIO_MCLK         0x02ed
 317                         >;
 318                 };
 319
 320                 pinctrl_uart1: uart1grp {
 321                         fsl,pins = <
 322                                 VF610_PAD_PTB4__UART1_TX                0x21a2
 323                                 VF610_PAD_PTB5__UART1_RX                0x21a1
 324                         >;
 325                 };
 326
 327                 pinctrl_uart2: uart2grp {
 328                         fsl,pins = <
 329                                 VF610_PAD_PTB6__UART2_TX                0x21a2
 330                                 VF610_PAD_PTB7__UART2_RX                0x21a1
 331                         >;
 332                 };
 333         };
 334 };
 335
 336 &nfc {
 337         assigned-clocks = <&clks VF610_CLK_NFC>;
 338         assigned-clock-rates = <33000000>;
 339         pinctrl-names = "default";
 340         pinctrl-0 = <&pinctrl_nfc>;
 341         status = "okay";
 342
 343         nand@0 {
 344                 compatible = "fsl,vf610-nfc-nandcs";
 345                 reg = <0>;
 346                 #address-cells = <1>;
 347                 #size-cells = <1>;
 348                 nand-bus-width = <16>;
 349                 nand-ecc-mode = "hw";
 350                 nand-ecc-strength = <24>;
 351                 nand-ecc-step-size = <2048>;
 352                 nand-on-flash-bbt;
 353         };
 354 };
 355
 356 &pwm0 {
 357         pinctrl-names = "default";
 358         pinctrl-0 = <&pinctrl_pwm0>;
 359         status = "okay";
 360 };
 361
 362 &sai2 {
 363         #sound-dai-cells = <0>;
 364         pinctrl-names = "default";
 365         pinctrl-0 = <&pinctrl_sai2>;
 366         status = "okay";
 367 };
 368
 369 &uart1 {
 370         pinctrl-names = "default";
 371         pinctrl-0 = <&pinctrl_uart1>;
 372         status = "okay";
 373 };
 374
 375 &uart2 {
 376         pinctrl-names = "default";
 377         pinctrl-0 = <&pinctrl_uart2>;
 378         status = "okay";
 379 };
 380
 381 &usbdev0 {
 382         disable-over-current;
 383         status = "okay";
 384 };
 385
 386 &usbh1 {
 387         disable-over-current;
 388         status = "okay";
 389 };
 390
 391 &usbmisc0 {
 392         status = "okay";
 393 };
 394
 395 &usbmisc1 {
 396         status = "okay";
 397 };
 398
 399 &usbphy0 {
 400         status = "okay";
 401 };
 402
 403 &usbphy1 {
 404         status = "okay";
 405 };