2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
32 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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39 * OTHER DEALINGS IN THE SOFTWARE.
46 model = "VF610 Tower Board";
47 compatible = "fsl,vf610-twr", "fsl,vf610";
50 bootargs = "console=ttyLP1,115200";
54 reg = <0x80000000 0x8000000>;
58 compatible = "fixed-clock";
60 clock-frequency = <24576000>;
64 compatible = "fixed-clock";
66 clock-frequency = <50000000>;
70 compatible = "simple-bus";
74 reg_3p3v: regulator@0 {
75 compatible = "regulator-fixed";
77 regulator-name = "3P3V";
78 regulator-min-microvolt = <3300000>;
79 regulator-max-microvolt = <3300000>;
83 reg_vcc_3v3_mcu: regulator@1 {
84 compatible = "regulator-fixed";
86 regulator-name = "vcc_3v3_mcu";
87 regulator-min-microvolt = <3300000>;
88 regulator-max-microvolt = <3300000>;
93 compatible = "simple-audio-card";
94 simple-audio-card,format = "i2s";
95 simple-audio-card,widgets =
96 "Microphone", "Microphone Jack",
97 "Headphone", "Headphone Jack",
98 "Speaker", "Speaker Ext",
99 "Line", "Line In Jack";
100 simple-audio-card,routing =
101 "MIC_IN", "Microphone Jack",
102 "Microphone Jack", "Mic Bias",
103 "LINE_IN", "Line In Jack",
104 "Headphone Jack", "HP_OUT",
105 "Speaker Ext", "LINE_OUT";
107 simple-audio-card,cpu {
113 simple-audio-card,codec {
114 sound-dai = <&codec>;
122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_adc0_ad5>;
124 vref-supply = <®_vcc_3v3_mcu>;
129 clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>;
130 clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext";
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_dspi0>;
139 sflash: at26df081a@0 {
140 #address-cells = <1>;
142 compatible = "atmel,at26df081a";
143 spi-max-frequency = <16000000>;
155 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_esdhc1>;
158 cd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
164 phy-handle = <ðphy0>;
165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_fec0>;
170 #address-cells = <1>;
173 ethphy0: ethernet-phy@0 {
177 ethphy1: ethernet-phy@1 {
185 phy-handle = <ðphy1>;
186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_fec1>;
192 clock-frequency = <100000>;
193 pinctrl-names = "default";
194 pinctrl-0 = <&pinctrl_i2c0>;
198 #sound-dai-cells = <0>;
199 compatible = "fsl,sgtl5000";
201 VDDA-supply = <®_3p3v>;
202 VDDIO-supply = <®_3p3v>;
203 clocks = <&clks VF610_CLK_SAI2>;
209 pinctrl_adc0_ad5: adc0ad5grp {
211 VF610_PAD_PTC30__ADC0_SE5 0xa1
215 pinctrl_dspi0: dspi0grp {
217 VF610_PAD_PTB19__DSPI0_CS0 0x1182
218 VF610_PAD_PTB20__DSPI0_SIN 0x1181
219 VF610_PAD_PTB21__DSPI0_SOUT 0x1182
220 VF610_PAD_PTB22__DSPI0_SCK 0x1182
224 pinctrl_esdhc1: esdhc1grp {
226 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
227 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
228 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
229 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
230 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
231 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
232 VF610_PAD_PTA7__GPIO_134 0x219d
236 pinctrl_fec0: fec0grp {
238 VF610_PAD_PTA6__RMII_CLKIN 0x30d1
239 VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d3
240 VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1
241 VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1
242 VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1
243 VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1
244 VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1
245 VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2
246 VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2
247 VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2
251 pinctrl_fec1: fec1grp {
253 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
254 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
255 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
256 VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
257 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
258 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
259 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
260 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
261 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
265 pinctrl_i2c0: i2c0grp {
267 VF610_PAD_PTB14__I2C0_SCL 0x30d3
268 VF610_PAD_PTB15__I2C0_SDA 0x30d3
272 pinctrl_nfc: nfcgrp {
274 VF610_PAD_PTD31__NF_IO15 0x28df
275 VF610_PAD_PTD30__NF_IO14 0x28df
276 VF610_PAD_PTD29__NF_IO13 0x28df
277 VF610_PAD_PTD28__NF_IO12 0x28df
278 VF610_PAD_PTD27__NF_IO11 0x28df
279 VF610_PAD_PTD26__NF_IO10 0x28df
280 VF610_PAD_PTD25__NF_IO9 0x28df
281 VF610_PAD_PTD24__NF_IO8 0x28df
282 VF610_PAD_PTD23__NF_IO7 0x28df
283 VF610_PAD_PTD22__NF_IO6 0x28df
284 VF610_PAD_PTD21__NF_IO5 0x28df
285 VF610_PAD_PTD20__NF_IO4 0x28df
286 VF610_PAD_PTD19__NF_IO3 0x28df
287 VF610_PAD_PTD18__NF_IO2 0x28df
288 VF610_PAD_PTD17__NF_IO1 0x28df
289 VF610_PAD_PTD16__NF_IO0 0x28df
290 VF610_PAD_PTB24__NF_WE_B 0x28c2
291 VF610_PAD_PTB25__NF_CE0_B 0x28c2
292 VF610_PAD_PTB27__NF_RE_B 0x28c2
293 VF610_PAD_PTC26__NF_RB_B 0x283d
294 VF610_PAD_PTC27__NF_ALE 0x28c2
295 VF610_PAD_PTC28__NF_CLE 0x28c2
299 pinctrl_pwm0: pwm0grp {
301 VF610_PAD_PTB0__FTM0_CH0 0x1582
302 VF610_PAD_PTB1__FTM0_CH1 0x1582
303 VF610_PAD_PTB2__FTM0_CH2 0x1582
304 VF610_PAD_PTB3__FTM0_CH3 0x1582
308 pinctrl_sai2: sai2grp {
310 VF610_PAD_PTA16__SAI2_TX_BCLK 0x02ed
311 VF610_PAD_PTA18__SAI2_TX_DATA 0x02ee
312 VF610_PAD_PTA19__SAI2_TX_SYNC 0x02ed
313 VF610_PAD_PTA21__SAI2_RX_BCLK 0x02ed
314 VF610_PAD_PTA22__SAI2_RX_DATA 0x02ed
315 VF610_PAD_PTA23__SAI2_RX_SYNC 0x02ed
316 VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed
320 pinctrl_uart1: uart1grp {
322 VF610_PAD_PTB4__UART1_TX 0x21a2
323 VF610_PAD_PTB5__UART1_RX 0x21a1
327 pinctrl_uart2: uart2grp {
329 VF610_PAD_PTB6__UART2_TX 0x21a2
330 VF610_PAD_PTB7__UART2_RX 0x21a1
337 assigned-clocks = <&clks VF610_CLK_NFC>;
338 assigned-clock-rates = <33000000>;
339 pinctrl-names = "default";
340 pinctrl-0 = <&pinctrl_nfc>;
344 compatible = "fsl,vf610-nfc-nandcs";
346 #address-cells = <1>;
348 nand-bus-width = <16>;
349 nand-ecc-mode = "hw";
350 nand-ecc-strength = <24>;
351 nand-ecc-step-size = <2048>;
357 pinctrl-names = "default";
358 pinctrl-0 = <&pinctrl_pwm0>;
363 #sound-dai-cells = <0>;
364 pinctrl-names = "default";
365 pinctrl-0 = <&pinctrl_sai2>;
370 pinctrl-names = "default";
371 pinctrl-0 = <&pinctrl_uart1>;
376 pinctrl-names = "default";
377 pinctrl-0 = <&pinctrl_uart2>;
382 disable-over-current;
387 disable-over-current;