arch/arm/boot/dts/vf610-zii-dev.dtsi

   1 /*
   2  * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
   3  *
   4  * Based on an original 'vf610-twr.dts' which is Copyright 2015,
   5  * Freescale Semiconductor, Inc.
   6  *
   7  * This file is dual-licensed: you can use it either under the terms
   8  * of the GPL or the X11 license, at your option. Note that this dual
   9  * licensing only applies to this file, and not this project as a
  10  * whole.
  11  *
  12  *  a) This file is free software; you can redistribute it and/or
  13  *     modify it under the terms of the GNU General Public License
  14  *     version 2 as published by the Free Software Foundation.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include "vf610.dtsi"
  46
  47 / {
  48         chosen {
  49                 stdout-path = "serial0:115200n8";
  50         };
  51
  52         memory {
  53                 reg = <0x80000000 0x20000000>;
  54         };
  55
  56         gpio-leds {
  57                 compatible = "gpio-leds";
  58                 pinctrl-0 = <&pinctrl_leds_debug>;
  59                 pinctrl-names = "default";
  60
  61                 debug {
  62                         label = "zii:green:debug1";
  63                         gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
  64                         linux,default-trigger = "heartbeat";
  65                 };
  66         };
  67
  68         reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu {
  69                 compatible = "regulator-fixed";
  70                 regulator-name = "vcc_3v3_mcu";
  71                 regulator-min-microvolt = <3300000>;
  72                 regulator-max-microvolt = <3300000>;
  73         };
  74
  75         usb0_vbus: regulator-usb0-vbus {
  76                 compatible = "regulator-fixed";
  77                 pinctrl-0 = <&pinctrl_usb_vbus>;
  78                 regulator-name = "usb_vbus";
  79                 regulator-min-microvolt = <5000000>;
  80                 regulator-max-microvolt = <5000000>;
  81                 enable-active-high;
  82                 regulator-always-on;
  83                 regulator-boot-on;
  84                 gpio = <&gpio0 6 0>;
  85         };
  86 };
  87
  88 &adc0 {
  89         pinctrl-names = "default";
  90         pinctrl-0 = <&pinctrl_adc0_ad5>;
  91         vref-supply = <&reg_vcc_3v3_mcu>;
  92         status = "okay";
  93 };
  94
  95 &edma0 {
  96         status = "okay";
  97 };
  98
  99 &esdhc1 {
 100         pinctrl-names = "default";
 101         pinctrl-0 = <&pinctrl_esdhc1>;
 102         bus-width = <4>;
 103         status = "okay";
 104 };
 105
 106 &fec0 {
 107         phy-mode = "rmii";
 108         pinctrl-names = "default";
 109         pinctrl-0 = <&pinctrl_fec0>;
 110         status = "okay";
 111 };
 112
 113 &fec1 {
 114         phy-mode = "rmii";
 115         pinctrl-names = "default";
 116         pinctrl-0 = <&pinctrl_fec1>;
 117         status = "okay";
 118
 119         fixed-link {
 120                    speed = <100>;
 121                    full-duplex;
 122         };
 123
 124         mdio1: mdio {
 125                 #address-cells = <1>;
 126                 #size-cells = <0>;
 127                 status = "okay";
 128         };
 129 };
 130
 131 &i2c0 {
 132         clock-frequency = <100000>;
 133         pinctrl-names = "default", "gpio";
 134         pinctrl-0 = <&pinctrl_i2c0>;
 135         pinctrl-1 = <&pinctrl_i2c0_gpio>;
 136         scl-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
 137         sda-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
 138         status = "okay";
 139
 140         lm75@48 {
 141                 compatible = "national,lm75";
 142                 reg = <0x48>;
 143         };
 144
 145         at24c04@50 {
 146                 compatible = "atmel,24c04";
 147                 reg = <0x50>;
 148         };
 149
 150         at24c04@52 {
 151                 compatible = "atmel,24c04";
 152                 reg = <0x52>;
 153         };
 154
 155         ds1682@6b {
 156                 compatible = "dallas,ds1682";
 157                 reg = <0x6b>;
 158         };
 159 };
 160
 161 &i2c1 {
 162         clock-frequency = <100000>;
 163         pinctrl-names = "default";
 164         pinctrl-0 = <&pinctrl_i2c1>;
 165         status = "okay";
 166 };
 167
 168 &i2c2 {
 169         clock-frequency = <100000>;
 170         pinctrl-names = "default";
 171         pinctrl-0 = <&pinctrl_i2c2>;
 172         status = "okay";
 173 };
 174
 175 &uart0 {
 176         pinctrl-names = "default";
 177         pinctrl-0 = <&pinctrl_uart0>;
 178         status = "okay";
 179 };
 180
 181 &uart1 {
 182         pinctrl-names = "default";
 183         pinctrl-0 = <&pinctrl_uart1>;
 184         status = "okay";
 185 };
 186
 187 &uart2 {
 188         pinctrl-names = "default";
 189         pinctrl-0 = <&pinctrl_uart2>;
 190         status = "okay";
 191 };
 192
 193 &usbdev0 {
 194         disable-over-current;
 195         vbus-supply = <&usb0_vbus>;
 196         dr_mode = "host";
 197         status = "okay";
 198 };
 199
 200 &usbh1 {
 201         disable-over-current;
 202         status = "okay";
 203 };
 204
 205 &usbmisc0 {
 206         status = "okay";
 207 };
 208
 209 &usbmisc1 {
 210         status = "okay";
 211 };
 212
 213 &usbphy0 {
 214         status = "okay";
 215 };
 216
 217 &usbphy1 {
 218         status = "okay";
 219 };
 220
 221 &iomuxc {
 222         pinctrl_adc0_ad5: adc0ad5grp {
 223                 fsl,pins = <
 224                         VF610_PAD_PTC30__ADC0_SE5       0x00a1
 225                 >;
 226         };
 227
 228         pinctrl_dspi0: dspi0grp {
 229                 fsl,pins = <
 230                         VF610_PAD_PTB18__DSPI0_CS1      0x1182
 231                         VF610_PAD_PTB19__DSPI0_CS0      0x1182
 232                         VF610_PAD_PTB20__DSPI0_SIN      0x1181
 233                         VF610_PAD_PTB21__DSPI0_SOUT     0x1182
 234                         VF610_PAD_PTB22__DSPI0_SCK      0x1182
 235                 >;
 236         };
 237
 238         pinctrl_dspi2: dspi2grp {
 239                 fsl,pins = <
 240                         VF610_PAD_PTD31__DSPI2_CS1      0x1182
 241                         VF610_PAD_PTD30__DSPI2_CS0      0x1182
 242                         VF610_PAD_PTD29__DSPI2_SIN      0x1181
 243                         VF610_PAD_PTD28__DSPI2_SOUT     0x1182
 244                         VF610_PAD_PTD27__DSPI2_SCK      0x1182
 245                 >;
 246         };
 247
 248         pinctrl_esdhc1: esdhc1grp {
 249                 fsl,pins = <
 250                         VF610_PAD_PTA24__ESDHC1_CLK     0x31ef
 251                         VF610_PAD_PTA25__ESDHC1_CMD     0x31ef
 252                         VF610_PAD_PTA26__ESDHC1_DAT0    0x31ef
 253                         VF610_PAD_PTA27__ESDHC1_DAT1    0x31ef
 254                         VF610_PAD_PTA28__ESDHC1_DATA2   0x31ef
 255                         VF610_PAD_PTA29__ESDHC1_DAT3    0x31ef
 256                         VF610_PAD_PTA7__GPIO_134        0x219d
 257                 >;
 258         };
 259
 260         pinctrl_fec0: fec0grp {
 261                 fsl,pins = <
 262                         VF610_PAD_PTC0__ENET_RMII0_MDC  0x30d2
 263                         VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d3
 264                         VF610_PAD_PTC2__ENET_RMII0_CRS  0x30d1
 265                         VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1
 266                         VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1
 267                         VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1
 268                         VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2
 269                         VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2
 270                         VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2
 271                 >;
 272         };
 273
 274         pinctrl_fec1: fec1grp {
 275                 fsl,pins = <
 276                         VF610_PAD_PTA6__RMII_CLKIN              0x30d1
 277                         VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
 278                         VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
 279                         VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
 280                         VF610_PAD_PTC12__ENET_RMII1_RXD1        0x30d1
 281                         VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
 282                         VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
 283                         VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
 284                         VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
 285                         VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
 286                 >;
 287         };
 288
 289         pinctrl_gpio_spi0: pinctrl-gpio-spi0 {
 290                 fsl,pins = <
 291                         VF610_PAD_PTB22__GPIO_44        0x33e2
 292                         VF610_PAD_PTB21__GPIO_43        0x33e2
 293                         VF610_PAD_PTB20__GPIO_42        0x33e1
 294                         VF610_PAD_PTB19__GPIO_41        0x33e2
 295                         VF610_PAD_PTB18__GPIO_40        0x33e2
 296                 >;
 297         };
 298
 299         pinctrl_i2c_mux_reset: pinctrl-i2c-mux-reset {
 300                 fsl,pins = <
 301                          VF610_PAD_PTE14__GPIO_119      0x31c2
 302                          >;
 303         };
 304
 305         pinctrl_i2c0: i2c0grp {
 306                 fsl,pins = <
 307                         VF610_PAD_PTB14__I2C0_SCL       0x37ff
 308                         VF610_PAD_PTB15__I2C0_SDA       0x37ff
 309                 >;
 310         };
 311
 312         pinctrl_i2c0_gpio: i2c0grp-gpio {
 313                 fsl,pins = <
 314                         VF610_PAD_PTB14__GPIO_36        0x31c2
 315                         VF610_PAD_PTB15__GPIO_37        0x31c2
 316                 >;
 317         };
 318
 319
 320         pinctrl_i2c1: i2c1grp {
 321                 fsl,pins = <
 322                         VF610_PAD_PTB16__I2C1_SCL       0x37ff
 323                         VF610_PAD_PTB17__I2C1_SDA       0x37ff
 324                 >;
 325         };
 326
 327         pinctrl_i2c2: i2c2grp {
 328                 fsl,pins = <
 329                         VF610_PAD_PTA22__I2C2_SCL       0x37ff
 330                         VF610_PAD_PTA23__I2C2_SDA       0x37ff
 331                 >;
 332         };
 333
 334         pinctrl_leds_debug: pinctrl-leds-debug {
 335                 fsl,pins = <
 336                          VF610_PAD_PTD20__GPIO_74       0x31c2
 337                          >;
 338         };
 339
 340         pinctrl_qspi0: qspi0grp {
 341                 fsl,pins = <
 342                         VF610_PAD_PTD7__QSPI0_B_QSCK    0x31c3
 343                         VF610_PAD_PTD8__QSPI0_B_CS0     0x31ff
 344                         VF610_PAD_PTD9__QSPI0_B_DATA3   0x31c3
 345                         VF610_PAD_PTD10__QSPI0_B_DATA2  0x31c3
 346                         VF610_PAD_PTD11__QSPI0_B_DATA1  0x31c3
 347                         VF610_PAD_PTD12__QSPI0_B_DATA0  0x31c3
 348                 >;
 349         };
 350
 351         pinctrl_uart0: uart0grp {
 352                 fsl,pins = <
 353                         VF610_PAD_PTB10__UART0_TX       0x21a2
 354                         VF610_PAD_PTB11__UART0_RX       0x21a1
 355                 >;
 356         };
 357
 358         pinctrl_uart1: uart1grp {
 359                 fsl,pins = <
 360                         VF610_PAD_PTB23__UART1_TX       0x21a2
 361                         VF610_PAD_PTB24__UART1_RX       0x21a1
 362                 >;
 363         };
 364
 365         pinctrl_uart2: uart2grp {
 366                 fsl,pins = <
 367                         VF610_PAD_PTD0__UART2_TX        0x21a2
 368                         VF610_PAD_PTD1__UART2_RX        0x21a1
 369                 >;
 370         };
 371
 372         pinctrl_usb_vbus: pinctrl-usb-vbus {
 373                 fsl,pins = <
 374                         VF610_PAD_PTA16__GPIO_6 0x31c2
 375                 >;
 376         };
 377
 378         pinctrl_usb0_host: usb0-host-grp {
 379                 fsl,pins = <
 380                         VF610_PAD_PTD6__GPIO_85         0x0062
 381                 >;
 382         };
 383 };