2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include "skeleton.dtsi"
11 #include "vf610-pinfunc.h"
12 #include <dt-bindings/clock/vf610-clock.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
35 compatible = "arm,cortex-a5";
38 next-level-cache = <&L2>;
47 compatible = "fixed-clock";
48 clock-frequency = <32768>;
52 compatible = "fixed-clock";
53 clock-frequency = <24000000>;
60 compatible = "simple-bus";
61 interrupt-parent = <&intc>;
64 aips0: aips-bus@40000000 {
65 compatible = "fsl,aips-bus", "simple-bus";
68 interrupt-parent = <&intc>;
69 reg = <0x40000000 0x70000>;
72 intc: interrupt-controller@40002000 {
73 compatible = "arm,cortex-a9-gic";
74 #interrupt-cells = <3>;
78 reg = <0x40003000 0x1000>,
82 L2: l2-cache@40006000 {
83 compatible = "arm,pl310-cache";
84 reg = <0x40006000 0x1000>;
87 arm,data-latency = <1 1 1>;
88 arm,tag-latency = <2 2 2>;
91 edma0: dma-controller@40018000 {
93 compatible = "fsl,vf610-edma";
94 reg = <0x40018000 0x2000>,
97 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
98 <0 9 IRQ_TYPE_LEVEL_HIGH>;
99 interrupt-names = "edma-tx", "edma-err";
101 clock-names = "dmamux0", "dmamux1";
102 clocks = <&clks VF610_CLK_DMAMUX0>,
103 <&clks VF610_CLK_DMAMUX1>;
106 uart0: serial@40027000 {
107 compatible = "fsl,vf610-lpuart";
108 reg = <0x40027000 0x1000>;
109 interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
110 clocks = <&clks VF610_CLK_UART0>;
114 dma-names = "rx","tx";
118 uart1: serial@40028000 {
119 compatible = "fsl,vf610-lpuart";
120 reg = <0x40028000 0x1000>;
121 interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
122 clocks = <&clks VF610_CLK_UART1>;
126 dma-names = "rx","tx";
130 uart2: serial@40029000 {
131 compatible = "fsl,vf610-lpuart";
132 reg = <0x40029000 0x1000>;
133 interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
134 clocks = <&clks VF610_CLK_UART2>;
138 dma-names = "rx","tx";
142 uart3: serial@4002a000 {
143 compatible = "fsl,vf610-lpuart";
144 reg = <0x4002a000 0x1000>;
145 interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&clks VF610_CLK_UART3>;
150 dma-names = "rx","tx";
154 dspi0: dspi0@4002c000 {
155 #address-cells = <1>;
157 compatible = "fsl,vf610-dspi";
158 reg = <0x4002c000 0x1000>;
159 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
160 clocks = <&clks VF610_CLK_DSPI0>;
161 clock-names = "dspi";
162 spi-num-chipselects = <5>;
167 compatible = "fsl,vf610-sai";
168 reg = <0x40031000 0x1000>;
169 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
170 clocks = <&clks VF610_CLK_SAI2>;
172 dma-names = "tx", "rx";
173 dmas = <&edma0 0 21>,
179 compatible = "fsl,vf610-pit";
180 reg = <0x40037000 0x1000>;
181 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
182 clocks = <&clks VF610_CLK_PIT>;
187 compatible = "fsl,vf610-adc";
188 reg = <0x4003b000 0x1000>;
189 interrupts = <0 53 0x04>;
190 clocks = <&clks VF610_CLK_ADC0>;
196 compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
197 reg = <0x4003e000 0x1000>;
198 clocks = <&clks VF610_CLK_WDT>;
199 clock-names = "wdog";
202 qspi0: quadspi@40044000 {
203 #address-cells = <1>;
205 compatible = "fsl,vf610-qspi";
206 reg = <0x40044000 0x1000>;
207 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
208 clocks = <&clks VF610_CLK_QSPI0_EN>,
209 <&clks VF610_CLK_QSPI0>;
210 clock-names = "qspi_en", "qspi";
214 iomuxc: iomuxc@40048000 {
215 compatible = "fsl,vf610-iomuxc";
216 reg = <0x40048000 0x1000>;
217 #gpio-range-cells = <3>;
220 gpio1: gpio@40049000 {
221 compatible = "fsl,vf610-gpio";
222 reg = <0x40049000 0x1000 0x400ff000 0x40>;
223 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
226 interrupt-controller;
227 #interrupt-cells = <2>;
228 gpio-ranges = <&iomuxc 0 0 32>;
231 gpio2: gpio@4004a000 {
232 compatible = "fsl,vf610-gpio";
233 reg = <0x4004a000 0x1000 0x400ff040 0x40>;
234 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
237 interrupt-controller;
238 #interrupt-cells = <2>;
239 gpio-ranges = <&iomuxc 0 32 32>;
242 gpio3: gpio@4004b000 {
243 compatible = "fsl,vf610-gpio";
244 reg = <0x4004b000 0x1000 0x400ff080 0x40>;
245 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
248 interrupt-controller;
249 #interrupt-cells = <2>;
250 gpio-ranges = <&iomuxc 0 64 32>;
253 gpio4: gpio@4004c000 {
254 compatible = "fsl,vf610-gpio";
255 reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
256 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
259 interrupt-controller;
260 #interrupt-cells = <2>;
261 gpio-ranges = <&iomuxc 0 96 32>;
264 gpio5: gpio@4004d000 {
265 compatible = "fsl,vf610-gpio";
266 reg = <0x4004d000 0x1000 0x400ff100 0x40>;
267 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
270 interrupt-controller;
271 #interrupt-cells = <2>;
272 gpio-ranges = <&iomuxc 0 128 7>;
276 compatible = "fsl,vf610-anatop";
277 reg = <0x40050000 0x1000>;
281 #address-cells = <1>;
283 compatible = "fsl,vf610-i2c";
284 reg = <0x40066000 0x1000>;
285 interrupts =<0 71 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&clks VF610_CLK_I2C0>;
288 dmas = <&edma0 0 50>,
290 dma-names = "rx","tx";
295 compatible = "fsl,vf610-ccm";
296 reg = <0x4006b000 0x1000>;
301 aips1: aips-bus@40080000 {
302 compatible = "fsl,aips-bus", "simple-bus";
303 #address-cells = <1>;
305 reg = <0x40080000 0x80000>;
308 edma1: dma-controller@40098000 {
310 compatible = "fsl,vf610-edma";
311 reg = <0x40098000 0x2000>,
314 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>,
315 <0 11 IRQ_TYPE_LEVEL_HIGH>;
316 interrupt-names = "edma-tx", "edma-err";
318 clock-names = "dmamux0", "dmamux1";
319 clocks = <&clks VF610_CLK_DMAMUX2>,
320 <&clks VF610_CLK_DMAMUX3>;
323 uart4: serial@400a9000 {
324 compatible = "fsl,vf610-lpuart";
325 reg = <0x400a9000 0x1000>;
326 interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
327 clocks = <&clks VF610_CLK_UART4>;
332 uart5: serial@400aa000 {
333 compatible = "fsl,vf610-lpuart";
334 reg = <0x400aa000 0x1000>;
335 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&clks VF610_CLK_UART5>;
342 compatible = "fsl,vf610-adc";
343 reg = <0x400bb000 0x1000>;
344 interrupts = <0 54 0x04>;
345 clocks = <&clks VF610_CLK_ADC1>;
350 fec0: ethernet@400d0000 {
351 compatible = "fsl,mvf600-fec";
352 reg = <0x400d0000 0x1000>;
353 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&clks VF610_CLK_ENET0>,
355 <&clks VF610_CLK_ENET0>,
356 <&clks VF610_CLK_ENET>;
357 clock-names = "ipg", "ahb", "ptp";
361 fec1: ethernet@400d1000 {
362 compatible = "fsl,mvf600-fec";
363 reg = <0x400d1000 0x1000>;
364 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
365 clocks = <&clks VF610_CLK_ENET1>,
366 <&clks VF610_CLK_ENET1>,
367 <&clks VF610_CLK_ENET>;
368 clock-names = "ipg", "ahb", "ptp";