arch/arm/boot/dts/wm8505.dtsi

   1 /*
   2  * wm8505.dtsi - Device tree file for Wondermedia WM8505 SoC
   3  *
   4  * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
   5  *
   6  * Licensed under GPLv2 or later
   7  */
   8
   9 /include/ "skeleton.dtsi"
  10
  11 / {
  12         compatible = "wm,wm8505";
  13
  14         cpus {
  15                 cpu@0 {
  16                         compatible = "arm,arm926ejs";
  17                 };
  18         };
  19
  20         soc {
  21                 #address-cells = <1>;
  22                 #size-cells = <1>;
  23                 compatible = "simple-bus";
  24                 ranges;
  25                 interrupt-parent = <&intc0>;
  26
  27                 intc0: interrupt-controller@d8140000 {
  28                         compatible = "via,vt8500-intc";
  29                         interrupt-controller;
  30                         reg = <0xd8140000 0x10000>;
  31                         #interrupt-cells = <1>;
  32                 };
  33
  34                 /* Secondary IC cascaded to intc0 */
  35                 intc1: interrupt-controller@d8150000 {
  36                         compatible = "via,vt8500-intc";
  37                         interrupt-controller;
  38                         #interrupt-cells = <1>;
  39                         reg = <0xD8150000 0x10000>;
  40                         interrupts = <56 57 58 59 60 61 62 63>;
  41                 };
  42
  43                 gpio: gpio-controller@d8110000 {
  44                         compatible = "wm,wm8505-gpio";
  45                         gpio-controller;
  46                         reg = <0xd8110000 0x10000>;
  47                         #gpio-cells = <3>;
  48                 };
  49
  50                 pmc@d8130000 {
  51                         compatible = "via,vt8500-pmc";
  52                         reg = <0xd8130000 0x1000>;
  53                         clocks {
  54                                 #address-cells = <1>;
  55                                 #size-cells = <0>;
  56
  57                                 ref24: ref24M {
  58                                         #clock-cells = <0>;
  59                                         compatible = "fixed-clock";
  60                                         clock-frequency = <24000000>;
  61                                 };
  62
  63                                 ref25: ref25M {
  64                                         #clock-cells = <0>;
  65                                         compatible = "fixed-clock";
  66                                         clock-frequency = <25000000>;
  67                                 };
  68
  69                                 pllb: pllb {
  70                                         #clock-cells = <0>;
  71                                         compatible = "via,vt8500-pll-clock";
  72                                         clocks = <&ref25>;
  73                                         reg = <0x204>;
  74                                 };
  75
  76                                 clkuart0: uart0 {
  77                                         #clock-cells = <0>;
  78                                         compatible = "via,vt8500-device-clock";
  79                                         clocks = <&ref24>;
  80                                         enable-reg = <0x250>;
  81                                         enable-bit = <1>;
  82                                 };
  83
  84                                 clkuart1: uart1 {
  85                                         #clock-cells = <0>;
  86                                         compatible = "via,vt8500-device-clock";
  87                                         clocks = <&ref24>;
  88                                         enable-reg = <0x250>;
  89                                         enable-bit = <2>;
  90                                 };
  91
  92                                 clkuart2: uart2 {
  93                                         #clock-cells = <0>;
  94                                         compatible = "via,vt8500-device-clock";
  95                                         clocks = <&ref24>;
  96                                         enable-reg = <0x250>;
  97                                         enable-bit = <3>;
  98                                 };
  99
 100                                 clkuart3: uart3 {
 101                                         #clock-cells = <0>;
 102                                         compatible = "via,vt8500-device-clock";
 103                                         clocks = <&ref24>;
 104                                         enable-reg = <0x250>;
 105                                         enable-bit = <4>;
 106                                 };
 107
 108                                 clkuart4: uart4 {
 109                                         #clock-cells = <0>;
 110                                         compatible = "via,vt8500-device-clock";
 111                                         clocks = <&ref24>;
 112                                         enable-reg = <0x250>;
 113                                         enable-bit = <22>;
 114                                 };
 115
 116                                 clkuart5: uart5 {
 117                                         #clock-cells = <0>;
 118                                         compatible = "via,vt8500-device-clock";
 119                                         clocks = <&ref24>;
 120                                         enable-reg = <0x250>;
 121                                         enable-bit = <23>;
 122                                 };
 123
 124                                 clksdhc: sdhc {
 125                                         #clock-cells = <0>;
 126                                         compatible = "via,vt8500-device-clock";
 127                                         clocks = <&pllb>;
 128                                         divisor-reg = <0x328>;
 129                                         divisor-mask = <0x3f>;
 130                                         enable-reg = <0x254>;
 131                                         enable-bit = <18>;
 132                                 };
 133                         };
 134                 };
 135
 136                 timer@d8130100 {
 137                         compatible = "via,vt8500-timer";
 138                         reg = <0xd8130100 0x28>;
 139                         interrupts = <36>;
 140                 };
 141
 142                 ehci@d8007100 {
 143                         compatible = "via,vt8500-ehci";
 144                         reg = <0xd8007100 0x200>;
 145                         interrupts = <1>;
 146                 };
 147
 148                 uhci@d8007300 {
 149                         compatible = "platform-uhci";
 150                         reg = <0xd8007300 0x200>;
 151                         interrupts = <0>;
 152                 };
 153
 154                 fb: fb@d8050800 {
 155                         compatible = "wm,wm8505-fb";
 156                         reg = <0xd8050800 0x200>;
 157                 };
 158
 159                 ge_rops@d8050400 {
 160                         compatible = "wm,prizm-ge-rops";
 161                         reg = <0xd8050400 0x100>;
 162                 };
 163
 164                 uart@d8200000 {
 165                         compatible = "via,vt8500-uart";
 166                         reg = <0xd8200000 0x1040>;
 167                         interrupts = <32>;
 168                         clocks = <&clkuart0>;
 169                 };
 170
 171                 uart@d82b0000 {
 172                         compatible = "via,vt8500-uart";
 173                         reg = <0xd82b0000 0x1040>;
 174                         interrupts = <33>;
 175                         clocks = <&clkuart1>;
 176                 };
 177
 178                 uart@d8210000 {
 179                         compatible = "via,vt8500-uart";
 180                         reg = <0xd8210000 0x1040>;
 181                         interrupts = <47>;
 182                         clocks = <&clkuart2>;
 183                 };
 184
 185                 uart@d82c0000 {
 186                         compatible = "via,vt8500-uart";
 187                         reg = <0xd82c0000 0x1040>;
 188                         interrupts = <50>;
 189                         clocks = <&clkuart3>;
 190                 };
 191
 192                 uart@d8370000 {
 193                         compatible = "via,vt8500-uart";
 194                         reg = <0xd8370000 0x1040>;
 195                         interrupts = <31>;
 196                         clocks = <&clkuart4>;
 197                 };
 198
 199                 uart@d8380000 {
 200                         compatible = "via,vt8500-uart";
 201                         reg = <0xd8380000 0x1040>;
 202                         interrupts = <30>;
 203                         clocks = <&clkuart5>;
 204                 };
 205
 206                 rtc@d8100000 {
 207                         compatible = "via,vt8500-rtc";
 208                         reg = <0xd8100000 0x10000>;
 209                         interrupts = <48>;
 210                 };
 211
 212                 sdhc@d800a000 {
 213                         compatible = "wm,wm8505-sdhc";
 214                         reg = <0xd800a000 0x1000>;
 215                         interrupts = <20 21>;
 216                         clocks = <&clksdhc>;
 217                         bus-width = <4>;
 218                 };
 219         };
 220 };