2 * Copyright (C) 2011 Xilinx
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 /include/ "skeleton.dtsi"
16 compatible = "xlnx,zynq-7000";
19 compatible = "arm,cortex-a9-pmu";
20 interrupts = <0 5 4>, <0 6 4>;
21 interrupt-parent = <&intc>;
22 reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
26 compatible = "simple-bus";
29 interrupt-parent = <&intc>;
32 intc: interrupt-controller@f8f01000 {
33 compatible = "arm,cortex-a9-gic";
34 #interrupt-cells = <3>;
37 reg = <0xF8F01000 0x1000>,
41 L2: cache-controller {
42 compatible = "arm,pl310-cache";
43 reg = <0xF8F02000 0x1000>;
44 arm,data-latency = <3 2 2>;
45 arm,tag-latency = <2 2 2>;
50 uart0: uart@e0000000 {
51 compatible = "xlnx,xuartps";
53 clocks = <&clkc 23>, <&clkc 40>;
54 clock-names = "ref_clk", "aper_clk";
55 reg = <0xE0000000 0x1000>;
56 interrupts = <0 27 4>;
59 uart1: uart@e0001000 {
60 compatible = "xlnx,xuartps";
62 clocks = <&clkc 24>, <&clkc 41>;
63 clock-names = "ref_clk", "aper_clk";
64 reg = <0xE0001000 0x1000>;
65 interrupts = <0 50 4>;
68 gem0: ethernet@e000b000 {
69 compatible = "cdns,gem";
70 reg = <0xe000b000 0x4000>;
72 interrupts = <0 22 4>;
73 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
74 clock-names = "pclk", "hclk", "tx_clk";
77 gem1: ethernet@e000c000 {
78 compatible = "cdns,gem";
79 reg = <0xe000c000 0x4000>;
81 interrupts = <0 45 4>;
82 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
83 clock-names = "pclk", "hclk", "tx_clk";
87 compatible = "xlnx,zynq-slcr";
88 reg = <0xF8000000 0x1000>;
96 compatible = "xlnx,ps7-clkc";
97 ps-clk-frequency = <33333333>;
98 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
99 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
100 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
101 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
102 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
103 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
104 "gem1_aper", "sdio0_aper", "sdio1_aper",
105 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
106 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
107 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
108 "dbg_trc", "dbg_apb";
113 global_timer: timer@f8f00200 {
114 compatible = "arm,cortex-a9-global-timer";
115 reg = <0xf8f00200 0x20>;
116 interrupts = <1 11 0x301>;
117 interrupt-parent = <&intc>;
121 ttc0: ttc0@f8001000 {
122 interrupt-parent = <&intc>;
123 interrupts = < 0 10 4 0 11 4 0 12 4 >;
124 compatible = "cdns,ttc";
126 reg = <0xF8001000 0x1000>;
130 ttc1: ttc1@f8002000 {
131 interrupt-parent = <&intc>;
132 interrupts = < 0 37 4 0 38 4 0 39 4 >;
133 compatible = "cdns,ttc";
135 reg = <0xF8002000 0x1000>;
138 scutimer: scutimer@f8f00600 {
139 interrupt-parent = <&intc>;
140 interrupts = < 1 13 0x301 >;
141 compatible = "arm,cortex-a9-twd-timer";
142 reg = < 0xf8f00600 0x20 >;