2 * Copyright (C) 2011 - 2014 Xilinx
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 /include/ "skeleton.dtsi"
16 compatible = "xlnx,zynq-7000";
23 compatible = "arm,cortex-a9";
27 clock-latency = <1000>;
28 cpu0-supply = <®ulator_vccpint>;
37 compatible = "arm,cortex-a9";
45 compatible = "arm,cortex-a9-pmu";
46 interrupts = <0 5 4>, <0 6 4>;
47 interrupt-parent = <&intc>;
48 reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
51 regulator_vccpint: fixedregulator@0 {
52 compatible = "regulator-fixed";
53 regulator-name = "VCCPINT";
54 regulator-min-microvolt = <1000000>;
55 regulator-max-microvolt = <1000000>;
61 compatible = "simple-bus";
64 interrupt-parent = <&intc>;
68 compatible = "xlnx,zynq-xadc-1.00.a";
69 reg = <0xf8007100 0x20>;
71 interrupt-parent = <&intc>;
76 compatible = "xlnx,zynq-can-1.0";
78 clocks = <&clkc 19>, <&clkc 36>;
79 clock-names = "can_clk", "pclk";
80 reg = <0xe0008000 0x1000>;
81 interrupts = <0 28 4>;
82 interrupt-parent = <&intc>;
83 tx-fifo-depth = <0x40>;
84 rx-fifo-depth = <0x40>;
88 compatible = "xlnx,zynq-can-1.0";
90 clocks = <&clkc 20>, <&clkc 37>;
91 clock-names = "can_clk", "pclk";
92 reg = <0xe0009000 0x1000>;
93 interrupts = <0 51 4>;
94 interrupt-parent = <&intc>;
95 tx-fifo-depth = <0x40>;
96 rx-fifo-depth = <0x40>;
99 gpio0: gpio@e000a000 {
100 compatible = "xlnx,zynq-gpio-1.0";
104 interrupt-controller;
105 #interrupt-cells = <2>;
106 interrupt-parent = <&intc>;
107 interrupts = <0 20 4>;
108 reg = <0xe000a000 0x1000>;
112 compatible = "cdns,i2c-r1p10";
115 interrupt-parent = <&intc>;
116 interrupts = <0 25 4>;
117 reg = <0xe0004000 0x1000>;
118 #address-cells = <1>;
123 compatible = "cdns,i2c-r1p10";
126 interrupt-parent = <&intc>;
127 interrupts = <0 48 4>;
128 reg = <0xe0005000 0x1000>;
129 #address-cells = <1>;
133 intc: interrupt-controller@f8f01000 {
134 compatible = "arm,cortex-a9-gic";
135 #interrupt-cells = <3>;
136 interrupt-controller;
137 reg = <0xF8F01000 0x1000>,
141 L2: cache-controller@f8f02000 {
142 compatible = "arm,pl310-cache";
143 reg = <0xF8F02000 0x1000>;
144 interrupts = <0 2 4>;
145 arm,data-latency = <3 2 2>;
146 arm,tag-latency = <2 2 2>;
151 mc: memory-controller@f8006000 {
152 compatible = "xlnx,zynq-ddrc-a05";
153 reg = <0xf8006000 0x1000>;
156 uart0: serial@e0000000 {
157 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
159 clocks = <&clkc 23>, <&clkc 40>;
160 clock-names = "uart_clk", "pclk";
161 reg = <0xE0000000 0x1000>;
162 interrupts = <0 27 4>;
165 uart1: serial@e0001000 {
166 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
168 clocks = <&clkc 24>, <&clkc 41>;
169 clock-names = "uart_clk", "pclk";
170 reg = <0xE0001000 0x1000>;
171 interrupts = <0 50 4>;
175 compatible = "xlnx,zynq-spi-r1p6";
176 reg = <0xe0006000 0x1000>;
178 interrupt-parent = <&intc>;
179 interrupts = <0 26 4>;
180 clocks = <&clkc 25>, <&clkc 34>;
181 clock-names = "ref_clk", "pclk";
182 #address-cells = <1>;
187 compatible = "xlnx,zynq-spi-r1p6";
188 reg = <0xe0007000 0x1000>;
190 interrupt-parent = <&intc>;
191 interrupts = <0 49 4>;
192 clocks = <&clkc 26>, <&clkc 35>;
193 clock-names = "ref_clk", "pclk";
194 #address-cells = <1>;
198 gem0: ethernet@e000b000 {
199 compatible = "cdns,zynq-gem", "cdns,gem";
200 reg = <0xe000b000 0x1000>;
202 interrupts = <0 22 4>;
203 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
204 clock-names = "pclk", "hclk", "tx_clk";
205 #address-cells = <1>;
209 gem1: ethernet@e000c000 {
210 compatible = "cdns,zynq-gem", "cdns,gem";
211 reg = <0xe000c000 0x1000>;
213 interrupts = <0 45 4>;
214 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
215 clock-names = "pclk", "hclk", "tx_clk";
216 #address-cells = <1>;
220 sdhci0: sdhci@e0100000 {
221 compatible = "arasan,sdhci-8.9a";
223 clock-names = "clk_xin", "clk_ahb";
224 clocks = <&clkc 21>, <&clkc 32>;
225 interrupt-parent = <&intc>;
226 interrupts = <0 24 4>;
227 reg = <0xe0100000 0x1000>;
230 sdhci1: sdhci@e0101000 {
231 compatible = "arasan,sdhci-8.9a";
233 clock-names = "clk_xin", "clk_ahb";
234 clocks = <&clkc 22>, <&clkc 33>;
235 interrupt-parent = <&intc>;
236 interrupts = <0 47 4>;
237 reg = <0xe0101000 0x1000>;
240 slcr: slcr@f8000000 {
241 #address-cells = <1>;
243 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
244 reg = <0xF8000000 0x1000>;
248 compatible = "xlnx,ps7-clkc";
250 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
251 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
252 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
253 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
254 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
255 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
256 "gem1_aper", "sdio0_aper", "sdio1_aper",
257 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
258 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
259 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
260 "dbg_trc", "dbg_apb";
265 compatible = "xlnx,zynq-reset";
271 pinctrl0: pinctrl@700 {
272 compatible = "xlnx,pinctrl-zynq";
278 dmac_s: dmac@f8003000 {
279 compatible = "arm,pl330", "arm,primecell";
280 reg = <0xf8003000 0x1000>;
281 interrupt-parent = <&intc>;
282 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
283 "dma4", "dma5", "dma6", "dma7";
284 interrupts = <0 13 4>,
293 clock-names = "apb_pclk";
296 devcfg: devcfg@f8007000 {
297 compatible = "xlnx,zynq-devcfg-1.0";
298 reg = <0xf8007000 0x100>;
299 interrupt-parent = <&intc>;
300 interrupts = <0 8 4>;
302 clock-names = "ref_clk";
306 global_timer: timer@f8f00200 {
307 compatible = "arm,cortex-a9-global-timer";
308 reg = <0xf8f00200 0x20>;
309 interrupts = <1 11 0x301>;
310 interrupt-parent = <&intc>;
314 ttc0: timer@f8001000 {
315 interrupt-parent = <&intc>;
316 interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
317 compatible = "cdns,ttc";
319 reg = <0xF8001000 0x1000>;
322 ttc1: timer@f8002000 {
323 interrupt-parent = <&intc>;
324 interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
325 compatible = "cdns,ttc";
327 reg = <0xF8002000 0x1000>;
330 scutimer: timer@f8f00600 {
331 interrupt-parent = <&intc>;
332 interrupts = <1 13 0x301>;
333 compatible = "arm,cortex-a9-twd-timer";
334 reg = <0xf8f00600 0x20>;
339 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
342 interrupt-parent = <&intc>;
343 interrupts = <0 21 4>;
344 reg = <0xe0002000 0x1000>;
349 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
352 interrupt-parent = <&intc>;
353 interrupts = <0 44 4>;
354 reg = <0xe0003000 0x1000>;
358 watchdog0: watchdog@f8005000 {
360 compatible = "cdns,wdt-r1p2";
361 interrupt-parent = <&intc>;
362 interrupts = <0 9 1>;
363 reg = <0xf8005000 0x1000>;