arch/arm/boot/dts/zynq-zc702.dts

   1 /*
   2  *  Copyright (C) 2011 - 2014 Xilinx
   3  *  Copyright (C) 2012 National Instruments Corp.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14 /dts-v1/;
  15 /include/ "zynq-7000.dtsi"
  16
  17 / {
  18         model = "Zynq ZC702 Development Board";
  19         compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
  20
  21         aliases {
  22                 ethernet0 = &gem0;
  23                 i2c0 = &i2c0;
  24                 serial0 = &uart1;
  25         };
  26
  27         memory {
  28                 device_type = "memory";
  29                 reg = <0x0 0x40000000>;
  30         };
  31
  32         chosen {
  33                 bootargs = "earlyprintk";
  34                 stdout-path = "serial0:115200n8";
  35         };
  36
  37         leds {
  38                 compatible = "gpio-leds";
  39
  40                 ds23 {
  41                         label = "ds23";
  42                         gpios = <&gpio0 10 0>;
  43                         linux,default-trigger = "heartbeat";
  44                 };
  45         };
  46
  47         usb_phy0: phy0 {
  48                 compatible = "usb-nop-xceiv";
  49                 #phy-cells = <0>;
  50         };
  51 };
  52
  53 &amba {
  54         ocm: sram@fffc0000 {
  55                 compatible = "mmio-sram";
  56                 reg = <0xfffc0000 0x10000>;
  57         };
  58 };
  59
  60 &can0 {
  61         status = "okay";
  62         pinctrl-names = "default";
  63         pinctrl-0 = <&pinctrl_can0_default>;
  64 };
  65
  66 &clkc {
  67         ps-clk-frequency = <33333333>;
  68 };
  69
  70 &gem0 {
  71         status = "okay";
  72         phy-mode = "rgmii-id";
  73         phy-handle = <&ethernet_phy>;
  74         pinctrl-names = "default";
  75         pinctrl-0 = <&pinctrl_gem0_default>;
  76
  77         ethernet_phy: ethernet-phy@7 {
  78                 reg = <7>;
  79         };
  80 };
  81
  82 &gpio0 {
  83         pinctrl-names = "default";
  84         pinctrl-0 = <&pinctrl_gpio0_default>;
  85 };
  86
  87 &i2c0 {
  88         status = "okay";
  89         clock-frequency = <400000>;
  90         pinctrl-names = "default";
  91         pinctrl-0 = <&pinctrl_i2c0_default>;
  92
  93         i2cswitch@74 {
  94                 compatible = "nxp,pca9548";
  95                 #address-cells = <1>;
  96                 #size-cells = <0>;
  97                 reg = <0x74>;
  98
  99                 i2c@0 {
 100                         #address-cells = <1>;
 101                         #size-cells = <0>;
 102                         reg = <0>;
 103                         si570: clock-generator@5d {
 104                                 #clock-cells = <0>;
 105                                 compatible = "silabs,si570";
 106                                 temperature-stability = <50>;
 107                                 reg = <0x5d>;
 108                                 factory-fout = <156250000>;
 109                                 clock-frequency = <148500000>;
 110                         };
 111                 };
 112
 113                 i2c@2 {
 114                         #address-cells = <1>;
 115                         #size-cells = <0>;
 116                         reg = <2>;
 117                         eeprom@54 {
 118                                 compatible = "at,24c08";
 119                                 reg = <0x54>;
 120                         };
 121                 };
 122
 123                 i2c@3 {
 124                         #address-cells = <1>;
 125                         #size-cells = <0>;
 126                         reg = <3>;
 127                         gpio@21 {
 128                                 compatible = "ti,tca6416";
 129                                 reg = <0x21>;
 130                                 gpio-controller;
 131                                 #gpio-cells = <2>;
 132                         };
 133                 };
 134
 135                 i2c@4 {
 136                         #address-cells = <1>;
 137                         #size-cells = <0>;
 138                         reg = <4>;
 139                         rtc@51 {
 140                                 compatible = "nxp,pcf8563";
 141                                 reg = <0x51>;
 142                         };
 143                 };
 144
 145                 i2c@7 {
 146                         #address-cells = <1>;
 147                         #size-cells = <0>;
 148                         reg = <7>;
 149                         hwmon@52 {
 150                                 compatible = "ti,ucd9248";
 151                                 reg = <52>;
 152                         };
 153                         hwmon@53 {
 154                                 compatible = "ti,ucd9248";
 155                                 reg = <53>;
 156                         };
 157                         hwmon@54 {
 158                                 compatible = "ti,ucd9248";
 159                                 reg = <54>;
 160                         };
 161                 };
 162         };
 163 };
 164
 165 &pinctrl0 {
 166         pinctrl_can0_default: can0-default {
 167                 mux {
 168                         function = "can0";
 169                         groups = "can0_9_grp";
 170                 };
 171
 172                 conf {
 173                         groups = "can0_9_grp";
 174                         slew-rate = <0>;
 175                         io-standard = <1>;
 176                 };
 177
 178                 conf-rx {
 179                         pins = "MIO46";
 180                         bias-high-impedance;
 181                 };
 182
 183                 conf-tx {
 184                         pins = "MIO47";
 185                         bias-disable;
 186                 };
 187         };
 188
 189         pinctrl_gem0_default: gem0-default {
 190                 mux {
 191                         function = "ethernet0";
 192                         groups = "ethernet0_0_grp";
 193                 };
 194
 195                 conf {
 196                         groups = "ethernet0_0_grp";
 197                         slew-rate = <0>;
 198                         io-standard = <4>;
 199                 };
 200
 201                 conf-rx {
 202                         pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
 203                         bias-high-impedance;
 204                         low-power-disable;
 205                 };
 206
 207                 conf-tx {
 208                         pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
 209                         bias-disable;
 210                         low-power-enable;
 211                 };
 212
 213                 mux-mdio {
 214                         function = "mdio0";
 215                         groups = "mdio0_0_grp";
 216                 };
 217
 218                 conf-mdio {
 219                         groups = "mdio0_0_grp";
 220                         slew-rate = <0>;
 221                         io-standard = <1>;
 222                         bias-disable;
 223                 };
 224         };
 225
 226         pinctrl_gpio0_default: gpio0-default {
 227                 mux {
 228                         function = "gpio0";
 229                         groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
 230                                  "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
 231                                  "gpio0_13_grp", "gpio0_14_grp";
 232                 };
 233
 234                 conf {
 235                         groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
 236                                  "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
 237                                  "gpio0_13_grp", "gpio0_14_grp";
 238                         slew-rate = <0>;
 239                         io-standard = <1>;
 240                 };
 241
 242                 conf-pull-up {
 243                         pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14";
 244                         bias-pull-up;
 245                 };
 246
 247                 conf-pull-none {
 248                         pins = "MIO7", "MIO8";
 249                         bias-disable;
 250                 };
 251         };
 252
 253         pinctrl_i2c0_default: i2c0-default {
 254                 mux {
 255                         groups = "i2c0_10_grp";
 256                         function = "i2c0";
 257                 };
 258
 259                 conf {
 260                         groups = "i2c0_10_grp";
 261                         bias-pull-up;
 262                         slew-rate = <0>;
 263                         io-standard = <1>;
 264                 };
 265         };
 266
 267         pinctrl_sdhci0_default: sdhci0-default {
 268                 mux {
 269                         groups = "sdio0_2_grp";
 270                         function = "sdio0";
 271                 };
 272
 273                 conf {
 274                         groups = "sdio0_2_grp";
 275                         slew-rate = <0>;
 276                         io-standard = <1>;
 277                         bias-disable;
 278                 };
 279
 280                 mux-cd {
 281                         groups = "gpio0_0_grp";
 282                         function = "sdio0_cd";
 283                 };
 284
 285                 conf-cd {
 286                         groups = "gpio0_0_grp";
 287                         bias-high-impedance;
 288                         bias-pull-up;
 289                         slew-rate = <0>;
 290                         io-standard = <1>;
 291                 };
 292
 293                 mux-wp {
 294                         groups = "gpio0_15_grp";
 295                         function = "sdio0_wp";
 296                 };
 297
 298                 conf-wp {
 299                         groups = "gpio0_15_grp";
 300                         bias-high-impedance;
 301                         bias-pull-up;
 302                         slew-rate = <0>;
 303                         io-standard = <1>;
 304                 };
 305         };
 306
 307         pinctrl_uart1_default: uart1-default {
 308                 mux {
 309                         groups = "uart1_10_grp";
 310                         function = "uart1";
 311                 };
 312
 313                 conf {
 314                         groups = "uart1_10_grp";
 315                         slew-rate = <0>;
 316                         io-standard = <1>;
 317                 };
 318
 319                 conf-rx {
 320                         pins = "MIO49";
 321                         bias-high-impedance;
 322                 };
 323
 324                 conf-tx {
 325                         pins = "MIO48";
 326                         bias-disable;
 327                 };
 328         };
 329
 330         pinctrl_usb0_default: usb0-default {
 331                 mux {
 332                         groups = "usb0_0_grp";
 333                         function = "usb0";
 334                 };
 335
 336                 conf {
 337                         groups = "usb0_0_grp";
 338                         slew-rate = <0>;
 339                         io-standard = <1>;
 340                 };
 341
 342                 conf-rx {
 343                         pins = "MIO29", "MIO31", "MIO36";
 344                         bias-high-impedance;
 345                 };
 346
 347                 conf-tx {
 348                         pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
 349                                "MIO35", "MIO37", "MIO38", "MIO39";
 350                         bias-disable;
 351                 };
 352         };
 353 };
 354
 355 &sdhci0 {
 356         status = "okay";
 357         pinctrl-names = "default";
 358         pinctrl-0 = <&pinctrl_sdhci0_default>;
 359 };
 360
 361 &uart1 {
 362         status = "okay";
 363         pinctrl-names = "default";
 364         pinctrl-0 = <&pinctrl_uart1_default>;
 365 };
 366
 367 &usb0 {
 368         status = "okay";
 369         dr_mode = "host";
 370         usb-phy = <&usb_phy0>;
 371         pinctrl-names = "default";
 372         pinctrl-0 = <&pinctrl_usb0_default>;
 373 };