2 * EDMA3 support for DaVinci
4 * Copyright (C) 2006-2009 Texas Instruments.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/module.h>
23 #include <linux/interrupt.h>
24 #include <linux/platform_device.h>
26 #include <linux/slab.h>
28 #include <linux/platform_data/edma.h>
30 /* Offsets matching "struct edmacc_param" */
33 #define PARM_A_B_CNT 0x08
35 #define PARM_SRC_DST_BIDX 0x10
36 #define PARM_LINK_BCNTRLD 0x14
37 #define PARM_SRC_DST_CIDX 0x18
38 #define PARM_CCNT 0x1c
40 #define PARM_SIZE 0x20
42 /* Offsets for EDMA CC global channel registers and their shadows */
43 #define SH_ER 0x00 /* 64 bits */
44 #define SH_ECR 0x08 /* 64 bits */
45 #define SH_ESR 0x10 /* 64 bits */
46 #define SH_CER 0x18 /* 64 bits */
47 #define SH_EER 0x20 /* 64 bits */
48 #define SH_EECR 0x28 /* 64 bits */
49 #define SH_EESR 0x30 /* 64 bits */
50 #define SH_SER 0x38 /* 64 bits */
51 #define SH_SECR 0x40 /* 64 bits */
52 #define SH_IER 0x50 /* 64 bits */
53 #define SH_IECR 0x58 /* 64 bits */
54 #define SH_IESR 0x60 /* 64 bits */
55 #define SH_IPR 0x68 /* 64 bits */
56 #define SH_ICR 0x70 /* 64 bits */
66 /* Offsets for EDMA CC global registers */
67 #define EDMA_REV 0x0000
68 #define EDMA_CCCFG 0x0004
69 #define EDMA_QCHMAP 0x0200 /* 8 registers */
70 #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
71 #define EDMA_QDMAQNUM 0x0260
72 #define EDMA_QUETCMAP 0x0280
73 #define EDMA_QUEPRI 0x0284
74 #define EDMA_EMR 0x0300 /* 64 bits */
75 #define EDMA_EMCR 0x0308 /* 64 bits */
76 #define EDMA_QEMR 0x0310
77 #define EDMA_QEMCR 0x0314
78 #define EDMA_CCERR 0x0318
79 #define EDMA_CCERRCLR 0x031c
80 #define EDMA_EEVAL 0x0320
81 #define EDMA_DRAE 0x0340 /* 4 x 64 bits*/
82 #define EDMA_QRAE 0x0380 /* 4 registers */
83 #define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */
84 #define EDMA_QSTAT 0x0600 /* 2 registers */
85 #define EDMA_QWMTHRA 0x0620
86 #define EDMA_QWMTHRB 0x0624
87 #define EDMA_CCSTAT 0x0640
89 #define EDMA_M 0x1000 /* global channel registers */
90 #define EDMA_ECR 0x1008
91 #define EDMA_ECRH 0x100C
92 #define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */
93 #define EDMA_PARM 0x4000 /* 128 param entries */
95 #define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5))
97 #define EDMA_DCHMAP 0x0100 /* 64 registers */
98 #define CHMAP_EXIST BIT(24)
100 #define EDMA_MAX_DMACH 64
101 #define EDMA_MAX_PARAMENTRY 512
103 /*****************************************************************************/
105 static void __iomem *edmacc_regs_base[EDMA_MAX_CC];
107 static inline unsigned int edma_read(unsigned ctlr, int offset)
109 return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset);
112 static inline void edma_write(unsigned ctlr, int offset, int val)
114 __raw_writel(val, edmacc_regs_base[ctlr] + offset);
116 static inline void edma_modify(unsigned ctlr, int offset, unsigned and,
119 unsigned val = edma_read(ctlr, offset);
122 edma_write(ctlr, offset, val);
124 static inline void edma_and(unsigned ctlr, int offset, unsigned and)
126 unsigned val = edma_read(ctlr, offset);
128 edma_write(ctlr, offset, val);
130 static inline void edma_or(unsigned ctlr, int offset, unsigned or)
132 unsigned val = edma_read(ctlr, offset);
134 edma_write(ctlr, offset, val);
136 static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i)
138 return edma_read(ctlr, offset + (i << 2));
140 static inline void edma_write_array(unsigned ctlr, int offset, int i,
143 edma_write(ctlr, offset + (i << 2), val);
145 static inline void edma_modify_array(unsigned ctlr, int offset, int i,
146 unsigned and, unsigned or)
148 edma_modify(ctlr, offset + (i << 2), and, or);
150 static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or)
152 edma_or(ctlr, offset + (i << 2), or);
154 static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j,
157 edma_or(ctlr, offset + ((i*2 + j) << 2), or);
159 static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j,
162 edma_write(ctlr, offset + ((i*2 + j) << 2), val);
164 static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset)
166 return edma_read(ctlr, EDMA_SHADOW0 + offset);
168 static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset,
171 return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2));
173 static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val)
175 edma_write(ctlr, EDMA_SHADOW0 + offset, val);
177 static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i,
180 edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val);
182 static inline unsigned int edma_parm_read(unsigned ctlr, int offset,
185 return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5));
187 static inline void edma_parm_write(unsigned ctlr, int offset, int param_no,
190 edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val);
192 static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no,
193 unsigned and, unsigned or)
195 edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or);
197 static inline void edma_parm_and(unsigned ctlr, int offset, int param_no,
200 edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and);
202 static inline void edma_parm_or(unsigned ctlr, int offset, int param_no,
205 edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or);
208 static inline void set_bits(int offset, int len, unsigned long *p)
210 for (; len > 0; len--)
211 set_bit(offset + (len - 1), p);
214 static inline void clear_bits(int offset, int len, unsigned long *p)
216 for (; len > 0; len--)
217 clear_bit(offset + (len - 1), p);
220 /*****************************************************************************/
222 /* actual number of DMA channels and slots on this silicon */
224 /* how many dma resources of each type */
225 unsigned num_channels;
230 enum dma_event_q default_queue;
232 /* list of channels with no even trigger; terminated by "-1" */
235 /* The edma_inuse bit for each PaRAM slot is clear unless the
236 * channel is in use ... by ARM or DSP, for QDMA, or whatever.
238 DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
240 /* The edma_unused bit for each channel is clear unless
241 * it is not being used on this platform. It uses a bit
242 * of SOC-specific initialization code.
244 DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
246 unsigned irq_res_start;
247 unsigned irq_res_end;
249 struct dma_interrupt_data {
250 void (*callback)(unsigned channel, unsigned short ch_status,
253 } intr_data[EDMA_MAX_DMACH];
256 static struct edma *edma_cc[EDMA_MAX_CC];
257 static int arch_num_cc;
259 /* dummy param set used to (re)initialize parameter RAM slots */
260 static const struct edmacc_param dummy_paramset = {
261 .link_bcntrld = 0xffff,
265 /*****************************************************************************/
267 static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
268 enum dma_event_q queue_no)
270 int bit = (ch_no & 0x7) * 4;
272 /* default to low priority queue */
273 if (queue_no == EVENTQ_DEFAULT)
274 queue_no = edma_cc[ctlr]->default_queue;
277 edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3),
278 ~(0x7 << bit), queue_no << bit);
281 static void __init map_queue_tc(unsigned ctlr, int queue_no, int tc_no)
283 int bit = queue_no * 4;
284 edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit));
287 static void __init assign_priority_to_queue(unsigned ctlr, int queue_no,
290 int bit = queue_no * 4;
291 edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit),
292 ((priority & 0x7) << bit));
296 * map_dmach_param - Maps channel number to param entry number
298 * This maps the dma channel number to param entry numberter. In
299 * other words using the DMA channel mapping registers a param entry
300 * can be mapped to any channel
302 * Callers are responsible for ensuring the channel mapping logic is
303 * included in that particular EDMA variant (Eg : dm646x)
306 static void __init map_dmach_param(unsigned ctlr)
309 for (i = 0; i < EDMA_MAX_DMACH; i++)
310 edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5));
314 setup_dma_interrupt(unsigned lch,
315 void (*callback)(unsigned channel, u16 ch_status, void *data),
320 ctlr = EDMA_CTLR(lch);
321 lch = EDMA_CHAN_SLOT(lch);
324 edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
327 edma_cc[ctlr]->intr_data[lch].callback = callback;
328 edma_cc[ctlr]->intr_data[lch].data = data;
331 edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
333 edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5,
338 static int irq2ctlr(int irq)
340 if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end)
342 else if (irq >= edma_cc[1]->irq_res_start &&
343 irq <= edma_cc[1]->irq_res_end)
349 /******************************************************************************
351 * DMA interrupt handler
353 *****************************************************************************/
354 static irqreturn_t dma_irq_handler(int irq, void *data)
361 ctlr = irq2ctlr(irq);
365 dev_dbg(data, "dma_irq_handler\n");
367 sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 0);
369 sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 1);
372 sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 1);
375 sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 0);
383 dev_dbg(data, "IPR%d %08x\n", bank, sh_ipr);
385 slot = __ffs(sh_ipr);
386 sh_ipr &= ~(BIT(slot));
388 if (sh_ier & BIT(slot)) {
389 channel = (bank << 5) | slot;
390 /* Clear the corresponding IPR bits */
391 edma_shadow0_write_array(ctlr, SH_ICR, bank,
393 if (edma_cc[ctlr]->intr_data[channel].callback)
394 edma_cc[ctlr]->intr_data[channel].callback(
395 channel, DMA_COMPLETE,
396 edma_cc[ctlr]->intr_data[channel].data);
400 edma_shadow0_write(ctlr, SH_IEVAL, 1);
404 /******************************************************************************
406 * DMA error interrupt handler
408 *****************************************************************************/
409 static irqreturn_t dma_ccerr_handler(int irq, void *data)
413 unsigned int cnt = 0;
415 ctlr = irq2ctlr(irq);
419 dev_dbg(data, "dma_ccerr_handler\n");
421 if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
422 (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
423 (edma_read(ctlr, EDMA_QEMR) == 0) &&
424 (edma_read(ctlr, EDMA_CCERR) == 0))
429 if (edma_read_array(ctlr, EDMA_EMR, 0))
431 else if (edma_read_array(ctlr, EDMA_EMR, 1))
434 dev_dbg(data, "EMR%d %08x\n", j,
435 edma_read_array(ctlr, EDMA_EMR, j));
436 for (i = 0; i < 32; i++) {
437 int k = (j << 5) + i;
438 if (edma_read_array(ctlr, EDMA_EMR, j) &
440 /* Clear the corresponding EMR bits */
441 edma_write_array(ctlr, EDMA_EMCR, j,
444 edma_shadow0_write_array(ctlr, SH_SECR,
446 if (edma_cc[ctlr]->intr_data[k].
448 edma_cc[ctlr]->intr_data[k].
451 edma_cc[ctlr]->intr_data
456 } else if (edma_read(ctlr, EDMA_QEMR)) {
457 dev_dbg(data, "QEMR %02x\n",
458 edma_read(ctlr, EDMA_QEMR));
459 for (i = 0; i < 8; i++) {
460 if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) {
461 /* Clear the corresponding IPR bits */
462 edma_write(ctlr, EDMA_QEMCR, BIT(i));
463 edma_shadow0_write(ctlr, SH_QSECR,
466 /* NOTE: not reported!! */
469 } else if (edma_read(ctlr, EDMA_CCERR)) {
470 dev_dbg(data, "CCERR %08x\n",
471 edma_read(ctlr, EDMA_CCERR));
472 /* FIXME: CCERR.BIT(16) ignored! much better
473 * to just write CCERRCLR with CCERR value...
475 for (i = 0; i < 8; i++) {
476 if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) {
477 /* Clear the corresponding IPR bits */
478 edma_write(ctlr, EDMA_CCERRCLR, BIT(i));
480 /* NOTE: not reported!! */
484 if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
485 (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
486 (edma_read(ctlr, EDMA_QEMR) == 0) &&
487 (edma_read(ctlr, EDMA_CCERR) == 0))
493 edma_write(ctlr, EDMA_EEVAL, 1);
497 static int reserve_contiguous_slots(int ctlr, unsigned int id,
498 unsigned int num_slots,
499 unsigned int start_slot)
502 unsigned int count = num_slots;
503 int stop_slot = start_slot;
504 DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY);
506 for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) {
507 j = EDMA_CHAN_SLOT(i);
508 if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) {
509 /* Record our current beginning slot */
510 if (count == num_slots)
514 set_bit(j, tmp_inuse);
519 clear_bit(j, tmp_inuse);
521 if (id == EDMA_CONT_PARAMS_FIXED_EXACT) {
531 * We have to clear any bits that we set
532 * if we run out parameter RAM slots, i.e we do find a set
533 * of contiguous parameter RAM slots but do not find the exact number
534 * requested as we may reach the total number of parameter RAM slots
536 if (i == edma_cc[ctlr]->num_slots)
540 for_each_set_bit_from(j, tmp_inuse, stop_slot)
541 clear_bit(j, edma_cc[ctlr]->edma_inuse);
546 for (j = i - num_slots + 1; j <= i; ++j)
547 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j),
548 &dummy_paramset, PARM_SIZE);
550 return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1);
553 static int prepare_unused_channel_list(struct device *dev, void *data)
555 struct platform_device *pdev = to_platform_device(dev);
558 for (i = 0; i < pdev->num_resources; i++) {
559 if ((pdev->resource[i].flags & IORESOURCE_DMA) &&
560 (int)pdev->resource[i].start >= 0) {
561 ctlr = EDMA_CTLR(pdev->resource[i].start);
562 clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
563 edma_cc[ctlr]->edma_unused);
570 /*-----------------------------------------------------------------------*/
572 static bool unused_chan_list_done;
574 /* Resource alloc/free: dma channels, parameter RAM slots */
577 * edma_alloc_channel - allocate DMA channel and paired parameter RAM
578 * @channel: specific channel to allocate; negative for "any unmapped channel"
579 * @callback: optional; to be issued on DMA completion or errors
580 * @data: passed to callback
581 * @eventq_no: an EVENTQ_* constant, used to choose which Transfer
582 * Controller (TC) executes requests using this channel. Use
583 * EVENTQ_DEFAULT unless you really need a high priority queue.
585 * This allocates a DMA channel and its associated parameter RAM slot.
586 * The parameter RAM is initialized to hold a dummy transfer.
588 * Normal use is to pass a specific channel number as @channel, to make
589 * use of hardware events mapped to that channel. When the channel will
590 * be used only for software triggering or event chaining, channels not
591 * mapped to hardware events (or mapped to unused events) are preferable.
593 * DMA transfers start from a channel using edma_start(), or by
594 * chaining. When the transfer described in that channel's parameter RAM
595 * slot completes, that slot's data may be reloaded through a link.
597 * DMA errors are only reported to the @callback associated with the
598 * channel driving that transfer, but transfer completion callbacks can
599 * be sent to another channel under control of the TCC field in
600 * the option word of the transfer's parameter RAM set. Drivers must not
601 * use DMA transfer completion callbacks for channels they did not allocate.
602 * (The same applies to TCC codes used in transfer chaining.)
604 * Returns the number of the channel, else negative errno.
606 int edma_alloc_channel(int channel,
607 void (*callback)(unsigned channel, u16 ch_status, void *data),
609 enum dma_event_q eventq_no)
611 unsigned i, done = 0, ctlr = 0;
614 if (!unused_chan_list_done) {
616 * Scan all the platform devices to find out the EDMA channels
617 * used and clear them in the unused list, making the rest
618 * available for ARM usage.
620 ret = bus_for_each_dev(&platform_bus_type, NULL, NULL,
621 prepare_unused_channel_list);
625 unused_chan_list_done = true;
629 ctlr = EDMA_CTLR(channel);
630 channel = EDMA_CHAN_SLOT(channel);
634 for (i = 0; i < arch_num_cc; i++) {
637 channel = find_next_bit(edma_cc[i]->edma_unused,
638 edma_cc[i]->num_channels,
640 if (channel == edma_cc[i]->num_channels)
642 if (!test_and_set_bit(channel,
643 edma_cc[i]->edma_inuse)) {
655 } else if (channel >= edma_cc[ctlr]->num_channels) {
657 } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) {
661 /* ensure access through shadow region 0 */
662 edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
664 /* ensure no events are pending */
665 edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
666 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
667 &dummy_paramset, PARM_SIZE);
670 setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel),
673 map_dmach_queue(ctlr, channel, eventq_no);
675 return EDMA_CTLR_CHAN(ctlr, channel);
677 EXPORT_SYMBOL(edma_alloc_channel);
681 * edma_free_channel - deallocate DMA channel
682 * @channel: dma channel returned from edma_alloc_channel()
684 * This deallocates the DMA channel and associated parameter RAM slot
685 * allocated by edma_alloc_channel().
687 * Callers are responsible for ensuring the channel is inactive, and
688 * will not be reactivated by linking, chaining, or software calls to
691 void edma_free_channel(unsigned channel)
695 ctlr = EDMA_CTLR(channel);
696 channel = EDMA_CHAN_SLOT(channel);
698 if (channel >= edma_cc[ctlr]->num_channels)
701 setup_dma_interrupt(channel, NULL, NULL);
702 /* REVISIT should probably take out of shadow region 0 */
704 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
705 &dummy_paramset, PARM_SIZE);
706 clear_bit(channel, edma_cc[ctlr]->edma_inuse);
708 EXPORT_SYMBOL(edma_free_channel);
711 * edma_alloc_slot - allocate DMA parameter RAM
712 * @slot: specific slot to allocate; negative for "any unused slot"
714 * This allocates a parameter RAM slot, initializing it to hold a
715 * dummy transfer. Slots allocated using this routine have not been
716 * mapped to a hardware DMA channel, and will normally be used by
717 * linking to them from a slot associated with a DMA channel.
719 * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
720 * slots may be allocated on behalf of DSP firmware.
722 * Returns the number of the slot, else negative errno.
724 int edma_alloc_slot(unsigned ctlr, int slot)
730 slot = EDMA_CHAN_SLOT(slot);
733 slot = edma_cc[ctlr]->num_channels;
735 slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse,
736 edma_cc[ctlr]->num_slots, slot);
737 if (slot == edma_cc[ctlr]->num_slots)
739 if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse))
742 } else if (slot < edma_cc[ctlr]->num_channels ||
743 slot >= edma_cc[ctlr]->num_slots) {
745 } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) {
749 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
750 &dummy_paramset, PARM_SIZE);
752 return EDMA_CTLR_CHAN(ctlr, slot);
754 EXPORT_SYMBOL(edma_alloc_slot);
757 * edma_free_slot - deallocate DMA parameter RAM
758 * @slot: parameter RAM slot returned from edma_alloc_slot()
760 * This deallocates the parameter RAM slot allocated by edma_alloc_slot().
761 * Callers are responsible for ensuring the slot is inactive, and will
764 void edma_free_slot(unsigned slot)
768 ctlr = EDMA_CTLR(slot);
769 slot = EDMA_CHAN_SLOT(slot);
771 if (slot < edma_cc[ctlr]->num_channels ||
772 slot >= edma_cc[ctlr]->num_slots)
775 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
776 &dummy_paramset, PARM_SIZE);
777 clear_bit(slot, edma_cc[ctlr]->edma_inuse);
779 EXPORT_SYMBOL(edma_free_slot);
783 * edma_alloc_cont_slots- alloc contiguous parameter RAM slots
784 * The API will return the starting point of a set of
785 * contiguous parameter RAM slots that have been requested
787 * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT
788 * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
789 * @count: number of contiguous Paramter RAM slots
790 * @slot - the start value of Parameter RAM slot that should be passed if id
791 * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
793 * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of
794 * contiguous Parameter RAM slots from parameter RAM 64 in the case of
795 * DaVinci SOCs and 32 in the case of DA8xx SOCs.
797 * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a
798 * set of contiguous parameter RAM slots from the "slot" that is passed as an
799 * argument to the API.
801 * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries
802 * starts looking for a set of contiguous parameter RAMs from the "slot"
803 * that is passed as an argument to the API. On failure the API will try to
804 * find a set of contiguous Parameter RAM slots from the remaining Parameter
807 int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
810 * The start slot requested should be greater than
811 * the number of channels and lesser than the total number
814 if ((id != EDMA_CONT_PARAMS_ANY) &&
815 (slot < edma_cc[ctlr]->num_channels ||
816 slot >= edma_cc[ctlr]->num_slots))
820 * The number of parameter RAM slots requested cannot be less than 1
821 * and cannot be more than the number of slots minus the number of
824 if (count < 1 || count >
825 (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels))
829 case EDMA_CONT_PARAMS_ANY:
830 return reserve_contiguous_slots(ctlr, id, count,
831 edma_cc[ctlr]->num_channels);
832 case EDMA_CONT_PARAMS_FIXED_EXACT:
833 case EDMA_CONT_PARAMS_FIXED_NOT_EXACT:
834 return reserve_contiguous_slots(ctlr, id, count, slot);
840 EXPORT_SYMBOL(edma_alloc_cont_slots);
843 * edma_free_cont_slots - deallocate DMA parameter RAM slots
844 * @slot: first parameter RAM of a set of parameter RAM slots to be freed
845 * @count: the number of contiguous parameter RAM slots to be freed
847 * This deallocates the parameter RAM slots allocated by
848 * edma_alloc_cont_slots.
849 * Callers/applications need to keep track of sets of contiguous
850 * parameter RAM slots that have been allocated using the edma_alloc_cont_slots
852 * Callers are responsible for ensuring the slots are inactive, and will
855 int edma_free_cont_slots(unsigned slot, int count)
857 unsigned ctlr, slot_to_free;
860 ctlr = EDMA_CTLR(slot);
861 slot = EDMA_CHAN_SLOT(slot);
863 if (slot < edma_cc[ctlr]->num_channels ||
864 slot >= edma_cc[ctlr]->num_slots ||
868 for (i = slot; i < slot + count; ++i) {
870 slot_to_free = EDMA_CHAN_SLOT(i);
872 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free),
873 &dummy_paramset, PARM_SIZE);
874 clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse);
879 EXPORT_SYMBOL(edma_free_cont_slots);
881 /*-----------------------------------------------------------------------*/
883 /* Parameter RAM operations (i) -- read/write partial slots */
886 * edma_set_src - set initial DMA source address in parameter RAM slot
887 * @slot: parameter RAM slot being configured
888 * @src_port: physical address of source (memory, controller FIFO, etc)
889 * @addressMode: INCR, except in very rare cases
890 * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
891 * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
893 * Note that the source address is modified during the DMA transfer
894 * according to edma_set_src_index().
896 void edma_set_src(unsigned slot, dma_addr_t src_port,
897 enum address_mode mode, enum fifo_width width)
901 ctlr = EDMA_CTLR(slot);
902 slot = EDMA_CHAN_SLOT(slot);
904 if (slot < edma_cc[ctlr]->num_slots) {
905 unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
908 /* set SAM and program FWID */
909 i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8));
914 edma_parm_write(ctlr, PARM_OPT, slot, i);
916 /* set the source port address
917 in source register of param structure */
918 edma_parm_write(ctlr, PARM_SRC, slot, src_port);
921 EXPORT_SYMBOL(edma_set_src);
924 * edma_set_dest - set initial DMA destination address in parameter RAM slot
925 * @slot: parameter RAM slot being configured
926 * @dest_port: physical address of destination (memory, controller FIFO, etc)
927 * @addressMode: INCR, except in very rare cases
928 * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
929 * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
931 * Note that the destination address is modified during the DMA transfer
932 * according to edma_set_dest_index().
934 void edma_set_dest(unsigned slot, dma_addr_t dest_port,
935 enum address_mode mode, enum fifo_width width)
939 ctlr = EDMA_CTLR(slot);
940 slot = EDMA_CHAN_SLOT(slot);
942 if (slot < edma_cc[ctlr]->num_slots) {
943 unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
946 /* set DAM and program FWID */
947 i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8));
952 edma_parm_write(ctlr, PARM_OPT, slot, i);
953 /* set the destination port address
954 in dest register of param structure */
955 edma_parm_write(ctlr, PARM_DST, slot, dest_port);
958 EXPORT_SYMBOL(edma_set_dest);
961 * edma_get_position - returns the current transfer points
962 * @slot: parameter RAM slot being examined
963 * @src: pointer to source port position
964 * @dst: pointer to destination port position
966 * Returns current source and destination addresses for a particular
967 * parameter RAM slot. Its channel should not be active when this is called.
969 void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst)
971 struct edmacc_param temp;
974 ctlr = EDMA_CTLR(slot);
975 slot = EDMA_CHAN_SLOT(slot);
977 edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp);
983 EXPORT_SYMBOL(edma_get_position);
986 * edma_set_src_index - configure DMA source address indexing
987 * @slot: parameter RAM slot being configured
988 * @src_bidx: byte offset between source arrays in a frame
989 * @src_cidx: byte offset between source frames in a block
991 * Offsets are specified to support either contiguous or discontiguous
992 * memory transfers, or repeated access to a hardware register, as needed.
993 * When accessing hardware registers, both offsets are normally zero.
995 void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx)
999 ctlr = EDMA_CTLR(slot);
1000 slot = EDMA_CHAN_SLOT(slot);
1002 if (slot < edma_cc[ctlr]->num_slots) {
1003 edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
1004 0xffff0000, src_bidx);
1005 edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
1006 0xffff0000, src_cidx);
1009 EXPORT_SYMBOL(edma_set_src_index);
1012 * edma_set_dest_index - configure DMA destination address indexing
1013 * @slot: parameter RAM slot being configured
1014 * @dest_bidx: byte offset between destination arrays in a frame
1015 * @dest_cidx: byte offset between destination frames in a block
1017 * Offsets are specified to support either contiguous or discontiguous
1018 * memory transfers, or repeated access to a hardware register, as needed.
1019 * When accessing hardware registers, both offsets are normally zero.
1021 void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx)
1025 ctlr = EDMA_CTLR(slot);
1026 slot = EDMA_CHAN_SLOT(slot);
1028 if (slot < edma_cc[ctlr]->num_slots) {
1029 edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
1030 0x0000ffff, dest_bidx << 16);
1031 edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
1032 0x0000ffff, dest_cidx << 16);
1035 EXPORT_SYMBOL(edma_set_dest_index);
1038 * edma_set_transfer_params - configure DMA transfer parameters
1039 * @slot: parameter RAM slot being configured
1040 * @acnt: how many bytes per array (at least one)
1041 * @bcnt: how many arrays per frame (at least one)
1042 * @ccnt: how many frames per block (at least one)
1043 * @bcnt_rld: used only for A-Synchronized transfers; this specifies
1044 * the value to reload into bcnt when it decrements to zero
1045 * @sync_mode: ASYNC or ABSYNC
1047 * See the EDMA3 documentation to understand how to configure and link
1048 * transfers using the fields in PaRAM slots. If you are not doing it
1049 * all at once with edma_write_slot(), you will use this routine
1050 * plus two calls each for source and destination, setting the initial
1051 * address and saying how to index that address.
1053 * An example of an A-Synchronized transfer is a serial link using a
1054 * single word shift register. In that case, @acnt would be equal to
1055 * that word size; the serial controller issues a DMA synchronization
1056 * event to transfer each word, and memory access by the DMA transfer
1057 * controller will be word-at-a-time.
1059 * An example of an AB-Synchronized transfer is a device using a FIFO.
1060 * In that case, @acnt equals the FIFO width and @bcnt equals its depth.
1061 * The controller with the FIFO issues DMA synchronization events when
1062 * the FIFO threshold is reached, and the DMA transfer controller will
1063 * transfer one frame to (or from) the FIFO. It will probably use
1064 * efficient burst modes to access memory.
1066 void edma_set_transfer_params(unsigned slot,
1067 u16 acnt, u16 bcnt, u16 ccnt,
1068 u16 bcnt_rld, enum sync_dimension sync_mode)
1072 ctlr = EDMA_CTLR(slot);
1073 slot = EDMA_CHAN_SLOT(slot);
1075 if (slot < edma_cc[ctlr]->num_slots) {
1076 edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot,
1077 0x0000ffff, bcnt_rld << 16);
1078 if (sync_mode == ASYNC)
1079 edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM);
1081 edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM);
1082 /* Set the acount, bcount, ccount registers */
1083 edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt);
1084 edma_parm_write(ctlr, PARM_CCNT, slot, ccnt);
1087 EXPORT_SYMBOL(edma_set_transfer_params);
1090 * edma_link - link one parameter RAM slot to another
1091 * @from: parameter RAM slot originating the link
1092 * @to: parameter RAM slot which is the link target
1094 * The originating slot should not be part of any active DMA transfer.
1096 void edma_link(unsigned from, unsigned to)
1098 unsigned ctlr_from, ctlr_to;
1100 ctlr_from = EDMA_CTLR(from);
1101 from = EDMA_CHAN_SLOT(from);
1102 ctlr_to = EDMA_CTLR(to);
1103 to = EDMA_CHAN_SLOT(to);
1105 if (from >= edma_cc[ctlr_from]->num_slots)
1107 if (to >= edma_cc[ctlr_to]->num_slots)
1109 edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000,
1112 EXPORT_SYMBOL(edma_link);
1115 * edma_unlink - cut link from one parameter RAM slot
1116 * @from: parameter RAM slot originating the link
1118 * The originating slot should not be part of any active DMA transfer.
1119 * Its link is set to 0xffff.
1121 void edma_unlink(unsigned from)
1125 ctlr = EDMA_CTLR(from);
1126 from = EDMA_CHAN_SLOT(from);
1128 if (from >= edma_cc[ctlr]->num_slots)
1130 edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff);
1132 EXPORT_SYMBOL(edma_unlink);
1134 /*-----------------------------------------------------------------------*/
1136 /* Parameter RAM operations (ii) -- read/write whole parameter sets */
1139 * edma_write_slot - write parameter RAM data for slot
1140 * @slot: number of parameter RAM slot being modified
1141 * @param: data to be written into parameter RAM slot
1143 * Use this to assign all parameters of a transfer at once. This
1144 * allows more efficient setup of transfers than issuing multiple
1145 * calls to set up those parameters in small pieces, and provides
1146 * complete control over all transfer options.
1148 void edma_write_slot(unsigned slot, const struct edmacc_param *param)
1152 ctlr = EDMA_CTLR(slot);
1153 slot = EDMA_CHAN_SLOT(slot);
1155 if (slot >= edma_cc[ctlr]->num_slots)
1157 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param,
1160 EXPORT_SYMBOL(edma_write_slot);
1163 * edma_read_slot - read parameter RAM data from slot
1164 * @slot: number of parameter RAM slot being copied
1165 * @param: where to store copy of parameter RAM data
1167 * Use this to read data from a parameter RAM slot, perhaps to
1168 * save them as a template for later reuse.
1170 void edma_read_slot(unsigned slot, struct edmacc_param *param)
1174 ctlr = EDMA_CTLR(slot);
1175 slot = EDMA_CHAN_SLOT(slot);
1177 if (slot >= edma_cc[ctlr]->num_slots)
1179 memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
1182 EXPORT_SYMBOL(edma_read_slot);
1184 /*-----------------------------------------------------------------------*/
1186 /* Various EDMA channel control operations */
1189 * edma_pause - pause dma on a channel
1190 * @channel: on which edma_start() has been called
1192 * This temporarily disables EDMA hardware events on the specified channel,
1193 * preventing them from triggering new transfers on its behalf
1195 void edma_pause(unsigned channel)
1199 ctlr = EDMA_CTLR(channel);
1200 channel = EDMA_CHAN_SLOT(channel);
1202 if (channel < edma_cc[ctlr]->num_channels) {
1203 unsigned int mask = BIT(channel & 0x1f);
1205 edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
1208 EXPORT_SYMBOL(edma_pause);
1211 * edma_resume - resumes dma on a paused channel
1212 * @channel: on which edma_pause() has been called
1214 * This re-enables EDMA hardware events on the specified channel.
1216 void edma_resume(unsigned channel)
1220 ctlr = EDMA_CTLR(channel);
1221 channel = EDMA_CHAN_SLOT(channel);
1223 if (channel < edma_cc[ctlr]->num_channels) {
1224 unsigned int mask = BIT(channel & 0x1f);
1226 edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
1229 EXPORT_SYMBOL(edma_resume);
1232 * edma_start - start dma on a channel
1233 * @channel: channel being activated
1235 * Channels with event associations will be triggered by their hardware
1236 * events, and channels without such associations will be triggered by
1237 * software. (At this writing there is no interface for using software
1238 * triggers except with channels that don't support hardware triggers.)
1240 * Returns zero on success, else negative errno.
1242 int edma_start(unsigned channel)
1246 ctlr = EDMA_CTLR(channel);
1247 channel = EDMA_CHAN_SLOT(channel);
1249 if (channel < edma_cc[ctlr]->num_channels) {
1250 int j = channel >> 5;
1251 unsigned int mask = BIT(channel & 0x1f);
1253 /* EDMA channels without event association */
1254 if (test_bit(channel, edma_cc[ctlr]->edma_unused)) {
1255 pr_debug("EDMA: ESR%d %08x\n", j,
1256 edma_shadow0_read_array(ctlr, SH_ESR, j));
1257 edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
1261 /* EDMA channel with event association */
1262 pr_debug("EDMA: ER%d %08x\n", j,
1263 edma_shadow0_read_array(ctlr, SH_ER, j));
1264 /* Clear any pending event or error */
1265 edma_write_array(ctlr, EDMA_ECR, j, mask);
1266 edma_write_array(ctlr, EDMA_EMCR, j, mask);
1268 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1269 edma_shadow0_write_array(ctlr, SH_EESR, j, mask);
1270 pr_debug("EDMA: EER%d %08x\n", j,
1271 edma_shadow0_read_array(ctlr, SH_EER, j));
1277 EXPORT_SYMBOL(edma_start);
1280 * edma_stop - stops dma on the channel passed
1281 * @channel: channel being deactivated
1283 * When @lch is a channel, any active transfer is paused and
1284 * all pending hardware events are cleared. The current transfer
1285 * may not be resumed, and the channel's Parameter RAM should be
1286 * reinitialized before being reused.
1288 void edma_stop(unsigned channel)
1292 ctlr = EDMA_CTLR(channel);
1293 channel = EDMA_CHAN_SLOT(channel);
1295 if (channel < edma_cc[ctlr]->num_channels) {
1296 int j = channel >> 5;
1297 unsigned int mask = BIT(channel & 0x1f);
1299 edma_shadow0_write_array(ctlr, SH_EECR, j, mask);
1300 edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
1301 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1302 edma_write_array(ctlr, EDMA_EMCR, j, mask);
1304 pr_debug("EDMA: EER%d %08x\n", j,
1305 edma_shadow0_read_array(ctlr, SH_EER, j));
1307 /* REVISIT: consider guarding against inappropriate event
1308 * chaining by overwriting with dummy_paramset.
1312 EXPORT_SYMBOL(edma_stop);
1314 /******************************************************************************
1316 * It cleans ParamEntry qand bring back EDMA to initial state if media has
1317 * been removed before EDMA has finished.It is usedful for removable media.
1319 * ch_no - channel no
1321 * Return: zero on success, or corresponding error no on failure
1323 * FIXME this should not be needed ... edma_stop() should suffice.
1325 *****************************************************************************/
1327 void edma_clean_channel(unsigned channel)
1331 ctlr = EDMA_CTLR(channel);
1332 channel = EDMA_CHAN_SLOT(channel);
1334 if (channel < edma_cc[ctlr]->num_channels) {
1335 int j = (channel >> 5);
1336 unsigned int mask = BIT(channel & 0x1f);
1338 pr_debug("EDMA: EMR%d %08x\n", j,
1339 edma_read_array(ctlr, EDMA_EMR, j));
1340 edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
1341 /* Clear the corresponding EMR bits */
1342 edma_write_array(ctlr, EDMA_EMCR, j, mask);
1344 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1345 edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
1348 EXPORT_SYMBOL(edma_clean_channel);
1351 * edma_clear_event - clear an outstanding event on the DMA channel
1353 * channel - channel number
1355 void edma_clear_event(unsigned channel)
1359 ctlr = EDMA_CTLR(channel);
1360 channel = EDMA_CHAN_SLOT(channel);
1362 if (channel >= edma_cc[ctlr]->num_channels)
1365 edma_write(ctlr, EDMA_ECR, BIT(channel));
1367 edma_write(ctlr, EDMA_ECRH, BIT(channel - 32));
1369 EXPORT_SYMBOL(edma_clear_event);
1371 /*-----------------------------------------------------------------------*/
1373 static int __init edma_probe(struct platform_device *pdev)
1375 struct edma_soc_info **info = pdev->dev.platform_data;
1376 const s8 (*queue_priority_mapping)[2];
1377 const s8 (*queue_tc_mapping)[2];
1378 int i, j, off, ln, found = 0;
1380 const s16 (*rsv_chans)[2];
1381 const s16 (*rsv_slots)[2];
1382 int irq[EDMA_MAX_CC] = {0, 0};
1383 int err_irq[EDMA_MAX_CC] = {0, 0};
1384 struct resource *r[EDMA_MAX_CC] = {NULL};
1385 resource_size_t len[EDMA_MAX_CC];
1392 for (j = 0; j < EDMA_MAX_CC; j++) {
1393 sprintf(res_name, "edma_cc%d", j);
1394 r[j] = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1396 if (!r[j] || !info[j]) {
1405 len[j] = resource_size(r[j]);
1407 r[j] = request_mem_region(r[j]->start, len[j],
1408 dev_name(&pdev->dev));
1414 edmacc_regs_base[j] = ioremap(r[j]->start, len[j]);
1415 if (!edmacc_regs_base[j]) {
1420 edma_cc[j] = kzalloc(sizeof(struct edma), GFP_KERNEL);
1426 edma_cc[j]->num_channels = min_t(unsigned, info[j]->n_channel,
1428 edma_cc[j]->num_slots = min_t(unsigned, info[j]->n_slot,
1429 EDMA_MAX_PARAMENTRY);
1430 edma_cc[j]->num_cc = min_t(unsigned, info[j]->n_cc,
1433 edma_cc[j]->default_queue = info[j]->default_queue;
1435 dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
1436 edmacc_regs_base[j]);
1438 for (i = 0; i < edma_cc[j]->num_slots; i++)
1439 memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i),
1440 &dummy_paramset, PARM_SIZE);
1442 /* Mark all channels as unused */
1443 memset(edma_cc[j]->edma_unused, 0xff,
1444 sizeof(edma_cc[j]->edma_unused));
1448 /* Clear the reserved channels in unused list */
1449 rsv_chans = info[j]->rsv->rsv_chans;
1451 for (i = 0; rsv_chans[i][0] != -1; i++) {
1452 off = rsv_chans[i][0];
1453 ln = rsv_chans[i][1];
1455 edma_cc[j]->edma_unused);
1459 /* Set the reserved slots in inuse list */
1460 rsv_slots = info[j]->rsv->rsv_slots;
1462 for (i = 0; rsv_slots[i][0] != -1; i++) {
1463 off = rsv_slots[i][0];
1464 ln = rsv_slots[i][1];
1466 edma_cc[j]->edma_inuse);
1471 sprintf(irq_name, "edma%d", j);
1472 irq[j] = platform_get_irq_byname(pdev, irq_name);
1473 edma_cc[j]->irq_res_start = irq[j];
1474 status = request_irq(irq[j], dma_irq_handler, 0, "edma",
1477 dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
1482 sprintf(irq_name, "edma%d_err", j);
1483 err_irq[j] = platform_get_irq_byname(pdev, irq_name);
1484 edma_cc[j]->irq_res_end = err_irq[j];
1485 status = request_irq(err_irq[j], dma_ccerr_handler, 0,
1486 "edma_error", &pdev->dev);
1488 dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
1489 err_irq[j], status);
1493 for (i = 0; i < edma_cc[j]->num_channels; i++)
1494 map_dmach_queue(j, i, info[j]->default_queue);
1496 queue_tc_mapping = info[j]->queue_tc_mapping;
1497 queue_priority_mapping = info[j]->queue_priority_mapping;
1499 /* Event queue to TC mapping */
1500 for (i = 0; queue_tc_mapping[i][0] != -1; i++)
1501 map_queue_tc(j, queue_tc_mapping[i][0],
1502 queue_tc_mapping[i][1]);
1504 /* Event queue priority mapping */
1505 for (i = 0; queue_priority_mapping[i][0] != -1; i++)
1506 assign_priority_to_queue(j,
1507 queue_priority_mapping[i][0],
1508 queue_priority_mapping[i][1]);
1510 /* Map the channel to param entry if channel mapping logic
1513 if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)
1516 for (i = 0; i < info[j]->n_region; i++) {
1517 edma_write_array2(j, EDMA_DRAE, i, 0, 0x0);
1518 edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
1519 edma_write_array(j, EDMA_QRAE, i, 0x0);
1527 for (i = 0; i < EDMA_MAX_CC; i++) {
1529 free_irq(err_irq[i], &pdev->dev);
1531 free_irq(irq[i], &pdev->dev);
1534 for (i = 0; i < EDMA_MAX_CC; i++) {
1536 release_mem_region(r[i]->start, len[i]);
1537 if (edmacc_regs_base[i])
1538 iounmap(edmacc_regs_base[i]);
1545 static struct platform_driver edma_driver = {
1546 .driver.name = "edma",
1549 static int __init edma_init(void)
1551 return platform_driver_probe(&edma_driver, edma_probe);
1553 arch_initcall(edma_init);