2 * linux/arch/arm/common/it8152.c
4 * Copyright Compulab Ltd, 2002-2007
5 * Mike Rapoport <mike@compulab.co.il>
7 * The DMA bouncing part is taken from arch/arm/mach-ixp4xx/common-pci.c
8 * (see this file for respective copyrights)
10 * Thanks to Guennadi Liakhovetski <gl@dsa-ac.de> for IRQ enumberation
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/ptrace.h>
22 #include <linux/interrupt.h>
24 #include <linux/init.h>
25 #include <linux/ioport.h>
26 #include <linux/irq.h>
29 #include <asm/mach/pci.h>
30 #include <asm/hardware/it8152.h>
34 static void it8152_mask_irq(struct irq_data *d)
36 unsigned int irq = d->irq;
38 if (irq >= IT8152_LD_IRQ(0)) {
39 __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) |
40 (1 << (irq - IT8152_LD_IRQ(0)))),
42 } else if (irq >= IT8152_LP_IRQ(0)) {
43 __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) |
44 (1 << (irq - IT8152_LP_IRQ(0)))),
46 } else if (irq >= IT8152_PD_IRQ(0)) {
47 __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) |
48 (1 << (irq - IT8152_PD_IRQ(0)))),
53 static void it8152_unmask_irq(struct irq_data *d)
55 unsigned int irq = d->irq;
57 if (irq >= IT8152_LD_IRQ(0)) {
58 __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) &
59 ~(1 << (irq - IT8152_LD_IRQ(0)))),
61 } else if (irq >= IT8152_LP_IRQ(0)) {
62 __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) &
63 ~(1 << (irq - IT8152_LP_IRQ(0)))),
65 } else if (irq >= IT8152_PD_IRQ(0)) {
66 __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) &
67 ~(1 << (irq - IT8152_PD_IRQ(0)))),
72 static struct irq_chip it8152_irq_chip = {
74 .irq_ack = it8152_mask_irq,
75 .irq_mask = it8152_mask_irq,
76 .irq_unmask = it8152_unmask_irq,
79 void it8152_init_irq(void)
83 __raw_writel((0xffff), IT8152_INTC_PDCNIMR);
84 __raw_writel((0), IT8152_INTC_PDCNIRR);
85 __raw_writel((0xffff), IT8152_INTC_LPCNIMR);
86 __raw_writel((0), IT8152_INTC_LPCNIRR);
87 __raw_writel((0xffff), IT8152_INTC_LDCNIMR);
88 __raw_writel((0), IT8152_INTC_LDCNIRR);
90 for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) {
91 irq_set_chip_and_handler(irq, &it8152_irq_chip,
93 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
97 void it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
99 int bits_pd, bits_lp, bits_ld;
104 bits_pd = __raw_readl(IT8152_INTC_PDCNIRR);
105 bits_lp = __raw_readl(IT8152_INTC_LPCNIRR);
106 bits_ld = __raw_readl(IT8152_INTC_LDCNIRR);
109 __raw_writel((~bits_pd), IT8152_INTC_PDCNIRR);
110 __raw_writel((~bits_lp), IT8152_INTC_LPCNIRR);
111 __raw_writel((~bits_ld), IT8152_INTC_LDCNIRR);
113 if (!(bits_ld | bits_lp | bits_pd)) {
114 /* Re-read to guarantee, that there was a moment of
115 time, when they all three were 0. */
116 bits_pd = __raw_readl(IT8152_INTC_PDCNIRR);
117 bits_lp = __raw_readl(IT8152_INTC_LPCNIRR);
118 bits_ld = __raw_readl(IT8152_INTC_LDCNIRR);
119 if (!(bits_ld | bits_lp | bits_pd))
123 bits_pd &= ((1 << IT8152_PD_IRQ_COUNT) - 1);
126 generic_handle_irq(IT8152_PD_IRQ(i));
127 bits_pd &= ~(1 << i);
130 bits_lp &= ((1 << IT8152_LP_IRQ_COUNT) - 1);
133 generic_handle_irq(IT8152_LP_IRQ(i));
134 bits_lp &= ~(1 << i);
137 bits_ld &= ((1 << IT8152_LD_IRQ_COUNT) - 1);
140 generic_handle_irq(IT8152_LD_IRQ(i));
141 bits_ld &= ~(1 << i);
146 /* mapping for on-chip devices */
147 int __init it8152_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
149 if ((dev->vendor == PCI_VENDOR_ID_ITE) &&
150 (dev->device == PCI_DEVICE_ID_ITE_8152)) {
151 if ((dev->class >> 8) == PCI_CLASS_MULTIMEDIA_AUDIO)
152 return IT8152_AUDIO_INT;
153 if ((dev->class >> 8) == PCI_CLASS_SERIAL_USB)
154 return IT8152_USB_INT;
155 if ((dev->class >> 8) == PCI_CLASS_SYSTEM_DMA)
156 return IT8152_CDMA_INT;
162 static unsigned long it8152_pci_dev_base_address(struct pci_bus *bus,
165 unsigned long addr = 0;
167 if (bus->number == 0) {
168 if (devfn < PCI_DEVFN(MAX_SLOTS, 0))
171 addr = (bus->number << 16) | (devfn << 8);
176 static int it8152_pci_read_config(struct pci_bus *bus,
177 unsigned int devfn, int where,
178 int size, u32 *value)
180 unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
186 __raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
187 v = (__raw_readl(IT8152_PCI_CFG_DATA) >> (8 * (shift)));
191 return PCIBIOS_SUCCESSFUL;
194 static int it8152_pci_write_config(struct pci_bus *bus,
195 unsigned int devfn, int where,
198 unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
199 u32 v, vtemp, mask = 0;
209 __raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
210 vtemp = __raw_readl(IT8152_PCI_CFG_DATA);
213 vtemp &= ~(mask << (8 * shift));
217 v = (value << (8 * shift));
218 __raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
219 __raw_writel((v | vtemp), IT8152_PCI_CFG_DATA);
221 return PCIBIOS_SUCCESSFUL;
224 static struct pci_ops it8152_ops = {
225 .read = it8152_pci_read_config,
226 .write = it8152_pci_write_config,
229 static struct resource it8152_io = {
230 .name = "IT8152 PCI I/O region",
231 .flags = IORESOURCE_IO,
234 static struct resource it8152_mem = {
235 .name = "IT8152 PCI memory region",
238 .flags = IORESOURCE_MEM,
242 * The following functions are needed for DMA bouncing.
243 * ITE8152 chip can address up to 64MByte, so all the devices
244 * connected to ITE8152 (PCI and USB) should have limited DMA window
246 static int it8152_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
248 dev_dbg(dev, "%s: dma_addr %08x, size %08x\n",
249 __func__, dma_addr, size);
250 return (dma_addr + size - PHYS_OFFSET) >= SZ_64M;
254 * Setup DMA mask to 64MB on devices connected to ITE8152. Ignore all
257 static int it8152_pci_platform_notify(struct device *dev)
259 if (dev->bus == &pci_bus_type) {
261 *dev->dma_mask = (SZ_64M - 1) | PHYS_OFFSET;
262 dev->coherent_dma_mask = (SZ_64M - 1) | PHYS_OFFSET;
263 dmabounce_register_dev(dev, 2048, 4096, it8152_needs_bounce);
268 static int it8152_pci_platform_notify_remove(struct device *dev)
270 if (dev->bus == &pci_bus_type)
271 dmabounce_unregister_dev(dev);
276 int dma_set_coherent_mask(struct device *dev, u64 mask)
278 if (mask >= PHYS_OFFSET + SZ_64M - 1)
284 int __init it8152_pci_setup(int nr, struct pci_sys_data *sys)
286 it8152_io.start = IT8152_IO_BASE + 0x12000;
287 it8152_io.end = IT8152_IO_BASE + 0x12000 + 0x100000;
289 sys->mem_offset = 0x10000000;
290 sys->io_offset = IT8152_IO_BASE;
292 if (request_resource(&ioport_resource, &it8152_io)) {
293 printk(KERN_ERR "PCI: unable to allocate IO region\n");
296 if (request_resource(&iomem_resource, &it8152_mem)) {
297 printk(KERN_ERR "PCI: unable to allocate memory region\n");
301 sys->resource[0] = &it8152_io;
302 sys->resource[1] = &it8152_mem;
304 if (platform_notify || platform_notify_remove) {
305 printk(KERN_ERR "PCI: Can't use platform_notify\n");
309 platform_notify = it8152_pci_platform_notify;
310 platform_notify_remove = it8152_pci_platform_notify_remove;
315 release_resource(&it8152_io);
317 release_resource(&it8152_mem);
323 * If we set up a device for bus mastering, we need to check the latency
324 * timer as we don't have even crappy BIOSes to set it properly.
325 * The implementation is from arch/i386/pci/i386.c
327 unsigned int pcibios_max_latency = 255;
329 void pcibios_set_master(struct pci_dev *dev)
333 /* no need to update on-chip OHCI controller */
334 if ((dev->vendor == PCI_VENDOR_ID_ITE) &&
335 (dev->device == PCI_DEVICE_ID_ITE_8152) &&
336 ((dev->class >> 8) == PCI_CLASS_SERIAL_USB))
339 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
341 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
342 else if (lat > pcibios_max_latency)
343 lat = pcibios_max_latency;
346 printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
348 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
352 struct pci_bus * __init it8152_pci_scan_bus(int nr, struct pci_sys_data *sys)
354 return pci_scan_bus(nr, &it8152_ops, sys);
357 EXPORT_SYMBOL(dma_set_coherent_mask);