1 /* linux/arch/arm/common/pl330.c
3 * Copyright (C) 2010 Samsung Electronics Co Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/module.h>
25 #include <linux/string.h>
27 #include <linux/delay.h>
28 #include <linux/interrupt.h>
29 #include <linux/dma-mapping.h>
31 #include <asm/hardware/pl330.h>
33 /* Register and Bit field Definitions */
35 #define DS_ST_STOP 0x0
36 #define DS_ST_EXEC 0x1
37 #define DS_ST_CMISS 0x2
38 #define DS_ST_UPDTPC 0x3
40 #define DS_ST_ATBRR 0x5
41 #define DS_ST_QBUSY 0x6
43 #define DS_ST_KILL 0x8
44 #define DS_ST_CMPLT 0x9
45 #define DS_ST_FLTCMP 0xe
46 #define DS_ST_FAULT 0xf
51 #define INTSTATUS 0x28
58 #define FTC(n) (_FTC + (n)*0x4)
61 #define CS(n) (_CS + (n)*0x8)
62 #define CS_CNS (1 << 21)
65 #define CPC(n) (_CPC + (n)*0x8)
68 #define SA(n) (_SA + (n)*0x20)
71 #define DA(n) (_DA + (n)*0x20)
74 #define CC(n) (_CC + (n)*0x20)
76 #define CC_SRCINC (1 << 0)
77 #define CC_DSTINC (1 << 14)
78 #define CC_SRCPRI (1 << 8)
79 #define CC_DSTPRI (1 << 22)
80 #define CC_SRCNS (1 << 9)
81 #define CC_DSTNS (1 << 23)
82 #define CC_SRCIA (1 << 10)
83 #define CC_DSTIA (1 << 24)
84 #define CC_SRCBRSTLEN_SHFT 4
85 #define CC_DSTBRSTLEN_SHFT 18
86 #define CC_SRCBRSTSIZE_SHFT 1
87 #define CC_DSTBRSTSIZE_SHFT 15
88 #define CC_SRCCCTRL_SHFT 11
89 #define CC_SRCCCTRL_MASK 0x7
90 #define CC_DSTCCTRL_SHFT 25
91 #define CC_DRCCCTRL_MASK 0x7
92 #define CC_SWAP_SHFT 28
95 #define LC0(n) (_LC0 + (n)*0x20)
98 #define LC1(n) (_LC1 + (n)*0x20)
100 #define DBGSTATUS 0xd00
101 #define DBG_BUSY (1 << 0)
104 #define DBGINST0 0xd08
105 #define DBGINST1 0xd0c
114 #define PERIPH_ID 0xfe0
115 #define PCELL_ID 0xff0
117 #define CR0_PERIPH_REQ_SET (1 << 0)
118 #define CR0_BOOT_EN_SET (1 << 1)
119 #define CR0_BOOT_MAN_NS (1 << 2)
120 #define CR0_NUM_CHANS_SHIFT 4
121 #define CR0_NUM_CHANS_MASK 0x7
122 #define CR0_NUM_PERIPH_SHIFT 12
123 #define CR0_NUM_PERIPH_MASK 0x1f
124 #define CR0_NUM_EVENTS_SHIFT 17
125 #define CR0_NUM_EVENTS_MASK 0x1f
127 #define CR1_ICACHE_LEN_SHIFT 0
128 #define CR1_ICACHE_LEN_MASK 0x7
129 #define CR1_NUM_ICACHELINES_SHIFT 4
130 #define CR1_NUM_ICACHELINES_MASK 0xf
132 #define CRD_DATA_WIDTH_SHIFT 0
133 #define CRD_DATA_WIDTH_MASK 0x7
134 #define CRD_WR_CAP_SHIFT 4
135 #define CRD_WR_CAP_MASK 0x7
136 #define CRD_WR_Q_DEP_SHIFT 8
137 #define CRD_WR_Q_DEP_MASK 0xf
138 #define CRD_RD_CAP_SHIFT 12
139 #define CRD_RD_CAP_MASK 0x7
140 #define CRD_RD_Q_DEP_SHIFT 16
141 #define CRD_RD_Q_DEP_MASK 0xf
142 #define CRD_DATA_BUFF_SHIFT 20
143 #define CRD_DATA_BUFF_MASK 0x3ff
146 #define DESIGNER 0x41
148 #define INTEG_CFG 0x0
149 #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
151 #define PCELL_ID_VAL 0xb105f00d
153 #define PL330_STATE_STOPPED (1 << 0)
154 #define PL330_STATE_EXECUTING (1 << 1)
155 #define PL330_STATE_WFE (1 << 2)
156 #define PL330_STATE_FAULTING (1 << 3)
157 #define PL330_STATE_COMPLETING (1 << 4)
158 #define PL330_STATE_WFP (1 << 5)
159 #define PL330_STATE_KILLING (1 << 6)
160 #define PL330_STATE_FAULT_COMPLETING (1 << 7)
161 #define PL330_STATE_CACHEMISS (1 << 8)
162 #define PL330_STATE_UPDTPC (1 << 9)
163 #define PL330_STATE_ATBARRIER (1 << 10)
164 #define PL330_STATE_QUEUEBUSY (1 << 11)
165 #define PL330_STATE_INVALID (1 << 15)
167 #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
168 | PL330_STATE_WFE | PL330_STATE_FAULTING)
170 #define CMD_DMAADDH 0x54
171 #define CMD_DMAEND 0x00
172 #define CMD_DMAFLUSHP 0x35
173 #define CMD_DMAGO 0xa0
174 #define CMD_DMALD 0x04
175 #define CMD_DMALDP 0x25
176 #define CMD_DMALP 0x20
177 #define CMD_DMALPEND 0x28
178 #define CMD_DMAKILL 0x01
179 #define CMD_DMAMOV 0xbc
180 #define CMD_DMANOP 0x18
181 #define CMD_DMARMB 0x12
182 #define CMD_DMASEV 0x34
183 #define CMD_DMAST 0x08
184 #define CMD_DMASTP 0x29
185 #define CMD_DMASTZ 0x0c
186 #define CMD_DMAWFE 0x36
187 #define CMD_DMAWFP 0x30
188 #define CMD_DMAWMB 0x13
192 #define SZ_DMAFLUSHP 2
196 #define SZ_DMALPEND 2
210 #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
211 #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
213 #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
214 #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
217 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
218 * at 1byte/burst for P<->M and M<->M respectively.
219 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
220 * should be enough for P<->M and M<->M respectively.
222 #define MCODE_BUFF_PER_REQ 256
224 /* If the _pl330_req is available to the client */
225 #define IS_FREE(req) (*((u8 *)((req)->mc_cpu)) == CMD_DMAEND)
227 /* Use this _only_ to wait on transient states */
228 #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
230 #ifdef PL330_DEBUG_MCGEN
231 static unsigned cmd_line;
232 #define PL330_DBGCMD_DUMP(off, x...) do { \
233 printk("%x:", cmd_line); \
237 #define PL330_DBGMC_START(addr) (cmd_line = addr)
239 #define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
240 #define PL330_DBGMC_START(addr) do {} while (0)
246 struct pl330_xfer *x;
269 /* Number of bytes taken to setup MC for the req */
272 /* Hook to attach to DMAC's list of reqs with due callback */
273 struct list_head rqd;
276 /* ToBeDone for tasklet */
284 struct pl330_thread {
287 /* If the channel is not yet acquired by any client */
290 struct pl330_dmac *dmac;
291 /* Only two at a time */
292 struct _pl330_req req[2];
293 /* Index of the last enqueued request */
295 /* Index of the last submitted request or -1 if the DMA is stopped */
299 enum pl330_dmac_state {
308 /* Holds list of reqs with due callbacks */
309 struct list_head req_done;
310 /* Pointer to platform specific stuff */
311 struct pl330_info *pinfo;
312 /* Maximum possible events/irqs */
314 /* BUS address of MicroCode buffer */
316 /* CPU address of MicroCode buffer */
318 /* List of all Channel threads */
319 struct pl330_thread *channels;
320 /* Pointer to the MANAGER thread */
321 struct pl330_thread *manager;
322 /* To handle bad news in interrupt */
323 struct tasklet_struct tasks;
324 struct _pl330_tbd dmac_tbd;
325 /* State of DMAC operation */
326 enum pl330_dmac_state state;
329 static inline void _callback(struct pl330_req *r, enum pl330_op_err err)
332 r->xfer_cb(r->token, err);
335 static inline bool _queue_empty(struct pl330_thread *thrd)
337 return (IS_FREE(&thrd->req[0]) && IS_FREE(&thrd->req[1]))
341 static inline bool _queue_full(struct pl330_thread *thrd)
343 return (IS_FREE(&thrd->req[0]) || IS_FREE(&thrd->req[1]))
347 static inline bool is_manager(struct pl330_thread *thrd)
349 struct pl330_dmac *pl330 = thrd->dmac;
351 /* MANAGER is indexed at the end */
352 if (thrd->id == pl330->pinfo->pcfg.num_chan)
358 /* If manager of the thread is in Non-Secure mode */
359 static inline bool _manager_ns(struct pl330_thread *thrd)
361 struct pl330_dmac *pl330 = thrd->dmac;
363 return (pl330->pinfo->pcfg.mode & DMAC_MODE_NS) ? true : false;
366 static inline u32 get_id(struct pl330_info *pi, u32 off)
368 void __iomem *regs = pi->base;
371 id |= (readb(regs + off + 0x0) << 0);
372 id |= (readb(regs + off + 0x4) << 8);
373 id |= (readb(regs + off + 0x8) << 16);
374 id |= (readb(regs + off + 0xc) << 24);
379 static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[],
380 enum pl330_dst da, u16 val)
385 buf[0] = CMD_DMAADDH;
387 *((u16 *)&buf[1]) = val;
389 PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n",
390 da == 1 ? "DA" : "SA", val);
395 static inline u32 _emit_END(unsigned dry_run, u8 buf[])
402 PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
407 static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
412 buf[0] = CMD_DMAFLUSHP;
418 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
423 static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond)
431 buf[0] |= (0 << 1) | (1 << 0);
432 else if (cond == BURST)
433 buf[0] |= (1 << 1) | (1 << 0);
435 PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
436 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
441 static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
442 enum pl330_cond cond, u8 peri)
456 PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
457 cond == SINGLE ? 'S' : 'B', peri >> 3);
462 static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
463 unsigned loop, u8 cnt)
473 cnt--; /* DMAC increments by 1 internally */
476 PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
482 enum pl330_cond cond;
488 static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
489 const struct _arg_LPEND *arg)
491 enum pl330_cond cond = arg->cond;
492 bool forever = arg->forever;
493 unsigned loop = arg->loop;
494 u8 bjump = arg->bjump;
499 buf[0] = CMD_DMALPEND;
508 buf[0] |= (0 << 1) | (1 << 0);
509 else if (cond == BURST)
510 buf[0] |= (1 << 1) | (1 << 0);
514 PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
515 forever ? "FE" : "END",
516 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
523 static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
528 buf[0] = CMD_DMAKILL;
533 static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
534 enum dmamov_dst dst, u32 val)
541 *((u32 *)&buf[2]) = val;
543 PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
544 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
549 static inline u32 _emit_NOP(unsigned dry_run, u8 buf[])
556 PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n");
561 static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
568 PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
573 static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
584 PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
589 static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
597 buf[0] |= (0 << 1) | (1 << 0);
598 else if (cond == BURST)
599 buf[0] |= (1 << 1) | (1 << 0);
601 PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
602 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
607 static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
608 enum pl330_cond cond, u8 peri)
622 PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
623 cond == SINGLE ? 'S' : 'B', peri >> 3);
628 static inline u32 _emit_STZ(unsigned dry_run, u8 buf[])
635 PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n");
640 static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev,
655 PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n",
656 ev >> 3, invalidate ? ", I" : "");
661 static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
662 enum pl330_cond cond, u8 peri)
670 buf[0] |= (0 << 1) | (0 << 0);
671 else if (cond == BURST)
672 buf[0] |= (1 << 1) | (0 << 0);
674 buf[0] |= (0 << 1) | (1 << 0);
680 PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
681 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
686 static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
693 PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
704 static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
705 const struct _arg_GO *arg)
708 u32 addr = arg->addr;
709 unsigned ns = arg->ns;
719 *((u32 *)&buf[2]) = addr;
724 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
726 /* Returns Time-Out */
727 static bool _until_dmac_idle(struct pl330_thread *thrd)
729 void __iomem *regs = thrd->dmac->pinfo->base;
730 unsigned long loops = msecs_to_loops(5);
733 /* Until Manager is Idle */
734 if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
746 static inline void _execute_DBGINSN(struct pl330_thread *thrd,
747 u8 insn[], bool as_manager)
749 void __iomem *regs = thrd->dmac->pinfo->base;
752 val = (insn[0] << 16) | (insn[1] << 24);
755 val |= (thrd->id << 8); /* Channel Number */
757 writel(val, regs + DBGINST0);
759 val = *((u32 *)&insn[2]);
760 writel(val, regs + DBGINST1);
762 /* If timed out due to halted state-machine */
763 if (_until_dmac_idle(thrd)) {
764 dev_err(thrd->dmac->pinfo->dev, "DMAC halted!\n");
769 writel(0, regs + DBGCMD);
773 * Mark a _pl330_req as free.
774 * We do it by writing DMAEND as the first instruction
775 * because no valid request is going to have DMAEND as
776 * its first instruction to execute.
778 static void mark_free(struct pl330_thread *thrd, int idx)
780 struct _pl330_req *req = &thrd->req[idx];
782 _emit_END(0, req->mc_cpu);
785 thrd->req_running = -1;
788 static inline u32 _state(struct pl330_thread *thrd)
790 void __iomem *regs = thrd->dmac->pinfo->base;
793 if (is_manager(thrd))
794 val = readl(regs + DS) & 0xf;
796 val = readl(regs + CS(thrd->id)) & 0xf;
800 return PL330_STATE_STOPPED;
802 return PL330_STATE_EXECUTING;
804 return PL330_STATE_CACHEMISS;
806 return PL330_STATE_UPDTPC;
808 return PL330_STATE_WFE;
810 return PL330_STATE_FAULTING;
812 if (is_manager(thrd))
813 return PL330_STATE_INVALID;
815 return PL330_STATE_ATBARRIER;
817 if (is_manager(thrd))
818 return PL330_STATE_INVALID;
820 return PL330_STATE_QUEUEBUSY;
822 if (is_manager(thrd))
823 return PL330_STATE_INVALID;
825 return PL330_STATE_WFP;
827 if (is_manager(thrd))
828 return PL330_STATE_INVALID;
830 return PL330_STATE_KILLING;
832 if (is_manager(thrd))
833 return PL330_STATE_INVALID;
835 return PL330_STATE_COMPLETING;
837 if (is_manager(thrd))
838 return PL330_STATE_INVALID;
840 return PL330_STATE_FAULT_COMPLETING;
842 return PL330_STATE_INVALID;
846 static void _stop(struct pl330_thread *thrd)
848 void __iomem *regs = thrd->dmac->pinfo->base;
849 u8 insn[6] = {0, 0, 0, 0, 0, 0};
851 if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
852 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
854 /* Return if nothing needs to be done */
855 if (_state(thrd) == PL330_STATE_COMPLETING
856 || _state(thrd) == PL330_STATE_KILLING
857 || _state(thrd) == PL330_STATE_STOPPED)
862 /* Stop generating interrupts for SEV */
863 writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN);
865 _execute_DBGINSN(thrd, insn, is_manager(thrd));
868 /* Start doing req 'idx' of thread 'thrd' */
869 static bool _trigger(struct pl330_thread *thrd)
871 void __iomem *regs = thrd->dmac->pinfo->base;
872 struct _pl330_req *req;
876 u8 insn[6] = {0, 0, 0, 0, 0, 0};
879 /* Return if already ACTIVE */
880 if (_state(thrd) != PL330_STATE_STOPPED)
883 idx = 1 - thrd->lstenq;
884 if (!IS_FREE(&thrd->req[idx]))
885 req = &thrd->req[idx];
888 if (!IS_FREE(&thrd->req[idx]))
889 req = &thrd->req[idx];
894 /* Return if no request */
901 ns = r->cfg->nonsecure ? 1 : 0;
902 else if (readl(regs + CS(thrd->id)) & CS_CNS)
907 /* See 'Abort Sources' point-4 at Page 2-25 */
908 if (_manager_ns(thrd) && !ns)
909 dev_info(thrd->dmac->pinfo->dev, "%s:%d Recipe for ABORT!\n",
913 go.addr = req->mc_bus;
915 _emit_GO(0, insn, &go);
917 /* Set to generate interrupts for SEV */
918 writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
920 /* Only manager can execute GO */
921 _execute_DBGINSN(thrd, insn, true);
923 thrd->req_running = idx;
928 static bool _start(struct pl330_thread *thrd)
930 switch (_state(thrd)) {
931 case PL330_STATE_FAULT_COMPLETING:
932 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
934 if (_state(thrd) == PL330_STATE_KILLING)
935 UNTIL(thrd, PL330_STATE_STOPPED)
937 case PL330_STATE_FAULTING:
940 case PL330_STATE_KILLING:
941 case PL330_STATE_COMPLETING:
942 UNTIL(thrd, PL330_STATE_STOPPED)
944 case PL330_STATE_STOPPED:
945 return _trigger(thrd);
947 case PL330_STATE_WFP:
948 case PL330_STATE_QUEUEBUSY:
949 case PL330_STATE_ATBARRIER:
950 case PL330_STATE_UPDTPC:
951 case PL330_STATE_CACHEMISS:
952 case PL330_STATE_EXECUTING:
955 case PL330_STATE_WFE: /* For RESUME, nothing yet */
961 static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
962 const struct _xfer_spec *pxs, int cyc)
967 off += _emit_LD(dry_run, &buf[off], ALWAYS);
968 off += _emit_RMB(dry_run, &buf[off]);
969 off += _emit_ST(dry_run, &buf[off], ALWAYS);
970 off += _emit_WMB(dry_run, &buf[off]);
976 static inline int _ldst_devtomem(unsigned dry_run, u8 buf[],
977 const struct _xfer_spec *pxs, int cyc)
982 off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->r->peri);
983 off += _emit_LDP(dry_run, &buf[off], SINGLE, pxs->r->peri);
984 off += _emit_ST(dry_run, &buf[off], ALWAYS);
985 off += _emit_FLUSHP(dry_run, &buf[off], pxs->r->peri);
991 static inline int _ldst_memtodev(unsigned dry_run, u8 buf[],
992 const struct _xfer_spec *pxs, int cyc)
997 off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->r->peri);
998 off += _emit_LD(dry_run, &buf[off], ALWAYS);
999 off += _emit_STP(dry_run, &buf[off], SINGLE, pxs->r->peri);
1000 off += _emit_FLUSHP(dry_run, &buf[off], pxs->r->peri);
1006 static int _bursts(unsigned dry_run, u8 buf[],
1007 const struct _xfer_spec *pxs, int cyc)
1011 switch (pxs->r->rqtype) {
1013 off += _ldst_memtodev(dry_run, &buf[off], pxs, cyc);
1016 off += _ldst_devtomem(dry_run, &buf[off], pxs, cyc);
1019 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
1022 off += 0x40000000; /* Scare off the Client */
1029 /* Returns bytes consumed and updates bursts */
1030 static inline int _loop(unsigned dry_run, u8 buf[],
1031 unsigned long *bursts, const struct _xfer_spec *pxs)
1033 int cyc, cycmax, szlp, szlpend, szbrst, off;
1034 unsigned lcnt0, lcnt1, ljmp0, ljmp1;
1035 struct _arg_LPEND lpend;
1037 /* Max iterations possible in DMALP is 256 */
1038 if (*bursts >= 256*256) {
1041 cyc = *bursts / lcnt1 / lcnt0;
1042 } else if (*bursts > 256) {
1044 lcnt0 = *bursts / lcnt1;
1052 szlp = _emit_LP(1, buf, 0, 0);
1053 szbrst = _bursts(1, buf, pxs, 1);
1055 lpend.cond = ALWAYS;
1056 lpend.forever = false;
1059 szlpend = _emit_LPEND(1, buf, &lpend);
1067 * Max bursts that we can unroll due to limit on the
1068 * size of backward jump that can be encoded in DMALPEND
1069 * which is 8-bits and hence 255
1071 cycmax = (255 - (szlp + szlpend)) / szbrst;
1073 cyc = (cycmax < cyc) ? cycmax : cyc;
1078 off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
1082 off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
1085 off += _bursts(dry_run, &buf[off], pxs, cyc);
1087 lpend.cond = ALWAYS;
1088 lpend.forever = false;
1090 lpend.bjump = off - ljmp1;
1091 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1094 lpend.cond = ALWAYS;
1095 lpend.forever = false;
1097 lpend.bjump = off - ljmp0;
1098 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1101 *bursts = lcnt1 * cyc;
1108 static inline int _setup_loops(unsigned dry_run, u8 buf[],
1109 const struct _xfer_spec *pxs)
1111 struct pl330_xfer *x = pxs->x;
1113 unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
1118 off += _loop(dry_run, &buf[off], &c, pxs);
1125 static inline int _setup_xfer(unsigned dry_run, u8 buf[],
1126 const struct _xfer_spec *pxs)
1128 struct pl330_xfer *x = pxs->x;
1131 /* DMAMOV SAR, x->src_addr */
1132 off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
1133 /* DMAMOV DAR, x->dst_addr */
1134 off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
1137 off += _setup_loops(dry_run, &buf[off], pxs);
1143 * A req is a sequence of one or more xfer units.
1144 * Returns the number of bytes taken to setup the MC for the req.
1146 static int _setup_req(unsigned dry_run, struct pl330_thread *thrd,
1147 unsigned index, struct _xfer_spec *pxs)
1149 struct _pl330_req *req = &thrd->req[index];
1150 struct pl330_xfer *x;
1151 u8 *buf = req->mc_cpu;
1154 PL330_DBGMC_START(req->mc_bus);
1156 /* DMAMOV CCR, ccr */
1157 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
1161 /* Error if xfer length is not aligned at burst size */
1162 if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr)))
1166 off += _setup_xfer(dry_run, &buf[off], pxs);
1171 /* DMASEV peripheral/event */
1172 off += _emit_SEV(dry_run, &buf[off], thrd->ev);
1174 off += _emit_END(dry_run, &buf[off]);
1179 static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
1189 /* We set same protection levels for Src and DST for now */
1190 if (rqc->privileged)
1191 ccr |= CC_SRCPRI | CC_DSTPRI;
1193 ccr |= CC_SRCNS | CC_DSTNS;
1194 if (rqc->insnaccess)
1195 ccr |= CC_SRCIA | CC_DSTIA;
1197 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
1198 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
1200 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1201 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1203 ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
1204 ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1206 ccr |= (rqc->swap << CC_SWAP_SHFT);
1211 static inline bool _is_valid(u32 ccr)
1213 enum pl330_dstcachectrl dcctl;
1214 enum pl330_srccachectrl scctl;
1216 dcctl = (ccr >> CC_DSTCCTRL_SHFT) & CC_DRCCCTRL_MASK;
1217 scctl = (ccr >> CC_SRCCCTRL_SHFT) & CC_SRCCCTRL_MASK;
1219 if (dcctl == DINVALID1 || dcctl == DINVALID2
1220 || scctl == SINVALID1 || scctl == SINVALID2)
1227 * Submit a list of xfers after which the client wants notification.
1228 * Client is not notified after each xfer unit, just once after all
1229 * xfer units are done or some error occurs.
1231 int pl330_submit_req(void *ch_id, struct pl330_req *r)
1233 struct pl330_thread *thrd = ch_id;
1234 struct pl330_dmac *pl330;
1235 struct pl330_info *pi;
1236 struct _xfer_spec xs;
1237 unsigned long flags;
1243 /* No Req or Unacquired Channel or DMAC */
1244 if (!r || !thrd || thrd->free)
1251 if (pl330->state == DYING
1252 || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
1253 dev_info(thrd->dmac->pinfo->dev, "%s:%d\n",
1254 __func__, __LINE__);
1258 /* If request for non-existing peripheral */
1259 if (r->rqtype != MEMTOMEM && r->peri >= pi->pcfg.num_peri) {
1260 dev_info(thrd->dmac->pinfo->dev,
1261 "%s:%d Invalid peripheral(%u)!\n",
1262 __func__, __LINE__, r->peri);
1266 spin_lock_irqsave(&pl330->lock, flags);
1268 if (_queue_full(thrd)) {
1273 /* Prefer Secure Channel */
1274 if (!_manager_ns(thrd))
1275 r->cfg->nonsecure = 0;
1277 r->cfg->nonsecure = 1;
1279 /* Use last settings, if not provided */
1281 ccr = _prepare_ccr(r->cfg);
1283 ccr = readl(regs + CC(thrd->id));
1285 /* If this req doesn't have valid xfer settings */
1286 if (!_is_valid(ccr)) {
1288 dev_info(thrd->dmac->pinfo->dev, "%s:%d Invalid CCR(%x)!\n",
1289 __func__, __LINE__, ccr);
1293 idx = IS_FREE(&thrd->req[0]) ? 0 : 1;
1298 /* First dry run to check if req is acceptable */
1299 ret = _setup_req(1, thrd, idx, &xs);
1303 if (ret > pi->mcbufsz / 2) {
1304 dev_info(thrd->dmac->pinfo->dev,
1305 "%s:%d Trying increasing mcbufsz\n",
1306 __func__, __LINE__);
1311 /* Hook the request */
1313 thrd->req[idx].mc_len = _setup_req(0, thrd, idx, &xs);
1314 thrd->req[idx].r = r;
1319 spin_unlock_irqrestore(&pl330->lock, flags);
1323 EXPORT_SYMBOL(pl330_submit_req);
1325 static void pl330_dotask(unsigned long data)
1327 struct pl330_dmac *pl330 = (struct pl330_dmac *) data;
1328 struct pl330_info *pi = pl330->pinfo;
1329 unsigned long flags;
1332 spin_lock_irqsave(&pl330->lock, flags);
1334 /* The DMAC itself gone nuts */
1335 if (pl330->dmac_tbd.reset_dmac) {
1336 pl330->state = DYING;
1337 /* Reset the manager too */
1338 pl330->dmac_tbd.reset_mngr = true;
1339 /* Clear the reset flag */
1340 pl330->dmac_tbd.reset_dmac = false;
1343 if (pl330->dmac_tbd.reset_mngr) {
1344 _stop(pl330->manager);
1345 /* Reset all channels */
1346 pl330->dmac_tbd.reset_chan = (1 << pi->pcfg.num_chan) - 1;
1347 /* Clear the reset flag */
1348 pl330->dmac_tbd.reset_mngr = false;
1351 for (i = 0; i < pi->pcfg.num_chan; i++) {
1353 if (pl330->dmac_tbd.reset_chan & (1 << i)) {
1354 struct pl330_thread *thrd = &pl330->channels[i];
1355 void __iomem *regs = pi->base;
1356 enum pl330_op_err err;
1360 if (readl(regs + FSC) & (1 << thrd->id))
1361 err = PL330_ERR_FAIL;
1363 err = PL330_ERR_ABORT;
1365 spin_unlock_irqrestore(&pl330->lock, flags);
1367 _callback(thrd->req[1 - thrd->lstenq].r, err);
1368 _callback(thrd->req[thrd->lstenq].r, err);
1370 spin_lock_irqsave(&pl330->lock, flags);
1372 thrd->req[0].r = NULL;
1373 thrd->req[1].r = NULL;
1377 /* Clear the reset flag */
1378 pl330->dmac_tbd.reset_chan &= ~(1 << i);
1382 spin_unlock_irqrestore(&pl330->lock, flags);
1387 /* Returns 1 if state was updated, 0 otherwise */
1388 int pl330_update(const struct pl330_info *pi)
1390 struct _pl330_req *rqdone;
1391 struct pl330_dmac *pl330;
1392 unsigned long flags;
1395 int id, ev, ret = 0;
1397 if (!pi || !pi->pl330_data)
1401 pl330 = pi->pl330_data;
1403 spin_lock_irqsave(&pl330->lock, flags);
1405 val = readl(regs + FSM) & 0x1;
1407 pl330->dmac_tbd.reset_mngr = true;
1409 pl330->dmac_tbd.reset_mngr = false;
1411 val = readl(regs + FSC) & ((1 << pi->pcfg.num_chan) - 1);
1412 pl330->dmac_tbd.reset_chan |= val;
1415 while (i < pi->pcfg.num_chan) {
1416 if (val & (1 << i)) {
1418 "Reset Channel-%d\t CS-%x FTC-%x\n",
1419 i, readl(regs + CS(i)),
1420 readl(regs + FTC(i)));
1421 _stop(&pl330->channels[i]);
1427 /* Check which event happened i.e, thread notified */
1428 val = readl(regs + ES);
1429 if (pi->pcfg.num_events < 32
1430 && val & ~((1 << pi->pcfg.num_events) - 1)) {
1431 pl330->dmac_tbd.reset_dmac = true;
1432 dev_err(pi->dev, "%s:%d Unexpected!\n", __func__, __LINE__);
1437 for (ev = 0; ev < pi->pcfg.num_events; ev++) {
1438 if (val & (1 << ev)) { /* Event occurred */
1439 struct pl330_thread *thrd;
1440 u32 inten = readl(regs + INTEN);
1443 /* Clear the event */
1444 if (inten & (1 << ev))
1445 writel(1 << ev, regs + INTCLR);
1449 id = pl330->events[ev];
1451 thrd = &pl330->channels[id];
1453 active = thrd->req_running;
1454 if (active == -1) /* Aborted */
1457 rqdone = &thrd->req[active];
1458 mark_free(thrd, active);
1460 /* Get going again ASAP */
1463 /* For now, just make a list of callbacks to be done */
1464 list_add_tail(&rqdone->rqd, &pl330->req_done);
1468 /* Now that we are in no hurry, do the callbacks */
1469 while (!list_empty(&pl330->req_done)) {
1470 struct pl330_req *r;
1472 rqdone = container_of(pl330->req_done.next,
1473 struct _pl330_req, rqd);
1475 list_del_init(&rqdone->rqd);
1477 /* Detach the req */
1481 spin_unlock_irqrestore(&pl330->lock, flags);
1482 _callback(r, PL330_ERR_NONE);
1483 spin_lock_irqsave(&pl330->lock, flags);
1487 spin_unlock_irqrestore(&pl330->lock, flags);
1489 if (pl330->dmac_tbd.reset_dmac
1490 || pl330->dmac_tbd.reset_mngr
1491 || pl330->dmac_tbd.reset_chan) {
1493 tasklet_schedule(&pl330->tasks);
1498 EXPORT_SYMBOL(pl330_update);
1500 int pl330_chan_ctrl(void *ch_id, enum pl330_chan_op op)
1502 struct pl330_thread *thrd = ch_id;
1503 struct pl330_dmac *pl330;
1504 unsigned long flags;
1505 int ret = 0, active = thrd->req_running;
1507 if (!thrd || thrd->free || thrd->dmac->state == DYING)
1512 spin_lock_irqsave(&pl330->lock, flags);
1515 case PL330_OP_FLUSH:
1516 /* Make sure the channel is stopped */
1519 thrd->req[0].r = NULL;
1520 thrd->req[1].r = NULL;
1525 case PL330_OP_ABORT:
1526 /* Make sure the channel is stopped */
1529 /* ABORT is only for the active req */
1533 thrd->req[active].r = NULL;
1534 mark_free(thrd, active);
1536 /* Start the next */
1537 case PL330_OP_START:
1538 if ((active == -1) && !_start(thrd))
1546 spin_unlock_irqrestore(&pl330->lock, flags);
1549 EXPORT_SYMBOL(pl330_chan_ctrl);
1551 int pl330_chan_status(void *ch_id, struct pl330_chanstatus *pstatus)
1553 struct pl330_thread *thrd = ch_id;
1554 struct pl330_dmac *pl330;
1555 struct pl330_info *pi;
1560 if (!pstatus || !thrd || thrd->free)
1567 /* The client should remove the DMAC and add again */
1568 if (pl330->state == DYING)
1569 pstatus->dmac_halted = true;
1571 pstatus->dmac_halted = false;
1573 val = readl(regs + FSC);
1574 if (val & (1 << thrd->id))
1575 pstatus->faulting = true;
1577 pstatus->faulting = false;
1579 active = thrd->req_running;
1582 /* Indicate that the thread is not running */
1583 pstatus->top_req = NULL;
1584 pstatus->wait_req = NULL;
1586 pstatus->top_req = thrd->req[active].r;
1587 pstatus->wait_req = !IS_FREE(&thrd->req[1 - active])
1588 ? thrd->req[1 - active].r : NULL;
1591 pstatus->src_addr = readl(regs + SA(thrd->id));
1592 pstatus->dst_addr = readl(regs + DA(thrd->id));
1596 EXPORT_SYMBOL(pl330_chan_status);
1598 /* Reserve an event */
1599 static inline int _alloc_event(struct pl330_thread *thrd)
1601 struct pl330_dmac *pl330 = thrd->dmac;
1602 struct pl330_info *pi = pl330->pinfo;
1605 for (ev = 0; ev < pi->pcfg.num_events; ev++)
1606 if (pl330->events[ev] == -1) {
1607 pl330->events[ev] = thrd->id;
1614 static bool _chan_ns(const struct pl330_info *pi, int i)
1616 return pi->pcfg.irq_ns & (1 << i);
1619 /* Upon success, returns IdentityToken for the
1620 * allocated channel, NULL otherwise.
1622 void *pl330_request_channel(const struct pl330_info *pi)
1624 struct pl330_thread *thrd = NULL;
1625 struct pl330_dmac *pl330;
1626 unsigned long flags;
1629 if (!pi || !pi->pl330_data)
1632 pl330 = pi->pl330_data;
1634 if (pl330->state == DYING)
1637 chans = pi->pcfg.num_chan;
1639 spin_lock_irqsave(&pl330->lock, flags);
1641 for (i = 0; i < chans; i++) {
1642 thrd = &pl330->channels[i];
1643 if ((thrd->free) && (!_manager_ns(thrd) ||
1645 thrd->ev = _alloc_event(thrd);
1646 if (thrd->ev >= 0) {
1649 thrd->req[0].r = NULL;
1651 thrd->req[1].r = NULL;
1659 spin_unlock_irqrestore(&pl330->lock, flags);
1663 EXPORT_SYMBOL(pl330_request_channel);
1665 /* Release an event */
1666 static inline void _free_event(struct pl330_thread *thrd, int ev)
1668 struct pl330_dmac *pl330 = thrd->dmac;
1669 struct pl330_info *pi = pl330->pinfo;
1671 /* If the event is valid and was held by the thread */
1672 if (ev >= 0 && ev < pi->pcfg.num_events
1673 && pl330->events[ev] == thrd->id)
1674 pl330->events[ev] = -1;
1677 void pl330_release_channel(void *ch_id)
1679 struct pl330_thread *thrd = ch_id;
1680 struct pl330_dmac *pl330;
1681 unsigned long flags;
1683 if (!thrd || thrd->free)
1688 _callback(thrd->req[1 - thrd->lstenq].r, PL330_ERR_ABORT);
1689 _callback(thrd->req[thrd->lstenq].r, PL330_ERR_ABORT);
1693 spin_lock_irqsave(&pl330->lock, flags);
1694 _free_event(thrd, thrd->ev);
1696 spin_unlock_irqrestore(&pl330->lock, flags);
1698 EXPORT_SYMBOL(pl330_release_channel);
1700 /* Initialize the structure for PL330 configuration, that can be used
1701 * by the client driver the make best use of the DMAC
1703 static void read_dmac_config(struct pl330_info *pi)
1705 void __iomem *regs = pi->base;
1708 val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
1709 val &= CRD_DATA_WIDTH_MASK;
1710 pi->pcfg.data_bus_width = 8 * (1 << val);
1712 val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
1713 val &= CRD_DATA_BUFF_MASK;
1714 pi->pcfg.data_buf_dep = val + 1;
1716 val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
1717 val &= CR0_NUM_CHANS_MASK;
1719 pi->pcfg.num_chan = val;
1721 val = readl(regs + CR0);
1722 if (val & CR0_PERIPH_REQ_SET) {
1723 val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
1725 pi->pcfg.num_peri = val;
1726 pi->pcfg.peri_ns = readl(regs + CR4);
1728 pi->pcfg.num_peri = 0;
1731 val = readl(regs + CR0);
1732 if (val & CR0_BOOT_MAN_NS)
1733 pi->pcfg.mode |= DMAC_MODE_NS;
1735 pi->pcfg.mode &= ~DMAC_MODE_NS;
1737 val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
1738 val &= CR0_NUM_EVENTS_MASK;
1740 pi->pcfg.num_events = val;
1742 pi->pcfg.irq_ns = readl(regs + CR3);
1744 pi->pcfg.periph_id = get_id(pi, PERIPH_ID);
1745 pi->pcfg.pcell_id = get_id(pi, PCELL_ID);
1748 static inline void _reset_thread(struct pl330_thread *thrd)
1750 struct pl330_dmac *pl330 = thrd->dmac;
1751 struct pl330_info *pi = pl330->pinfo;
1753 thrd->req[0].mc_cpu = pl330->mcode_cpu
1754 + (thrd->id * pi->mcbufsz);
1755 thrd->req[0].mc_bus = pl330->mcode_bus
1756 + (thrd->id * pi->mcbufsz);
1757 thrd->req[0].r = NULL;
1760 thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
1762 thrd->req[1].mc_bus = thrd->req[0].mc_bus
1764 thrd->req[1].r = NULL;
1768 static int dmac_alloc_threads(struct pl330_dmac *pl330)
1770 struct pl330_info *pi = pl330->pinfo;
1771 int chans = pi->pcfg.num_chan;
1772 struct pl330_thread *thrd;
1775 /* Allocate 1 Manager and 'chans' Channel threads */
1776 pl330->channels = kzalloc((1 + chans) * sizeof(*thrd),
1778 if (!pl330->channels)
1781 /* Init Channel threads */
1782 for (i = 0; i < chans; i++) {
1783 thrd = &pl330->channels[i];
1786 _reset_thread(thrd);
1790 /* MANAGER is indexed at the end */
1791 thrd = &pl330->channels[chans];
1795 pl330->manager = thrd;
1800 static int dmac_alloc_resources(struct pl330_dmac *pl330)
1802 struct pl330_info *pi = pl330->pinfo;
1803 int chans = pi->pcfg.num_chan;
1807 * Alloc MicroCode buffer for 'chans' Channel threads.
1808 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
1810 pl330->mcode_cpu = dma_alloc_coherent(pi->dev,
1811 chans * pi->mcbufsz,
1812 &pl330->mcode_bus, GFP_KERNEL);
1813 if (!pl330->mcode_cpu) {
1814 dev_err(pi->dev, "%s:%d Can't allocate memory!\n",
1815 __func__, __LINE__);
1819 ret = dmac_alloc_threads(pl330);
1821 dev_err(pi->dev, "%s:%d Can't to create channels for DMAC!\n",
1822 __func__, __LINE__);
1823 dma_free_coherent(pi->dev,
1824 chans * pi->mcbufsz,
1825 pl330->mcode_cpu, pl330->mcode_bus);
1832 int pl330_add(struct pl330_info *pi)
1834 struct pl330_dmac *pl330;
1838 if (!pi || !pi->dev)
1841 /* If already added */
1846 * If the SoC can perform reset on the DMAC, then do it
1847 * before reading its configuration.
1854 /* Check if we can handle this DMAC */
1855 if ((get_id(pi, PERIPH_ID) & 0xfffff) != PERIPH_ID_VAL
1856 || get_id(pi, PCELL_ID) != PCELL_ID_VAL) {
1857 dev_err(pi->dev, "PERIPH_ID 0x%x, PCELL_ID 0x%x !\n",
1858 get_id(pi, PERIPH_ID), get_id(pi, PCELL_ID));
1862 /* Read the configuration of the DMAC */
1863 read_dmac_config(pi);
1865 if (pi->pcfg.num_events == 0) {
1866 dev_err(pi->dev, "%s:%d Can't work without events!\n",
1867 __func__, __LINE__);
1871 pl330 = kzalloc(sizeof(*pl330), GFP_KERNEL);
1873 dev_err(pi->dev, "%s:%d Can't allocate memory!\n",
1874 __func__, __LINE__);
1878 /* Assign the info structure and private data */
1880 pi->pl330_data = pl330;
1882 spin_lock_init(&pl330->lock);
1884 INIT_LIST_HEAD(&pl330->req_done);
1886 /* Use default MC buffer size if not provided */
1888 pi->mcbufsz = MCODE_BUFF_PER_REQ * 2;
1890 /* Mark all events as free */
1891 for (i = 0; i < pi->pcfg.num_events; i++)
1892 pl330->events[i] = -1;
1894 /* Allocate resources needed by the DMAC */
1895 ret = dmac_alloc_resources(pl330);
1897 dev_err(pi->dev, "Unable to create channels for DMAC\n");
1902 tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330);
1904 pl330->state = INIT;
1908 EXPORT_SYMBOL(pl330_add);
1910 static int dmac_free_threads(struct pl330_dmac *pl330)
1912 struct pl330_info *pi = pl330->pinfo;
1913 int chans = pi->pcfg.num_chan;
1914 struct pl330_thread *thrd;
1917 /* Release Channel threads */
1918 for (i = 0; i < chans; i++) {
1919 thrd = &pl330->channels[i];
1920 pl330_release_channel((void *)thrd);
1924 kfree(pl330->channels);
1929 static void dmac_free_resources(struct pl330_dmac *pl330)
1931 struct pl330_info *pi = pl330->pinfo;
1932 int chans = pi->pcfg.num_chan;
1934 dmac_free_threads(pl330);
1936 dma_free_coherent(pi->dev, chans * pi->mcbufsz,
1937 pl330->mcode_cpu, pl330->mcode_bus);
1940 void pl330_del(struct pl330_info *pi)
1942 struct pl330_dmac *pl330;
1944 if (!pi || !pi->pl330_data)
1947 pl330 = pi->pl330_data;
1949 pl330->state = UNINIT;
1951 tasklet_kill(&pl330->tasks);
1953 /* Free DMAC resources */
1954 dmac_free_resources(pl330);
1957 pi->pl330_data = NULL;
1959 EXPORT_SYMBOL(pl330_del);