2 * linux/arch/arm/common/vic.c
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <linux/init.h>
22 #include <linux/list.h>
24 #include <linux/sysdev.h>
26 #include <asm/mach/irq.h>
27 #include <asm/hardware/vic.h>
29 static void vic_mask_irq(unsigned int irq)
31 void __iomem *base = get_irq_chip_data(irq);
33 writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
36 static void vic_unmask_irq(unsigned int irq)
38 void __iomem *base = get_irq_chip_data(irq);
40 writel(1 << irq, base + VIC_INT_ENABLE);
44 * vic_init2 - common initialisation code
45 * @base: Base of the VIC.
47 * Common initialisation code for registeration
50 static void vic_init2(void __iomem *base)
54 for (i = 0; i < 16; i++) {
55 void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
56 writel(VIC_VECT_CNTL_ENABLE | i, reg);
59 writel(32, base + VIC_PL190_DEF_VECT_ADDR);
62 #if defined(CONFIG_PM)
64 * struct vic_device - VIC PM device
65 * @sysdev: The system device which is registered.
66 * @irq: The IRQ number for the base of the VIC.
67 * @base: The register base for the VIC.
68 * @resume_sources: A bitmask of interrupts for resume.
69 * @resume_irqs: The IRQs enabled for resume.
70 * @int_select: Save for VIC_INT_SELECT.
71 * @int_enable: Save for VIC_INT_ENABLE.
72 * @soft_int: Save for VIC_INT_SOFT.
73 * @protect: Save for VIC_PROTECT.
76 struct sys_device sysdev;
88 /* we cannot allocate memory when VICs are initially registered */
89 static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
91 static inline struct vic_device *to_vic(struct sys_device *sys)
93 return container_of(sys, struct vic_device, sysdev);
98 static int vic_class_resume(struct sys_device *dev)
100 struct vic_device *vic = to_vic(dev);
101 void __iomem *base = vic->base;
103 printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);
105 /* re-initialise static settings */
108 writel(vic->int_select, base + VIC_INT_SELECT);
109 writel(vic->protect, base + VIC_PROTECT);
111 /* set the enabled ints and then clear the non-enabled */
112 writel(vic->int_enable, base + VIC_INT_ENABLE);
113 writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);
115 /* and the same for the soft-int register */
117 writel(vic->soft_int, base + VIC_INT_SOFT);
118 writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
123 static int vic_class_suspend(struct sys_device *dev, pm_message_t state)
125 struct vic_device *vic = to_vic(dev);
126 void __iomem *base = vic->base;
128 printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);
130 vic->int_select = readl(base + VIC_INT_SELECT);
131 vic->int_enable = readl(base + VIC_INT_ENABLE);
132 vic->soft_int = readl(base + VIC_INT_SOFT);
133 vic->protect = readl(base + VIC_PROTECT);
135 /* set the interrupts (if any) that are used for
136 * resuming the system */
138 writel(vic->resume_irqs, base + VIC_INT_ENABLE);
139 writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
144 struct sysdev_class vic_class = {
146 .suspend = vic_class_suspend,
147 .resume = vic_class_resume,
151 * vic_pm_register - Register a VIC for later power management control
152 * @base: The base address of the VIC.
153 * @irq: The base IRQ for the VIC.
154 * @resume_sources: bitmask of interrupts allowed for resume sources.
156 * Register the VIC with the system device tree so that it can be notified
157 * of suspend and resume requests and ensure that the correct actions are
158 * taken to re-instate the settings on resume.
160 static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources)
162 struct vic_device *v;
164 if (vic_id >= ARRAY_SIZE(vic_devices))
165 printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
167 v = &vic_devices[vic_id];
169 v->resume_sources = resume_sources;
176 * vic_pm_init - initicall to register VIC pm
178 * This is called via late_initcall() to register
179 * the resources for the VICs due to the early
180 * nature of the VIC's registration.
182 static int __init vic_pm_init(void)
184 struct vic_device *dev = vic_devices;
191 err = sysdev_class_register(&vic_class);
193 printk(KERN_ERR "%s: cannot register class\n", __func__);
197 for (id = 0; id < vic_id; id++, dev++) {
199 dev->sysdev.cls = &vic_class;
201 err = sysdev_register(&dev->sysdev);
203 printk(KERN_ERR "%s: failed to register device\n",
212 late_initcall(vic_pm_init);
214 static struct vic_device *vic_from_irq(unsigned int irq)
216 struct vic_device *v = vic_devices;
217 unsigned int base_irq = irq & ~31;
220 for (id = 0; id < vic_id; id++, v++) {
221 if (v->irq == base_irq)
228 static int vic_set_wake(unsigned int irq, unsigned int on)
230 struct vic_device *v = vic_from_irq(irq);
231 unsigned int off = irq & 31;
237 v->resume_irqs |= 1 << off;
239 v->resume_irqs &= ~(1 << off);
245 static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { }
247 #define vic_set_wake NULL
248 #endif /* CONFIG_PM */
250 static struct irq_chip vic_chip = {
253 .mask = vic_mask_irq,
254 .unmask = vic_unmask_irq,
255 .set_wake = vic_set_wake,
259 * vic_init - initialise a vectored interrupt controller
260 * @base: iomem base address
261 * @irq_start: starting interrupt number, must be muliple of 32
262 * @vic_sources: bitmask of interrupt sources to allow
263 * @resume_sources: bitmask of interrupt sources to allow for resume
265 void __init vic_init(void __iomem *base, unsigned int irq_start,
266 u32 vic_sources, u32 resume_sources)
270 /* Disable all interrupts initially. */
272 writel(0, base + VIC_INT_SELECT);
273 writel(0, base + VIC_INT_ENABLE);
274 writel(~0, base + VIC_INT_ENABLE_CLEAR);
275 writel(0, base + VIC_IRQ_STATUS);
276 writel(0, base + VIC_ITCR);
277 writel(~0, base + VIC_INT_SOFT_CLEAR);
280 * Make sure we clear all existing interrupts
282 writel(0, base + VIC_PL190_VECT_ADDR);
283 for (i = 0; i < 19; i++) {
286 value = readl(base + VIC_PL190_VECT_ADDR);
287 writel(value, base + VIC_PL190_VECT_ADDR);
292 for (i = 0; i < 32; i++) {
293 if (vic_sources & (1 << i)) {
294 unsigned int irq = irq_start + i;
296 set_irq_chip(irq, &vic_chip);
297 set_irq_chip_data(irq, base);
298 set_irq_handler(irq, handle_level_irq);
299 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
303 vic_pm_register(base, irq_start, resume_sources);