2 * linux/arch/arm/common/vic.c
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/init.h>
23 #include <linux/list.h>
25 #include <linux/sysdev.h>
26 #include <linux/device.h>
27 #include <linux/amba/bus.h>
29 #include <asm/mach/irq.h>
30 #include <asm/hardware/vic.h>
32 #if defined(CONFIG_PM)
34 * struct vic_device - VIC PM device
35 * @sysdev: The system device which is registered.
36 * @irq: The IRQ number for the base of the VIC.
37 * @base: The register base for the VIC.
38 * @resume_sources: A bitmask of interrupts for resume.
39 * @resume_irqs: The IRQs enabled for resume.
40 * @int_select: Save for VIC_INT_SELECT.
41 * @int_enable: Save for VIC_INT_ENABLE.
42 * @soft_int: Save for VIC_INT_SOFT.
43 * @protect: Save for VIC_PROTECT.
46 struct sys_device sysdev;
58 /* we cannot allocate memory when VICs are initially registered */
59 static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
63 static inline struct vic_device *to_vic(struct sys_device *sys)
65 return container_of(sys, struct vic_device, sysdev);
67 #endif /* CONFIG_PM */
70 * vic_init2 - common initialisation code
71 * @base: Base of the VIC.
73 * Common initialisation code for registeration
76 static void vic_init2(void __iomem *base)
80 for (i = 0; i < 16; i++) {
81 void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
82 writel(VIC_VECT_CNTL_ENABLE | i, reg);
85 writel(32, base + VIC_PL190_DEF_VECT_ADDR);
88 #if defined(CONFIG_PM)
89 static int vic_class_resume(struct sys_device *dev)
91 struct vic_device *vic = to_vic(dev);
92 void __iomem *base = vic->base;
94 printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);
96 /* re-initialise static settings */
99 writel(vic->int_select, base + VIC_INT_SELECT);
100 writel(vic->protect, base + VIC_PROTECT);
102 /* set the enabled ints and then clear the non-enabled */
103 writel(vic->int_enable, base + VIC_INT_ENABLE);
104 writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);
106 /* and the same for the soft-int register */
108 writel(vic->soft_int, base + VIC_INT_SOFT);
109 writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
114 static int vic_class_suspend(struct sys_device *dev, pm_message_t state)
116 struct vic_device *vic = to_vic(dev);
117 void __iomem *base = vic->base;
119 printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);
121 vic->int_select = readl(base + VIC_INT_SELECT);
122 vic->int_enable = readl(base + VIC_INT_ENABLE);
123 vic->soft_int = readl(base + VIC_INT_SOFT);
124 vic->protect = readl(base + VIC_PROTECT);
126 /* set the interrupts (if any) that are used for
127 * resuming the system */
129 writel(vic->resume_irqs, base + VIC_INT_ENABLE);
130 writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
135 struct sysdev_class vic_class = {
137 .suspend = vic_class_suspend,
138 .resume = vic_class_resume,
142 * vic_pm_init - initicall to register VIC pm
144 * This is called via late_initcall() to register
145 * the resources for the VICs due to the early
146 * nature of the VIC's registration.
148 static int __init vic_pm_init(void)
150 struct vic_device *dev = vic_devices;
157 err = sysdev_class_register(&vic_class);
159 printk(KERN_ERR "%s: cannot register class\n", __func__);
163 for (id = 0; id < vic_id; id++, dev++) {
165 dev->sysdev.cls = &vic_class;
167 err = sysdev_register(&dev->sysdev);
169 printk(KERN_ERR "%s: failed to register device\n",
177 late_initcall(vic_pm_init);
180 * vic_pm_register - Register a VIC for later power management control
181 * @base: The base address of the VIC.
182 * @irq: The base IRQ for the VIC.
183 * @resume_sources: bitmask of interrupts allowed for resume sources.
185 * Register the VIC with the system device tree so that it can be notified
186 * of suspend and resume requests and ensure that the correct actions are
187 * taken to re-instate the settings on resume.
189 static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources)
191 struct vic_device *v;
193 if (vic_id >= ARRAY_SIZE(vic_devices))
194 printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
196 v = &vic_devices[vic_id];
198 v->resume_sources = resume_sources;
204 static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { }
205 #endif /* CONFIG_PM */
207 static void vic_ack_irq(unsigned int irq)
209 void __iomem *base = get_irq_chip_data(irq);
211 writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
212 /* moreover, clear the soft-triggered, in case it was the reason */
213 writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
216 static void vic_mask_irq(unsigned int irq)
218 void __iomem *base = get_irq_chip_data(irq);
220 writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
223 static void vic_unmask_irq(unsigned int irq)
225 void __iomem *base = get_irq_chip_data(irq);
227 writel(1 << irq, base + VIC_INT_ENABLE);
230 #if defined(CONFIG_PM)
231 static struct vic_device *vic_from_irq(unsigned int irq)
233 struct vic_device *v = vic_devices;
234 unsigned int base_irq = irq & ~31;
237 for (id = 0; id < vic_id; id++, v++) {
238 if (v->irq == base_irq)
245 static int vic_set_wake(unsigned int irq, unsigned int on)
247 struct vic_device *v = vic_from_irq(irq);
248 unsigned int off = irq & 31;
254 if (!(bit & v->resume_sources))
258 v->resume_irqs |= bit;
260 v->resume_irqs &= ~bit;
265 #define vic_set_wake NULL
266 #endif /* CONFIG_PM */
268 static struct irq_chip vic_chip = {
271 .mask = vic_mask_irq,
272 .unmask = vic_unmask_irq,
273 .set_wake = vic_set_wake,
277 * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
278 * The original cell has 32 interrupts, while the modified one has 64,
279 * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
280 * the probe function is called twice, with base set to offset 000
281 * and 020 within the page. We call this "second block".
283 static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
287 int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
289 /* Disable all interrupts initially. */
291 writel(0, base + VIC_INT_SELECT);
292 writel(0, base + VIC_INT_ENABLE);
293 writel(~0, base + VIC_INT_ENABLE_CLEAR);
294 writel(0, base + VIC_IRQ_STATUS);
295 writel(0, base + VIC_ITCR);
296 writel(~0, base + VIC_INT_SOFT_CLEAR);
299 * Make sure we clear all existing interrupts. The vector registers
300 * in this cell are after the second block of general registers,
301 * so we can address them using standard offsets, but only from
302 * the second base address, which is 0x20 in the page
305 writel(0, base + VIC_PL190_VECT_ADDR);
306 for (i = 0; i < 19; i++) {
309 value = readl(base + VIC_PL190_VECT_ADDR);
310 writel(value, base + VIC_PL190_VECT_ADDR);
312 /* ST has 16 vectors as well, but we don't enable them by now */
313 for (i = 0; i < 16; i++) {
314 void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
318 writel(32, base + VIC_PL190_DEF_VECT_ADDR);
321 for (i = 0; i < 32; i++) {
322 if (vic_sources & (1 << i)) {
323 unsigned int irq = irq_start + i;
325 set_irq_chip(irq, &vic_chip);
326 set_irq_chip_data(irq, base);
327 set_irq_handler(irq, handle_level_irq);
328 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
334 * vic_init - initialise a vectored interrupt controller
335 * @base: iomem base address
336 * @irq_start: starting interrupt number, must be muliple of 32
337 * @vic_sources: bitmask of interrupt sources to allow
338 * @resume_sources: bitmask of interrupt sources to allow for resume
340 void __init vic_init(void __iomem *base, unsigned int irq_start,
341 u32 vic_sources, u32 resume_sources)
345 enum amba_vendor vendor;
347 /* Identify which VIC cell this one is, by reading the ID */
348 for (i = 0; i < 4; i++) {
349 u32 addr = ((u32)base & PAGE_MASK) + 0xfe0 + (i * 4);
350 cellid |= (readl(addr) & 0xff) << (8 * i);
352 vendor = (cellid >> 12) & 0xff;
353 printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n",
354 base, cellid, vendor);
358 vic_init_st(base, irq_start, vic_sources);
361 printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
363 case AMBA_VENDOR_ARM:
367 /* Disable all interrupts initially. */
369 writel(0, base + VIC_INT_SELECT);
370 writel(0, base + VIC_INT_ENABLE);
371 writel(~0, base + VIC_INT_ENABLE_CLEAR);
372 writel(0, base + VIC_IRQ_STATUS);
373 writel(0, base + VIC_ITCR);
374 writel(~0, base + VIC_INT_SOFT_CLEAR);
377 * Make sure we clear all existing interrupts
379 writel(0, base + VIC_PL190_VECT_ADDR);
380 for (i = 0; i < 19; i++) {
383 value = readl(base + VIC_PL190_VECT_ADDR);
384 writel(value, base + VIC_PL190_VECT_ADDR);
389 for (i = 0; i < 32; i++) {
390 if (vic_sources & (1 << i)) {
391 unsigned int irq = irq_start + i;
393 set_irq_chip(irq, &vic_chip);
394 set_irq_chip_data(irq, base);
395 set_irq_handler(irq, handle_level_irq);
396 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
400 vic_pm_register(base, irq_start, resume_sources);