3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Alex Zuepke <azu@sysgo.de>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/proc-armv/ptrace.h>
32 #include <asm/hardware.h>
35 /* we always count down the max. */
36 #define TIMER_LOAD_VAL 0xffff
37 /* macro to read the 16 bit timer */
38 #define READ_TIMER (IO_TC1D & 0xffff)
41 #define IRQEN (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_INTR_ENABLE))
42 #define TM2CTRL (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_CONTROL))
43 #define TM2STAT (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_STATUS))
44 #define TIMER_LOAD_VAL NETARM_GEN_TSTAT_CTC_MASK
45 #define READ_TIMER (TM2STAT & NETARM_GEN_TSTAT_CTC_MASK)
48 #ifdef CONFIG_S3C4510B
49 /* require interrupts for the S3C4510B */
50 # ifndef CONFIG_USE_IRQ
51 # error CONFIG_USE_IRQ _must_ be defined when using CONFIG_S3C4510B
53 static struct _irq_handler IRQ_HANDLER[N_IRQS];
55 #endif /* CONFIG_S3C4510B */
58 void do_irq (struct pt_regs *pt_regs)
60 #if defined(CONFIG_S3C4510B)
63 while ( (pending = GET_REG( REG_INTOFFSET)) != 0x54) { /* sentinal value for no pending interrutps */
64 IRQ_HANDLER[pending>>2].m_func( IRQ_HANDLER[pending>>2].m_data);
66 /* clear pending interrupt */
67 PUT_REG( REG_INTPEND, (1<<(pending>>2)));
69 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
70 /* No do_irq() for IntegratorAP/CM720T as yet */
72 #error do_irq() not defined for this CPU type
77 #ifdef CONFIG_S3C4510B
78 static void default_isr( void *data) {
79 printf ("default_isr(): called for IRQ %d\n", (int)data);
82 static void timer_isr( void *data) {
83 unsigned int *pTime = (unsigned int *)data;
86 if ( !(*pTime % (CONFIG_SYS_HZ/4))) {
88 PUT_REG( REG_IOPDATA, GET_REG(REG_IOPDATA) ^ 0x1);
94 #if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
95 /* Use IntegratorAP routines in board/integratorap.c */
98 static ulong timestamp;
101 #if defined(CONFIG_USE_IRQ) && defined(CONFIG_S3C4510B)
102 int arch_interrupt_init (void)
106 /* install default interrupt handlers */
107 for ( i = 0; i < N_IRQS; i++) {
108 IRQ_HANDLER[i].m_data = (void *)i;
109 IRQ_HANDLER[i].m_func = default_isr;
112 /* configure interrupts for IRQ mode */
113 PUT_REG( REG_INTMODE, 0x0);
114 /* clear any pending interrupts */
115 PUT_REG( REG_INTPEND, 0x1FFFFF);
119 /* install interrupt handler for timer */
120 IRQ_HANDLER[INT_TIMER0].m_data = (void *)×tamp;
121 IRQ_HANDLER[INT_TIMER0].m_func = timer_isr;
127 int timer_init (void)
129 #if defined(CONFIG_NETARM)
130 /* disable all interrupts */
133 /* operate timer 2 in non-prescale mode */
134 TM2CTRL = ( NETARM_GEN_TIMER_SET_HZ(CONFIG_SYS_HZ) |
135 NETARM_GEN_TCTL_ENABLE |
136 NETARM_GEN_TCTL_INIT_COUNT(TIMER_LOAD_VAL));
138 /* set timer 2 counter */
139 lastdec = TIMER_LOAD_VAL;
140 #elif defined(CONFIG_S3C4510B)
141 /* configure free running timer 0 */
142 PUT_REG( REG_TMOD, 0x0);
144 CLR_REG( REG_TMOD, TM0_RUN);
146 /* Configure for interval mode */
147 CLR_REG( REG_TMOD, TM1_TOGGLE);
150 * Load Timer data register with count down value.
151 * count_down_val = CONFIG_SYS_SYS_CLK_FREQ/CONFIG_SYS_HZ
153 PUT_REG( REG_TDATA0, (CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ));
156 * Enable global interrupt
157 * Enable timer0 interrupt
159 CLR_REG( REG_INTMASK, ((1<<INT_GLOBAL) | (1<<INT_TIMER0)));
162 SET_REG( REG_TMOD, TM0_RUN);
163 #elif defined(CONFIG_TEGRA)
164 /* No timer routines for tegra as yet */
167 #error No timer_init() defined for this CPU type
174 #endif /* ! IntegratorAP */
177 * timer without interrupts
181 #if defined(CONFIG_NETARM)
183 ulong get_timer (ulong base)
185 return get_timer_masked () - base;
188 void __udelay (unsigned long usec)
193 tmo *= CONFIG_SYS_HZ;
196 tmo += get_timer (0);
198 while (get_timer_masked () < tmo)
201 ulong get_timer_masked (void)
203 ulong now = READ_TIMER;
205 if (lastdec >= now) {
207 timestamp += lastdec - now;
209 /* we have an overflow ... */
210 timestamp += lastdec + TIMER_LOAD_VAL - now;
217 void udelay_masked (unsigned long usec)
225 tmo *= CONFIG_SYS_HZ;
228 tmo = usec * CONFIG_SYS_HZ;
232 endtime = get_timer_masked () + tmo;
235 ulong now = get_timer_masked ();
236 diff = endtime - now;
240 #elif defined(CONFIG_S3C4510B)
242 ulong get_timer (ulong base)
244 return timestamp - base;
247 void __udelay (unsigned long usec)
251 ticks = (usec * CONFIG_SYS_HZ) / 1000000;
253 ticks += get_timer (0);
255 while (get_timer (0) < ticks)
260 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
261 /* No timer routines for IntegratorAP/CM720T as yet */
262 #elif defined(CONFIG_TEGRA)
263 /* No timer routines for tegra as yet */
265 #error Timer routines not defined for this CPU type