2 * Freescale i.MX23/i.MX28 common code
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Copyright (C) 2010 Freescale Semiconductor, Inc.
10 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/errno.h>
16 #include <asm/arch/clock.h>
17 #include <asm/imx-common/dma.h>
18 #include <asm/arch/gpio.h>
19 #include <asm/arch/iomux.h>
20 #include <asm/arch/imx-regs.h>
21 #include <asm/arch/sys_proto.h>
22 #include <linux/compiler.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 /* Lowlevel init isn't used on i.MX28, so just have a dummy here */
27 inline void lowlevel_init(void) {}
29 #define BOOT_CAUSE_MASK (RTC_PERSISTENT0_EXTERNAL_RESET | \
30 RTC_PERSISTENT0_ALARM_WAKE | \
31 RTC_PERSISTENT0_THERMAL_RESET)
33 static int wait_rtc_stat(u32 mask)
37 struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
38 u32 old_val = readl(&rtc_regs->hw_rtc_stat);
40 debug("stat=%x\n", old_val);
42 while ((val = readl(&rtc_regs->hw_rtc_stat)) & mask) {
45 debug("stat: %x -> %x\n", old_val, val);
51 return !!(readl(&rtc_regs->hw_rtc_stat) & mask);
54 void reset_cpu(ulong ignored) __attribute__((noreturn));
56 void reset_cpu(ulong ignored)
58 struct mxs_rtc_regs *rtc_regs =
59 (struct mxs_rtc_regs *)MXS_RTC_BASE;
60 struct mxs_lcdif_regs *lcdif_regs =
61 (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
65 * Shut down the LCD controller as it interferes with BootROM boot mode
68 writel(LCDIF_CTRL_RUN, &lcdif_regs->hw_lcdif_ctrl_clr);
70 reg = readl(&rtc_regs->hw_rtc_persistent0);
71 if (reg & BOOT_CAUSE_MASK) {
72 writel(reg & ~BOOT_CAUSE_MASK, &rtc_regs->hw_rtc_persistent0);
73 wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0);
76 /* Wait 1 mS before doing the actual watchdog reset */
77 writel(1, &rtc_regs->hw_rtc_watchdog);
78 writel(RTC_CTRL_WATCHDOGEN, &rtc_regs->hw_rtc_ctrl_set);
80 /* Endless loop, reset will exit from here */
85 void enable_caches(void)
87 #ifndef CONFIG_SYS_ICACHE_OFF
90 #ifndef CONFIG_SYS_DCACHE_OFF
96 * This function will craft a jumptable at 0x0 which will redirect interrupt
97 * vectoring to proper location of U-Boot in RAM.
99 * The structure of the jumptable will be as follows:
100 * ldr pc, [pc, #0x18] ..... for each vector, thus repeated 8 times
101 * <destination address> ... for each previous ldr, thus also repeated 8 times
103 * The "ldr pc, [pc, #0x18]" instruction above loads address from memory at
104 * offset 0x18 from current value of PC register. Note that PC is already
105 * incremented by 4 when computing the offset, so the effective offset is
106 * actually 0x20, this the associated <destination address>. Loading the PC
107 * register with an address performs a jump to that address.
109 void mx28_fixup_vt(uint32_t start_addr)
111 /* ldr pc, [pc, #0x18] */
112 /* Jumptable location is 0x0 */
113 uint32_t *vt = (uint32_t *)0x20;
114 uint32_t cr = get_cr();
117 for (i = 0; i < 8; i++) {
118 /* cppcheck-suppress nullPointer */
120 /* cppcheck-suppress nullPointer */
121 vt[i + 8] = start_addr + (4 * i);
124 memcpy(vt, (void *)start_addr + 0x20, 32);
126 >>>>>>> karo-tx-uboot
129 #ifdef CONFIG_ARCH_MISC_INIT
130 int arch_misc_init(void)
132 mx28_fixup_vt(gd->relocaddr);
137 #ifdef CONFIG_ARCH_CPU_INIT
138 int arch_cpu_init(void)
140 struct mxs_clkctrl_regs *clkctrl_regs =
141 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
142 extern uint32_t _start;
144 mx28_fixup_vt((uint32_t)&_start);
149 /* Clear bypass bit */
150 writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
151 &clkctrl_regs->hw_clkctrl_clkseq_set);
153 /* Set GPMI clock to ref_gpmi / 12 */
154 clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi,
155 CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1);
160 * Configure GPIO unit
164 #ifdef CONFIG_APBH_DMA
173 #if defined(CONFIG_DISPLAY_CPUINFO)
174 static const char *get_cpu_type(void)
176 struct mxs_digctl_regs *digctl_regs =
177 (struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
179 switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
180 case HW_DIGCTL_CHIPID_MX23:
182 case HW_DIGCTL_CHIPID_MX28:
189 static const char *get_cpu_rev(void)
191 struct mxs_digctl_regs *digctl_regs =
192 (struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
193 uint8_t rev = readl(&digctl_regs->hw_digctl_chipid) & 0x000000FF;
195 switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
196 case HW_DIGCTL_CHIPID_MX23:
211 case HW_DIGCTL_CHIPID_MX28:
223 int print_cpuinfo(void)
225 struct mxs_spl_data *data = (struct mxs_spl_data *)
226 ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
228 printf("CPU: Freescale i.MX%s rev%s at %d MHz\n",
231 mxc_get_clock(MXC_ARM_CLK) / 1000000);
232 printf("BOOT: %s\n", mxs_boot_modes[data->boot_mode_idx].mode);
237 #define pr_clk(n, c) { \
238 unsigned long clk = c; \
239 printf("%-5s %3lu.%03lu MHz\n", #n ":", clk / 1000000, \
240 clk / 1000 % 1000); \
243 int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
245 pr_clk(CPU, mxc_get_clock(MXC_ARM_CLK));
246 pr_clk(APBH, mxc_get_clock(MXC_AHB_CLK));
247 pr_clk(APBX, mxc_get_clock(MXC_XBUS_CLK));
248 pr_clk(IO0, mxc_get_clock(MXC_IO0_CLK) * 1000);
249 pr_clk(IO1, mxc_get_clock(MXC_IO1_CLK) * 1000);
250 pr_clk(EMI, mxc_get_clock(MXC_EMI_CLK) * 1000000);
251 pr_clk(GPMI, mxc_get_clock(MXC_GPMI_CLK));
256 * Initializes on-chip ethernet controllers.
258 #if defined(CONFIG_MX28) && defined(CONFIG_CMD_NET)
259 int cpu_eth_init(bd_t *bis)
261 struct mxs_clkctrl_regs *clkctrl_regs =
262 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
264 /* Turn on ENET clocks */
265 clrbits_le32(&clkctrl_regs->hw_clkctrl_enet,
266 CLKCTRL_ENET_SLEEP | CLKCTRL_ENET_DISABLE);
268 /* Set up ENET PLL for 50 MHz */
269 /* Power on ENET PLL */
270 writel(CLKCTRL_PLL2CTRL0_POWER,
271 &clkctrl_regs->hw_clkctrl_pll2ctrl0_set);
276 * Enable pad output; must be done BEFORE enabling PLL
277 * according to i.MX28 Ref. Manual Rev. 1, 2010 p. 883
279 setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN);
281 /* Gate on ENET PLL */
282 writel(CLKCTRL_PLL2CTRL0_CLKGATE,
283 &clkctrl_regs->hw_clkctrl_pll2ctrl0_clr);
290 __weak void mx28_adjust_mac(int dev_id, unsigned char *mac)
293 mac[1] = 0x04; /* Use FSL vendor MAC address by default */
295 if (dev_id == 1) /* Let MAC1 be MAC0 + 1 by default */
299 #ifdef CONFIG_MX28_FEC_MAC_IN_OCOTP
301 #define MXS_OCOTP_MAX_TIMEOUT 1000000
302 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
304 struct mxs_ocotp_regs *ocotp_regs =
305 (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
310 writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
312 if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
313 MXS_OCOTP_MAX_TIMEOUT)) {
314 printf("MXS FEC: Can't get MAC from OCOTP\n");
318 data = readl(&ocotp_regs->hw_ocotp_cust0);
320 mac[2] = (data >> 24) & 0xff;
321 mac[3] = (data >> 16) & 0xff;
322 mac[4] = (data >> 8) & 0xff;
323 mac[5] = data & 0xff;
324 mx28_adjust_mac(dev_id, mac);
327 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
333 int mxs_dram_init(void)
335 struct mxs_spl_data *data = (struct mxs_spl_data *)
336 ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
338 if (data->mem_dram_size == 0) {
340 "Error, the RAM size passed up from SPL is 0!\n");
344 gd->ram_size = data->mem_dram_size;
349 clocks, CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks,