2 * Freescale i.MX28 Boot PMIC init
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/imx-regs.h>
17 #ifdef CONFIG_SYS_MXS_VDD5V_ONLY
18 #define DCDC4P2_DROPOUT_CONFIG POWER_DCDC4P2_DROPOUT_CTRL_100MV | \
19 POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2
21 #define DCDC4P2_DROPOUT_CONFIG POWER_DCDC4P2_DROPOUT_CTRL_100MV | \
22 POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL
24 #ifdef CONFIG_SYS_SPL_VDDD_VAL
25 #define VDDD_VAL CONFIG_SYS_SPL_VDDD_VAL
29 #ifdef CONFIG_SYS_SPL_VDDIO_VAL
30 #define VDDIO_VAL CONFIG_SYS_SPL_VDDIO_VAL
32 #define VDDIO_VAL 3300
34 #ifdef CONFIG_SYS_SPL_VDDA_VAL
35 #define VDDA_VAL CONFIG_SYS_SPL_VDDA_VAL
39 #ifdef CONFIG_SYS_SPL_VDDMEM_VAL
40 #define VDDMEM_VAL CONFIG_SYS_SPL_VDDMEM_VAL
42 #define VDDMEM_VAL 1700
45 #ifdef CONFIG_SYS_SPL_VDDD_BO_VAL
46 #define VDDD_BO_VAL CONFIG_SYS_SPL_VDDD_BO_VAL
48 #define VDDD_BO_VAL 150
50 #ifdef CONFIG_SYS_SPL_VDDIO_BO_VAL
51 #define VDDIO_BO_VAL CONFIG_SYS_SPL_VDDIO_BO_VAL
53 #define VDDIO_BO_VAL 150
55 #ifdef CONFIG_SYS_SPL_VDDA_BO_VAL
56 #define VDDA_BO_VAL CONFIG_SYS_SPL_VDDA_BO_VAL
58 #define VDDA_BO_VAL 175
60 #ifdef CONFIG_SYS_SPL_VDDMEM_BO_VAL
61 #define VDDMEM_BO_VAL CONFIG_SYS_SPL_VDDMEM_BO_VAL
63 #define VDDMEM_BO_VAL 25
66 #ifdef CONFIG_SYS_SPL_BATT_BO_LEVEL
67 #if CONFIG_SYS_SPL_BATT_BO_LEVEL < 2400 || CONFIG_SYS_SPL_BATT_BO_LEVEL > 3640
68 #error CONFIG_SYS_SPL_BATT_BO_LEVEL out of range
70 #define BATT_BO_VAL (((CONFIG_SYS_SPL_BATT_BO_LEVEL) - 2400) / 40)
72 /* Brownout default at 3V */
73 #define BATT_BO_VAL ((3000 - 2400) / 40)
76 #ifdef CONFIG_SYS_SPL_FIXED_BATT_SUPPLY
77 static const int fixed_batt_supply = 1;
79 static const int fixed_batt_supply;
82 static struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
85 * mxs_power_clock2xtal() - Switch CPU core clock source to 24MHz XTAL
87 * This function switches the CPU core clock from PLL to 24MHz XTAL
88 * oscilator. This is necessary if the PLL is being reconfigured to
89 * prevent crash of the CPU core.
91 static void mxs_power_clock2xtal(void)
93 struct mxs_clkctrl_regs *clkctrl_regs =
94 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
96 debug("SPL: Switching CPU clock to 24MHz XTAL\n");
98 /* Set XTAL as CPU reference clock */
99 writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
100 &clkctrl_regs->hw_clkctrl_clkseq_set);
104 * mxs_power_clock2pll() - Switch CPU core clock source to PLL
106 * This function switches the CPU core clock from 24MHz XTAL oscilator
107 * to PLL. This can only be called once the PLL has re-locked and once
108 * the PLL is stable after reconfiguration.
110 static void mxs_power_clock2pll(void)
112 struct mxs_clkctrl_regs *clkctrl_regs =
113 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
115 debug("SPL: Switching CPU core clock source to PLL\n");
118 * TODO: Are we really? It looks like we turn on PLL0, but we then
119 * set the CLKCTRL_CLKSEQ_BYPASS_CPU bit of the (which was already
120 * set by mxs_power_clock2xtal()). Clearing this bit here seems to
121 * introduce some instability (causing the CPU core to hang). Maybe
122 * we aren't giving PLL0 enough time to stabilise?
124 setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
125 CLKCTRL_PLL0CTRL0_POWER);
129 * TODO: Should the PLL0 FORCE_LOCK bit be set here followed be a
130 * wait on the PLL0 LOCK bit?
132 setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq,
133 CLKCTRL_CLKSEQ_BYPASS_CPU);
136 static int mxs_power_wait_rtc_stat(u32 mask)
138 int timeout = 5000; /* 3 ms according to i.MX28 Ref. Manual */
140 struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
142 while ((val = readl(&rtc_regs->hw_rtc_stat)) & mask) {
147 return !!(readl(&rtc_regs->hw_rtc_stat) & mask);
151 * mxs_power_set_auto_restart() - Set the auto-restart bit
153 * This function ungates the RTC block and sets the AUTO_RESTART
154 * bit to work around a design bug on MX28EVK Rev. A .
156 static int mxs_power_set_auto_restart(int on)
158 struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
160 debug("SPL: Setting auto-restart bit\n");
162 if (mxs_power_wait_rtc_stat(RTC_STAT_STALE_REGS_PERSISTENT0))
165 /* Do nothing if flag already set */
166 if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
169 if ((!(readl(&rtc_regs->hw_rtc_persistent0) &
170 RTC_PERSISTENT0_AUTO_RESTART) ^ !on) == 0)
173 if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0))
176 clrsetbits_le32(&rtc_regs->hw_rtc_persistent0,
177 !on * RTC_PERSISTENT0_AUTO_RESTART,
178 !!on * RTC_PERSISTENT0_AUTO_RESTART);
179 if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0))
186 * mxs_power_set_linreg() - Set linear regulators 25mV below DC-DC converter
188 * This function configures the VDDIO, VDDA and VDDD linear regulators output
189 * to be 25mV below the VDDIO, VDDA and VDDD output from the DC-DC switching
190 * converter. This is the recommended setting for the case where we use both
191 * linear regulators and DC-DC converter to power the VDDIO rail.
193 static void mxs_power_set_linreg(void)
195 /* Set linear regulator 25mV below switching converter */
196 debug("SPL: Setting VDDD 25mV below DC-DC converters\n");
197 clrsetbits_le32(&power_regs->hw_power_vdddctrl,
198 POWER_VDDDCTRL_LINREG_OFFSET_MASK,
199 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
201 debug("SPL: Setting VDDA 25mV below DC-DC converters\n");
202 clrsetbits_le32(&power_regs->hw_power_vddactrl,
203 POWER_VDDACTRL_LINREG_OFFSET_MASK,
204 POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
206 debug("SPL: Setting VDDIO 25mV below DC-DC converters\n");
207 clrsetbits_le32(&power_regs->hw_power_vddioctrl,
208 POWER_VDDIOCTRL_LINREG_OFFSET_MASK,
209 POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
213 * mxs_get_batt_volt() - Measure battery input voltage
215 * This function retrieves the battery input voltage and returns it.
217 static int mxs_get_batt_volt(void)
219 uint32_t volt = readl(&power_regs->hw_power_battmonitor);
221 volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
222 volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
225 debug("SPL: Battery Voltage = %dmV\n", volt);
230 * mxs_is_batt_ready() - Test if the battery provides enough voltage to boot
232 * This function checks if the battery input voltage is higher than 3.6V and
233 * therefore allows the system to successfully boot using this power source.
235 static int mxs_is_batt_ready(void)
237 return (mxs_get_batt_volt() >= 3600);
241 * mxs_is_batt_good() - Test if battery is operational at all
243 * This function starts recharging the battery and tests if the input current
244 * provided by the 5V input recharging the battery is also sufficient to power
245 * the DC-DC converter.
247 static int mxs_is_batt_good(void)
249 uint32_t volt = mxs_get_batt_volt();
251 if ((volt >= 2400) && (volt <= 4300)) {
252 debug("SPL: Battery is good\n");
256 clrsetbits_le32(&power_regs->hw_power_5vctrl,
257 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
258 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
259 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
260 &power_regs->hw_power_5vctrl_clr);
262 clrsetbits_le32(&power_regs->hw_power_charge,
263 POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
264 POWER_CHARGE_STOP_ILIMIT_10MA | 0x3);
266 writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr);
267 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
268 &power_regs->hw_power_5vctrl_clr);
272 volt = mxs_get_batt_volt();
275 debug("SPL: Battery Voltage too high\n");
280 debug("SPL: Battery is good\n");
284 writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
285 &power_regs->hw_power_charge_clr);
286 writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
294 debug("SPL: Battery Voltage too low\n");
299 * mxs_power_setup_5v_detect() - Start the 5V input detection comparator
301 * This function enables the 5V detection comparator and sets the 5V valid
302 * threshold to 4.4V . We use 4.4V threshold here to make sure that even
303 * under high load, the voltage drop on the 5V input won't be so critical
304 * to cause undervolt on the 4P2 linear regulator supplying the DC-DC
305 * converter and thus making the system crash.
307 static void mxs_power_setup_5v_detect(void)
309 /* Start 5V detection */
310 debug("SPL: Starting 5V input detection comparator\n");
311 clrsetbits_le32(&power_regs->hw_power_5vctrl,
312 POWER_5VCTRL_VBUSVALID_TRSH_MASK,
313 POWER_5VCTRL_VBUSVALID_TRSH_4V4 |
314 POWER_5VCTRL_PWRUP_VBUS_CMPS);
318 * mxs_src_power_init() - Preconfigure the power block
320 * This function configures reasonable values for the DC-DC control loop
321 * and battery monitor.
323 static void mxs_src_power_init(void)
325 debug("SPL: Pre-Configuring power block\n");
327 debug("SPL: Pre-Configuring power block\n");
329 /* Improve efficieny and reduce transient ripple */
330 writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
331 POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
333 clrsetbits_le32(&power_regs->hw_power_dclimits,
334 POWER_DCLIMITS_POSLIMIT_BUCK_MASK,
335 0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET);
337 if (!fixed_batt_supply) {
338 /* FIXME: This requires the LRADC to be set up! */
339 setbits_le32(&power_regs->hw_power_battmonitor,
340 POWER_BATTMONITOR_EN_BATADJ);
342 clrbits_le32(&power_regs->hw_power_battmonitor,
343 POWER_BATTMONITOR_EN_BATADJ);
346 /* Increase the RCSCALE level for quick DCDC response to dynamic load */
347 clrsetbits_le32(&power_regs->hw_power_loopctrl,
348 POWER_LOOPCTRL_EN_RCSCALE_MASK,
349 POWER_LOOPCTRL_RCSCALE_THRESH |
350 POWER_LOOPCTRL_EN_RCSCALE_8X);
352 clrsetbits_le32(&power_regs->hw_power_minpwr,
353 POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
355 if (!fixed_batt_supply) {
356 /* 5V to battery handoff ... FIXME */
357 setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
359 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
364 * mxs_power_init_4p2_params() - Configure the parameters of the 4P2 regulator
366 * This function configures the necessary parameters for the 4P2 linear
367 * regulator to supply the DC-DC converter from 5V input.
369 static void mxs_power_init_4p2_params(void)
371 debug("SPL: Configuring common 4P2 regulator params\n");
373 debug("SPL: Configuring common 4P2 regulator params\n");
375 /* Setup 4P2 parameters */
376 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
377 POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
378 POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET));
380 clrsetbits_le32(&power_regs->hw_power_5vctrl,
381 POWER_5VCTRL_HEADROOM_ADJ_MASK,
382 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET);
384 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
385 POWER_DCDC4P2_DROPOUT_CTRL_MASK,
386 DCDC4P2_DROPOUT_CONFIG);
388 clrsetbits_le32(&power_regs->hw_power_5vctrl,
389 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
390 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
394 * mxs_enable_4p2_dcdc_input() - Enable or disable the DCDC input from 4P2
395 * @xfer: Select if the input shall be enabled or disabled
397 * This function enables or disables the 4P2 input into the DC-DC converter.
399 static void mxs_enable_4p2_dcdc_input(int xfer)
401 uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
402 uint32_t prev_5v_brnout, prev_5v_droop;
404 debug("SPL: %s 4P2 DC-DC Input\n", xfer ? "Enabling" : "Disabling");
406 if (xfer && (readl(&power_regs->hw_power_5vctrl) &
407 POWER_5VCTRL_ENABLE_DCDC)) {
411 prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
412 POWER_5VCTRL_PWDN_5VBRNOUT;
413 prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
414 POWER_CTRL_ENIRQ_VDD5V_DROOP;
416 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
417 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
418 &power_regs->hw_power_reset);
420 clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
423 * Recording orignal values that will be modified temporarlily
424 * to handle a chip bug. See chip errata for CQ ENGR00115837
426 tmp = readl(&power_regs->hw_power_5vctrl);
427 vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK;
428 vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT;
430 pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO;
433 * Disable mechanisms that get erroneously tripped by when setting
434 * the DCDC4P2 EN_DCDC
436 clrbits_le32(&power_regs->hw_power_5vctrl,
437 POWER_5VCTRL_VBUSVALID_5VDETECT |
438 POWER_5VCTRL_VBUSVALID_TRSH_MASK);
440 writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set);
443 setbits_le32(&power_regs->hw_power_5vctrl,
444 POWER_5VCTRL_DCDC_XFER);
446 clrbits_le32(&power_regs->hw_power_5vctrl,
447 POWER_5VCTRL_DCDC_XFER);
449 setbits_le32(&power_regs->hw_power_5vctrl,
450 POWER_5VCTRL_ENABLE_DCDC);
452 setbits_le32(&power_regs->hw_power_dcdc4p2,
453 POWER_DCDC4P2_ENABLE_DCDC);
458 clrsetbits_le32(&power_regs->hw_power_5vctrl,
459 POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
462 writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set);
465 clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
467 while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
468 writel(POWER_CTRL_VBUS_VALID_IRQ,
469 &power_regs->hw_power_ctrl_clr);
471 if (prev_5v_brnout) {
472 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
473 &power_regs->hw_power_5vctrl_set);
474 writel(POWER_RESET_UNLOCK_KEY,
475 &power_regs->hw_power_reset);
477 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
478 &power_regs->hw_power_5vctrl_clr);
479 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
480 &power_regs->hw_power_reset);
483 while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
484 writel(POWER_CTRL_VDD5V_DROOP_IRQ,
485 &power_regs->hw_power_ctrl_clr);
488 clrbits_le32(&power_regs->hw_power_ctrl,
489 POWER_CTRL_ENIRQ_VDD5V_DROOP);
491 setbits_le32(&power_regs->hw_power_ctrl,
492 POWER_CTRL_ENIRQ_VDD5V_DROOP);
496 * mxs_power_init_4p2_regulator() - Start the 4P2 regulator
498 * This function enables the 4P2 regulator and switches the DC-DC converter
499 * to use the 4P2 input.
501 static void mxs_power_init_4p2_regulator(void)
505 debug("SPL: Enabling 4P2 regulator\n");
507 setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
509 writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
511 writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
512 &power_regs->hw_power_5vctrl_clr);
513 clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK);
515 /* Power up the 4p2 rail and logic/control */
516 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
517 &power_regs->hw_power_5vctrl_clr);
520 * Start charging up the 4p2 capacitor. We ramp of this charge
521 * gradually to avoid large inrush current from the 5V cable which can
522 * cause transients/problems
524 debug("SPL: Charging 4P2 capacitor\n");
525 mxs_enable_4p2_dcdc_input(0);
527 if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
529 * If we arrived here, we were unable to recover from mx23 chip
530 * errata 5837. 4P2 is disabled and sufficient battery power is
531 * not present. Exiting to not enable DCDC power during 5V
534 clrbits_le32(&power_regs->hw_power_dcdc4p2,
535 POWER_DCDC4P2_ENABLE_DCDC);
536 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
537 &power_regs->hw_power_5vctrl_set);
539 debug("SPL: Unable to recover from mx23 errata 5837\n");
544 * Here we set the 4p2 brownout level to something very close to 4.2V.
545 * We then check the brownout status. If the brownout status is false,
546 * the voltage is already close to the target voltage of 4.2V so we
547 * can go ahead and set the 4P2 current limit to our max target limit.
548 * If the brownout status is true, we need to ramp up the current limit
549 * so that we don't cause large inrush current issues. We step up the
550 * current limit until the brownout status is false or until we've
551 * reached our maximum defined 4p2 current limit.
553 debug("SPL: Setting 4P2 brownout level\n");
554 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
555 POWER_DCDC4P2_BO_MASK,
556 22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
558 if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
559 setbits_le32(&power_regs->hw_power_5vctrl,
560 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
562 tmp = (readl(&power_regs->hw_power_5vctrl) &
563 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
564 POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
566 if (!(readl(&power_regs->hw_power_sts) &
567 POWER_STS_DCDC_4P2_BO)) {
568 tmp = readl(&power_regs->hw_power_5vctrl);
569 tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
571 writel(tmp, &power_regs->hw_power_5vctrl);
575 tmp2 = readl(&power_regs->hw_power_5vctrl);
576 tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
578 POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
579 writel(tmp2, &power_regs->hw_power_5vctrl);
585 clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
586 writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
590 * mxs_power_init_dcdc_4p2_source() - Switch DC-DC converter to 4P2 source
592 * This function configures the DC-DC converter to be supplied from the 4P2
595 static void mxs_power_init_dcdc_4p2_source(void)
597 debug("SPL: Switching DC-DC converters to 4P2\n");
599 debug("SPL: Switching DC-DC converters to 4P2\n");
601 if (!(readl(&power_regs->hw_power_dcdc4p2) &
602 POWER_DCDC4P2_ENABLE_DCDC)) {
603 debug("SPL: Already switched - aborting\n");
607 mxs_enable_4p2_dcdc_input(1);
609 if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
610 clrbits_le32(&power_regs->hw_power_dcdc4p2,
611 POWER_DCDC4P2_ENABLE_DCDC);
612 writel(POWER_5VCTRL_ENABLE_DCDC,
613 &power_regs->hw_power_5vctrl_clr);
614 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
615 &power_regs->hw_power_5vctrl_set);
620 * mxs_power_enable_4p2() - Power up the 4P2 regulator
622 * This function drives the process of powering up the 4P2 linear regulator
623 * and switching the DC-DC converter input over to the 4P2 linear regulator.
625 static void mxs_power_enable_4p2(void)
627 uint32_t vdddctrl, vddactrl, vddioctrl;
630 debug("SPL: Powering up 4P2 regulator\n");
632 vdddctrl = readl(&power_regs->hw_power_vdddctrl);
633 vddactrl = readl(&power_regs->hw_power_vddactrl);
634 vddioctrl = readl(&power_regs->hw_power_vddioctrl);
636 setbits_le32(&power_regs->hw_power_vdddctrl,
637 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
638 POWER_VDDDCTRL_PWDN_BRNOUT);
640 setbits_le32(&power_regs->hw_power_vddactrl,
641 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
642 POWER_VDDACTRL_PWDN_BRNOUT);
644 setbits_le32(&power_regs->hw_power_vddioctrl,
645 POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
647 mxs_power_init_4p2_params();
648 mxs_power_init_4p2_regulator();
650 /* Shutdown battery (none present) */
651 if (!mxs_is_batt_ready()) {
652 clrbits_le32(&power_regs->hw_power_dcdc4p2,
653 POWER_DCDC4P2_BO_MASK);
654 writel(POWER_CTRL_DCDC4P2_BO_IRQ,
655 &power_regs->hw_power_ctrl_clr);
656 writel(POWER_CTRL_ENIRQ_DCDC4P2_BO,
657 &power_regs->hw_power_ctrl_clr);
660 mxs_power_init_dcdc_4p2_source();
662 writel(vdddctrl, &power_regs->hw_power_vdddctrl);
664 writel(vddactrl, &power_regs->hw_power_vddactrl);
666 writel(vddioctrl, &power_regs->hw_power_vddioctrl);
669 * Check if FET is enabled on either powerout and if so,
673 tmp |= !(readl(&power_regs->hw_power_vdddctrl) &
674 POWER_VDDDCTRL_DISABLE_FET);
675 tmp |= !(readl(&power_regs->hw_power_vddactrl) &
676 POWER_VDDACTRL_DISABLE_FET);
677 tmp |= !(readl(&power_regs->hw_power_vddioctrl) &
678 POWER_VDDIOCTRL_DISABLE_FET);
680 writel(POWER_CHARGE_ENABLE_LOAD,
681 &power_regs->hw_power_charge_clr);
683 debug("SPL: 4P2 regulator powered-up\n");
687 * mxs_boot_valid_5v() - Boot from 5V supply
689 * This function configures the power block to boot from valid 5V input.
690 * This is called only if the 5V is reliable and can properly supply the
691 * CPU. This function proceeds to configure the 4P2 converter to be supplied
694 static void mxs_boot_valid_5v(void)
696 debug("SPL: Booting from 5V supply\n");
698 debug("SPL: Booting from 5V supply\n");
701 * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
702 * disconnect event. FIXME
704 writel(POWER_5VCTRL_VBUSVALID_5VDETECT,
705 &power_regs->hw_power_5vctrl_set);
707 /* Configure polarity to check for 5V disconnection. */
708 writel(POWER_CTRL_POLARITY_VBUSVALID |
709 POWER_CTRL_POLARITY_VDD5V_GT_VDDIO,
710 &power_regs->hw_power_ctrl_clr);
712 writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
713 &power_regs->hw_power_ctrl_clr);
715 mxs_power_enable_4p2();
719 * mxs_powerdown() - Shut down the system
721 * This function powers down the CPU completely.
723 static void mxs_powerdown(void)
725 debug("Powering Down\n");
727 writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
728 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
729 &power_regs->hw_power_reset);
733 * mxs_batt_boot() - Configure the power block to boot from battery input
735 * This function configures the power block to boot from the battery voltage
738 static void mxs_batt_boot(void)
740 debug("SPL: Configuring power block to boot from battery\n");
742 debug("SPL: Configuring power block to boot from battery\n");
744 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
745 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
747 clrbits_le32(&power_regs->hw_power_dcdc4p2,
748 POWER_DCDC4P2_ENABLE_DCDC | POWER_DCDC4P2_ENABLE_4P2);
749 writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_clr);
751 /* 5V to battery handoff. */
752 setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
754 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
756 writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
758 clrsetbits_le32(&power_regs->hw_power_minpwr,
759 POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
761 mxs_power_set_linreg();
763 clrbits_le32(&power_regs->hw_power_vdddctrl,
764 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG);
766 clrbits_le32(&power_regs->hw_power_vddactrl,
767 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG);
769 clrbits_le32(&power_regs->hw_power_vddioctrl,
770 POWER_VDDIOCTRL_DISABLE_FET);
772 setbits_le32(&power_regs->hw_power_5vctrl,
773 POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
775 setbits_le32(&power_regs->hw_power_5vctrl,
776 POWER_5VCTRL_ENABLE_DCDC);
778 clrsetbits_le32(&power_regs->hw_power_5vctrl,
779 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
780 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
782 mxs_power_enable_4p2();
786 * mxs_handle_5v_conflict() - Test if the 5V input is reliable
788 * This function tests if the 5V input can reliably supply the system. If it
789 * can, then proceed to configuring the system to boot from 5V source, otherwise
790 * try booting from battery supply. If we can not boot from battery supply
791 * either, shut down the system.
793 static void mxs_handle_5v_conflict(void)
797 debug("SPL: Resolving 5V conflict\n");
799 setbits_le32(&power_regs->hw_power_vddioctrl,
800 POWER_VDDIOCTRL_BO_OFFSET_MASK);
803 tmp = readl(&power_regs->hw_power_sts);
805 if (tmp & POWER_STS_VDDIO_BO) {
807 * If VDDIO has a brownout, then the VDD5V_GT_VDDIO
810 debug("SPL: VDDIO has a brownout\n");
815 if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
816 debug("SPL: POWER_STS_VDD5V_GT_VDDIO is set\n");
820 debug("SPL: POWER_STS_VDD5V_GT_VDDIO is not set\n");
826 * TODO: I can't see this being reached. We'll either
827 * powerdown or boot from a stable 5V supply.
829 if (tmp & POWER_STS_PSWITCH_MASK) {
830 debug("SPL: POWER_STS_PSWITCH_MASK is set\n");
838 * mxs_5v_boot() - Configure the power block to boot from 5V input
840 * This function handles configuration of the power block when supplied by
843 static void mxs_5v_boot(void)
845 debug("SPL: Configuring power block to boot from 5V input\n");
847 debug("SPL: Configuring power block to boot from 5V input\n");
850 * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
851 * but their implementation always returns 1 so we omit it here.
853 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
854 debug("SPL: 5V VDD good\n");
860 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
861 debug("SPL: 5V VDD good (after delay)\n");
866 debug("SPL: 5V VDD not good\n");
867 mxs_handle_5v_conflict();
870 static void mxs_fixed_batt_boot(void)
872 writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
874 setbits_le32(&power_regs->hw_power_5vctrl,
875 POWER_5VCTRL_ENABLE_DCDC |
876 POWER_5VCTRL_ILIMIT_EQ_ZERO |
877 POWER_5VCTRL_PWDN_5VBRNOUT |
878 POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
880 writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
882 clrbits_le32(&power_regs->hw_power_vdddctrl,
883 POWER_VDDDCTRL_DISABLE_FET |
884 POWER_VDDDCTRL_ENABLE_LINREG |
885 POWER_VDDDCTRL_DISABLE_STEPPING);
887 clrbits_le32(&power_regs->hw_power_vddactrl,
888 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
889 POWER_VDDACTRL_DISABLE_STEPPING);
891 clrbits_le32(&power_regs->hw_power_vddioctrl,
892 POWER_VDDIOCTRL_DISABLE_FET |
893 POWER_VDDIOCTRL_DISABLE_STEPPING);
895 /* Stop 5V detection */
896 writel(POWER_5VCTRL_PWRUP_VBUS_CMPS,
897 &power_regs->hw_power_5vctrl_clr);
901 * mxs_init_batt_bo() - Configure battery brownout threshold
903 * This function configures the battery input brownout threshold. The value
904 * at which the battery brownout happens is configured to 3.0V in the code.
906 static void mxs_init_batt_bo(void)
908 debug("SPL: Initialising battery brown-out level to 3.0V\n");
910 debug("SPL: Initialising battery brown-out level to 3.0V\n");
913 clrsetbits_le32(&power_regs->hw_power_battmonitor,
914 POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
915 BATT_BO_VAL << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
917 writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
918 writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
922 * mxs_switch_vddd_to_dcdc_source() - Switch VDDD rail to DC-DC converter
924 * This function turns off the VDDD linear regulator and therefore makes
925 * the VDDD rail be supplied only by the DC-DC converter.
927 static void mxs_switch_vddd_to_dcdc_source(void)
929 debug("SPL: Switching VDDD to DC-DC converters\n");
931 debug("SPL: Switching VDDD to DC-DC converters\n");
933 clrsetbits_le32(&power_regs->hw_power_vdddctrl,
934 POWER_VDDDCTRL_LINREG_OFFSET_MASK,
935 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
937 clrbits_le32(&power_regs->hw_power_vdddctrl,
938 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
939 POWER_VDDDCTRL_DISABLE_STEPPING);
943 * mxs_power_configure_power_source() - Configure power block source
945 * This function is the core of the power configuration logic. The function
946 * selects the power block input source and configures the whole power block
947 * accordingly. After the configuration is complete and the system is stable
948 * again, the function switches the CPU clock source back to PLL. Finally,
949 * the function switches the voltage rails to DC-DC converter.
951 static void mxs_power_configure_power_source(void)
953 struct mxs_lradc_regs *lradc_regs =
954 (struct mxs_lradc_regs *)MXS_LRADC_BASE;
956 debug("SPL: Configuring power source\n");
958 mxs_src_power_init();
960 if (!fixed_batt_supply) {
961 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
962 if (mxs_is_batt_ready()) {
963 /* 5V source detected, good battery detected. */
966 if (!mxs_is_batt_good()) {
967 /* 5V source detected, bad battery detected. */
968 writel(LRADC_CONVERSION_AUTOMATIC,
969 &lradc_regs->hw_lradc_conversion_clr);
970 clrbits_le32(&power_regs->hw_power_battmonitor,
971 POWER_BATTMONITOR_BATT_VAL_MASK);
976 /* 5V not detected, booting from battery. */
980 mxs_fixed_batt_boot();
984 * TODO: Do not switch CPU clock to PLL if we are VDD5V is sourced
987 mxs_power_clock2pll();
991 mxs_switch_vddd_to_dcdc_source();
993 #ifdef CONFIG_SOC_MX23
994 /* Fire up the VDDMEM LinReg now that we're all set. */
995 debug("SPL: Enabling mx23 VDDMEM linear regulator\n");
996 writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT,
997 &power_regs->hw_power_vddmemctrl);
1002 * mxs_enable_output_rail_protection() - Enable power rail protection
1004 * This function enables overload protection on the power rails. This is
1005 * triggered if the power rails' voltage drops rapidly due to overload and
1006 * in such case, the supply to the powerrail is cut-off, protecting the
1007 * CPU from damage. Note that under such condition, the system will likely
1008 * crash or misbehave.
1010 static void mxs_enable_output_rail_protection(void)
1012 debug("SPL: Enabling output rail protection\n");
1014 debug("SPL: Enabling output rail protection\n");
1016 writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
1017 POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
1019 setbits_le32(&power_regs->hw_power_vdddctrl,
1020 POWER_VDDDCTRL_PWDN_BRNOUT);
1022 setbits_le32(&power_regs->hw_power_vddactrl,
1023 POWER_VDDACTRL_PWDN_BRNOUT);
1025 setbits_le32(&power_regs->hw_power_vddioctrl,
1026 POWER_VDDIOCTRL_PWDN_BRNOUT);
1030 * mxs_get_vddio_power_source_off() - Get VDDIO rail power source
1032 * This function tests if the VDDIO rail is supplied by linear regulator
1033 * or by the DC-DC converter. Returns 1 if powered by linear regulator,
1034 * returns 0 if powered by the DC-DC converter.
1036 static int mxs_get_vddio_power_source_off(void)
1040 if ((readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) &&
1041 !(readl(&power_regs->hw_power_5vctrl) &
1042 POWER_5VCTRL_ILIMIT_EQ_ZERO)) {
1044 tmp = readl(&power_regs->hw_power_vddioctrl);
1045 if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
1046 if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
1047 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
1052 if (!(readl(&power_regs->hw_power_5vctrl) &
1053 POWER_5VCTRL_ENABLE_DCDC)) {
1054 if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
1055 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
1065 * mxs_get_vddd_power_source_off() - Get VDDD rail power source
1067 * This function tests if the VDDD rail is supplied by linear regulator
1068 * or by the DC-DC converter. Returns 1 if powered by linear regulator,
1069 * returns 0 if powered by the DC-DC converter.
1071 static int mxs_get_vddd_power_source_off(void)
1075 tmp = readl(&power_regs->hw_power_vdddctrl);
1076 if (tmp & POWER_VDDDCTRL_DISABLE_FET) {
1077 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
1078 POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
1083 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
1084 if (!(readl(&power_regs->hw_power_5vctrl) &
1085 POWER_5VCTRL_ENABLE_DCDC)) {
1090 if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) {
1091 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
1092 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) {
1100 static int mxs_get_vdda_power_source_off(void)
1104 tmp = readl(&power_regs->hw_power_vddactrl);
1105 if (tmp & POWER_VDDACTRL_DISABLE_FET) {
1106 if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
1107 POWER_VDDACTRL_LINREG_OFFSET_0STEPS) {
1112 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
1113 if (!(readl(&power_regs->hw_power_5vctrl) &
1114 POWER_5VCTRL_ENABLE_DCDC)) {
1119 if (!(tmp & POWER_VDDACTRL_ENABLE_LINREG)) {
1120 if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
1121 POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW) {
1129 struct mxs_vddx_cfg {
1133 uint16_t highest_mV;
1134 int (*powered_by_linreg)(void);
1138 uint32_t bo_offset_mask;
1139 uint32_t bo_offset_offset;
1144 #define POWER_REG(n) &((struct mxs_power_regs *)MXS_POWER_BASE)->n
1146 static const struct mxs_vddx_cfg mxs_vddio_cfg = {
1147 .reg = POWER_REG(hw_power_vddioctrl),
1148 #if defined(CONFIG_SOC_MX23)
1155 .powered_by_linreg = mxs_get_vddio_power_source_off,
1156 .trg_mask = POWER_VDDIOCTRL_TRG_MASK,
1157 .bo_irq = POWER_CTRL_VDDIO_BO_IRQ,
1158 .bo_enirq = POWER_CTRL_ENIRQ_VDDIO_BO,
1159 .bo_offset_mask = POWER_VDDIOCTRL_BO_OFFSET_MASK,
1160 .bo_offset_offset = POWER_VDDIOCTRL_BO_OFFSET_OFFSET,
1165 static const struct mxs_vddx_cfg mxs_vddd_cfg = {
1166 .reg = POWER_REG(hw_power_vdddctrl),
1170 .powered_by_linreg = mxs_get_vddd_power_source_off,
1171 .trg_mask = POWER_VDDDCTRL_TRG_MASK,
1172 .bo_irq = POWER_CTRL_VDDD_BO_IRQ,
1173 .bo_enirq = POWER_CTRL_ENIRQ_VDDD_BO,
1174 .bo_offset_mask = POWER_VDDDCTRL_BO_OFFSET_MASK,
1175 .bo_offset_offset = POWER_VDDDCTRL_BO_OFFSET_OFFSET,
1180 static const struct mxs_vddx_cfg mxs_vdda_cfg = {
1181 .reg = POWER_REG(hw_power_vddactrl),
1185 .powered_by_linreg = mxs_get_vdda_power_source_off,
1186 .trg_mask = POWER_VDDACTRL_TRG_MASK,
1187 .bo_irq = POWER_CTRL_VDDA_BO_IRQ,
1188 .bo_enirq = POWER_CTRL_ENIRQ_VDDA_BO,
1189 .bo_offset_mask = POWER_VDDACTRL_BO_OFFSET_MASK,
1190 .bo_offset_offset = POWER_VDDACTRL_BO_OFFSET_OFFSET,
1195 #ifdef CONFIG_SOC_MX23
1196 static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
1197 .reg = POWER_REG(hw_power_vddmemctrl),
1201 .powered_by_linreg = NULL,
1202 .trg_mask = POWER_VDDMEMCTRL_TRG_MASK,
1205 .bo_offset_mask = 0,
1206 .bo_offset_offset = 0,
1211 * mxs_power_set_vddx() - Configure voltage on DC-DC converter rail
1212 * @cfg: Configuration data of the DC-DC converter rail
1213 * @new_target: New target voltage of the DC-DC converter rail
1214 * @new_brownout: New brownout trigger voltage
1216 * This function configures the output voltage on the DC-DC converter rail.
1217 * The rail is selected by the @cfg argument. The new voltage target is
1218 * selected by the @new_target and the voltage is specified in mV. The
1219 * new brownout value is selected by the @new_brownout argument and the
1220 * value is also in mV.
1222 static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
1223 uint32_t new_target, uint32_t bo_offset)
1225 uint32_t cur_target, diff, bo_int = 0;
1226 int powered_by_linreg = 0;
1229 if (new_target < cfg->lowest_mV) {
1230 new_target = cfg->lowest_mV;
1232 if (new_target > cfg->highest_mV) {
1233 new_target = cfg->highest_mV;
1236 if (new_target - bo_offset < cfg->bo_min_mV) {
1237 bo_offset = new_target - cfg->bo_min_mV;
1238 } else if (new_target - bo_offset > cfg->bo_max_mV) {
1239 bo_offset = new_target - cfg->bo_max_mV;
1242 bo_offset = DIV_ROUND_CLOSEST(bo_offset, cfg->step_mV);
1244 cur_target = readl(cfg->reg);
1245 cur_target &= cfg->trg_mask;
1246 cur_target *= cfg->step_mV;
1247 cur_target += cfg->lowest_mV;
1249 adjust_up = new_target > cur_target;
1250 if (cfg->powered_by_linreg)
1251 powered_by_linreg = cfg->powered_by_linreg();
1253 if (adjust_up && cfg->bo_irq) {
1254 if (powered_by_linreg) {
1255 bo_int = readl(&power_regs->hw_power_ctrl);
1256 writel(cfg->bo_enirq, &power_regs->hw_power_ctrl_clr);
1258 setbits_le32(cfg->reg, cfg->bo_offset_mask);
1262 if (abs(new_target - cur_target) > 100) {
1264 diff = cur_target + 100;
1266 diff = cur_target - 100;
1271 diff -= cfg->lowest_mV;
1272 diff /= cfg->step_mV;
1274 clrsetbits_le32(cfg->reg, cfg->trg_mask, diff);
1276 if (powered_by_linreg ||
1277 (readl(&power_regs->hw_power_sts) &
1278 POWER_STS_VDD5V_GT_VDDIO)) {
1281 while (!(readl(&power_regs->hw_power_sts) &
1287 cur_target = readl(cfg->reg);
1288 cur_target &= cfg->trg_mask;
1289 cur_target *= cfg->step_mV;
1290 cur_target += cfg->lowest_mV;
1291 } while (new_target > cur_target);
1294 if (adjust_up && powered_by_linreg) {
1295 writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
1296 if (bo_int & cfg->bo_enirq)
1297 writel(cfg->bo_enirq,
1298 &power_regs->hw_power_ctrl_set);
1301 clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
1302 bo_offset << cfg->bo_offset_offset);
1307 * mxs_setup_batt_detect() - Start the battery voltage measurement logic
1309 * This function starts and configures the LRADC block. This allows the
1310 * power initialization code to measure battery voltage and based on this
1311 * knowledge, decide whether to boot at all, boot from battery or boot
1314 static void mxs_setup_batt_detect(void)
1316 debug("SPL: Starting battery voltage measurement logic\n");
1319 mxs_lradc_enable_batt_measurement();
1324 * mxs_ungate_power() - Ungate the POWER block
1326 * This function ungates clock to the power block. In case the power block
1327 * was still gated at this point, it will not be possible to configure the
1328 * block and therefore the power initialization would fail. This function
1329 * is only needed on i.MX233, on i.MX28 the power block is always ungated.
1331 static void mxs_ungate_power(void)
1333 #ifdef CONFIG_SOC_MX23
1334 writel(POWER_CTRL_CLKGATE, &power_regs->hw_power_ctrl_clr);
1338 #ifdef CONFIG_CONFIG_MACH_MX28EVK
1339 #define auto_restart 1
1341 #define auto_restart 0
1345 * mxs_power_init() - The power block init main function
1347 * This function calls all the power block initialization functions in
1348 * proper sequence to start the power block.
1350 #define VDDX_VAL(v) (v) / 1000, (v) / 100 % 10
1352 void mxs_power_init(void)
1354 debug("SPL: Initialising Power Block\n");
1356 debug("SPL: Initialising Power Block\n");
1360 mxs_power_clock2xtal();
1361 if (mxs_power_set_auto_restart(auto_restart)) {
1362 serial_puts("Inconsistent value in RTC_PERSISTENT0 register; power-on-reset required\n");
1364 mxs_power_set_linreg();
1366 if (!fixed_batt_supply) {
1367 mxs_power_setup_5v_detect();
1368 mxs_setup_batt_detect();
1371 mxs_power_configure_power_source();
1372 mxs_enable_output_rail_protection();
1374 debug("SPL: Setting VDDIO to %uV%u (brownout @ %uv%02u)\n",
1375 VDDX_VAL(VDDIO_VAL), VDDX_VAL(VDDIO_VAL - VDDIO_BO_VAL));
1376 mxs_power_set_vddx(&mxs_vddio_cfg, VDDIO_VAL, VDDIO_BO_VAL);
1377 debug("SPL: Setting VDDD to %uV%u (brownout @ %uv%02u)\n",
1378 VDDX_VAL(VDDD_VAL), VDDX_VAL(VDDD_VAL - VDDD_BO_VAL));
1379 mxs_power_set_vddx(&mxs_vddd_cfg, VDDD_VAL, VDDD_BO_VAL);
1380 debug("SPL: Setting VDDA to %uV%u (brownout @ %uv%02u)\n",
1381 VDDX_VAL(VDDA_VAL), VDDX_VAL(VDDA_VAL - VDDA_BO_VAL));
1382 mxs_power_set_vddx(&mxs_vdda_cfg, VDDA_VAL, VDDA_BO_VAL);
1383 #ifdef CONFIG_SOC_MX23
1384 debug("SPL: Setting VDDMEM to %uV%u (brownout @ %uv%02u)\n",
1385 VDDX_VAL(VDDMEM_VAL), VDDX_VAL(VDDMEM_VAL - VDDMEM_BO_VAL));
1386 mxs_power_set_vddx(&mxs_vddmem_cfg, VDDMEM_VAL, VDDMEM_BO_VAL);
1388 clrbits_le32(&power_regs->hw_power_vddmemctrl,
1389 POWER_VDDMEMCTRL_ENABLE_LINREG);
1391 writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
1392 POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
1393 POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
1394 POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
1395 if (!fixed_batt_supply)
1396 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
1397 &power_regs->hw_power_5vctrl_set);
1400 #ifdef CONFIG_SPL_MXS_PSWITCH_WAIT
1402 * mxs_power_wait_pswitch() - Wait for power switch to be pressed
1404 * This function waits until the power-switch was pressed to start booting
1407 void mxs_power_wait_pswitch(void)
1409 debug("SPL: Waiting for power switch input\n");
1410 while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))