2 * DDR Configuration for AM33xx devices.
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
6 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/cpu.h>
10 #include <asm/arch/ddr_defs.h>
11 #include <asm/arch/sys_proto.h>
16 * Base address for EMIF instances
18 static struct emif_reg_struct *emif_reg[2] = {
19 (struct emif_reg_struct *)EMIF4_0_CFG_BASE,
20 (struct emif_reg_struct *)EMIF4_1_CFG_BASE,
24 * Base addresses for DDR PHY cmd/data regs
26 static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
27 (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
28 (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2,
31 static struct ddr_data_regs *ddr_data_reg[2] = {
32 (struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
33 (struct ddr_data_regs *)DDR_PHY_DATA_ADDR2,
37 * Base address for ddr io control instances
39 static struct ddr_cmdtctrl *ioctrl_reg =
40 (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR;
45 void config_sdram(const struct emif_regs *regs, int nr)
47 if (regs->zq_config) {
49 * A value of 0x2800 for the REF CTRL will give us
50 * about 570us for a delay, which will be long enough
51 * to configure things.
53 writel(0x2800, &emif_reg[nr]->emif_sdram_ref_ctrl);
54 writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
55 writel(regs->sdram_config, &cstat->emif_sdram_config);
56 writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
57 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
58 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
60 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
61 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
62 writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
68 void set_sdram_timings(const struct emif_regs *regs, int nr)
70 writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1);
71 writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw);
72 writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2);
73 writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw);
74 writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3);
75 writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
81 void config_ddr_phy(const struct emif_regs *regs, int nr)
83 writel(regs->emif_ddr_phy_ctlr_1,
84 &emif_reg[nr]->emif_ddr_phy_ctrl_1);
85 writel(regs->emif_ddr_phy_ctlr_1,
86 &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
90 * Configure DDR CMD control registers
92 void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
94 writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
95 writel(cmd->cmd0dldiff, &ddr_cmd_reg[nr]->cm0dldiff);
96 writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
98 writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
99 writel(cmd->cmd1dldiff, &ddr_cmd_reg[nr]->cm1dldiff);
100 writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);
102 writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
103 writel(cmd->cmd2dldiff, &ddr_cmd_reg[nr]->cm2dldiff);
104 writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
108 * Configure DDR DATA registers
110 void config_ddr_data(const struct ddr_data *data, int nr)
114 for (i = 0; i < DDR_DATA_REGS_NR; i++) {
115 writel(data->datardsratio0,
116 &(ddr_data_reg[nr]+i)->dt0rdsratio0);
117 writel(data->datawdsratio0,
118 &(ddr_data_reg[nr]+i)->dt0wdsratio0);
119 writel(data->datawiratio0,
120 &(ddr_data_reg[nr]+i)->dt0wiratio0);
121 writel(data->datagiratio0,
122 &(ddr_data_reg[nr]+i)->dt0giratio0);
123 writel(data->datafwsratio0,
124 &(ddr_data_reg[nr]+i)->dt0fwsratio0);
125 writel(data->datawrsratio0,
126 &(ddr_data_reg[nr]+i)->dt0wrsratio0);
127 writel(data->datauserank0delay,
128 &(ddr_data_reg[nr]+i)->dt0rdelays0);
129 writel(data->datadldiff0,
130 &(ddr_data_reg[nr]+i)->dt0dldiff0);
134 void config_io_ctrl(unsigned long val)
136 writel(val, &ioctrl_reg->cm0ioctl);
137 writel(val, &ioctrl_reg->cm1ioctl);
138 writel(val, &ioctrl_reg->cm2ioctl);
139 writel(val, &ioctrl_reg->dt0ioctl);
140 writel(val, &ioctrl_reg->dt1ioctl);