2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/errno.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sys_proto.h>
17 PLL_ARM, /* PLL1: ARM PLL */
18 PLL_528, /* PLL2: System Bus PLL*/
19 PLL_USBOTG, /* PLL3: OTG USB PLL */
20 PLL_AUDIO, /* PLL4: Audio PLL */
21 PLL_VIDEO, /* PLL5: Video PLL */
22 PLL_ENET, /* PLL6: ENET PLL */
23 PLL_USB2, /* PLL7: USB2 PLL */
24 PLL_MLB, /* PLL8: MLB PLL */
27 struct mxc_ccm_reg *const imx_ccm = (void *)CCM_BASE_ADDR;
28 struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
30 int clk_enable(struct clk *clk)
36 if (clk->usecount == 0) {
37 debug("%s: Enabling %s clock\n", __func__, clk->name);
38 ret = clk->enable(clk);
43 assert(clk->usecount > 0);
47 void clk_disable(struct clk *clk)
52 assert(clk->usecount > 0);
53 if (!(--clk->usecount)) {
55 debug("%s: Disabling %s clock\n", __func__, clk->name);
61 int clk_get_usecount(struct clk *clk)
69 u32 clk_get_rate(struct clk *clk)
77 struct clk *clk_get_parent(struct clk *clk)
85 int clk_set_rate(struct clk *clk, unsigned long rate)
87 if (clk && clk->set_rate)
88 clk->set_rate(clk, rate);
92 long clk_round_rate(struct clk *clk, unsigned long rate)
94 if (clk == NULL || !clk->round_rate)
97 return clk->round_rate(clk, rate);
100 int clk_set_parent(struct clk *clk, struct clk *parent)
102 debug("Setting parent of clk %p to %p (%p)\n", clk, parent,
103 clk ? clk->parent : NULL);
105 if (!clk || clk == parent)
108 if (clk->set_parent) {
111 ret = clk->set_parent(clk, parent);
115 clk->parent = parent;
119 #ifdef CONFIG_MXC_OCOTP
120 void enable_ocotp_clk(unsigned char enable)
124 reg = __raw_readl(&imx_ccm->CCGR2);
126 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
128 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
129 __raw_writel(reg, &imx_ccm->CCGR2);
133 #ifdef CONFIG_NAND_MXS
134 void setup_gpmi_io_clk(u32 cfg)
136 /* Disable clocks per ERR007177 from MX6 errata */
137 clrbits_le32(&imx_ccm->CCGR4,
138 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
139 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
140 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
141 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
142 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
144 clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
146 clrsetbits_le32(&imx_ccm->cs2cdr,
147 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
148 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
149 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
152 setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
153 setbits_le32(&imx_ccm->CCGR4,
154 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
155 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
156 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
157 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
158 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
162 void enable_usboh3_clk(unsigned char enable)
166 reg = __raw_readl(&imx_ccm->CCGR6);
168 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
170 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
171 __raw_writel(reg, &imx_ccm->CCGR6);
175 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_SOC_MX6SX)
176 void enable_enet_clk(unsigned char enable)
178 u32 mask = MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK;
181 setbits_le32(&imx_ccm->CCGR1, mask);
183 clrbits_le32(&imx_ccm->CCGR1, mask);
187 #ifdef CONFIG_MXC_UART
188 void enable_uart_clk(unsigned char enable)
190 u32 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
193 setbits_le32(&imx_ccm->CCGR5, mask);
195 clrbits_le32(&imx_ccm->CCGR5, mask);
200 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
207 mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
209 setbits_le32(&imx_ccm->CCGR6, mask);
211 clrbits_le32(&imx_ccm->CCGR6, mask);
217 #ifdef CONFIG_SYS_I2C_MXC
218 /* i2c_num can be from 0 - 3 */
219 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
228 mask = MXC_CCM_CCGR_CG_MASK
229 << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
231 reg = __raw_readl(&imx_ccm->CCGR2);
236 __raw_writel(reg, &imx_ccm->CCGR2);
238 if (is_cpu_type(MXC_CPU_MX6SX)) {
239 mask = MXC_CCM_CCGR6_I2C4_MASK;
240 addr = &imx_ccm->CCGR6;
242 mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
243 addr = &imx_ccm->CCGR1;
245 reg = __raw_readl(addr);
250 __raw_writel(reg, addr);
256 /* spi_num can be from 0 - SPI_MAX_NUM */
257 int enable_spi_clk(unsigned char enable, unsigned spi_num)
262 if (spi_num > SPI_MAX_NUM)
265 mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
266 reg = __raw_readl(&imx_ccm->CCGR1);
271 __raw_writel(reg, &imx_ccm->CCGR1);
274 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
280 div = __raw_readl(&anatop->pll_arm);
281 if (div & BM_ANADIG_PLL_ARM_BYPASS)
282 /* Assume the bypass clock is always derived from OSC */
284 div &= BM_ANADIG_PLL_ARM_DIV_SELECT;
286 return infreq * div / 2;
288 div = __raw_readl(&anatop->pll_528);
289 if (div & BM_ANADIG_PLL_528_BYPASS)
291 div &= BM_ANADIG_PLL_528_DIV_SELECT;
293 return infreq * (20 + div * 2);
295 div = __raw_readl(&anatop->usb1_pll_480_ctrl);
296 if (div & BM_ANADIG_USB_PLL_480_CTRL_BYPASS)
298 div &= BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT;
300 return infreq * (20 + div * 2);
302 div = __raw_readl(&anatop->pll_audio);
303 if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
305 div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
309 div = __raw_readl(&anatop->pll_video);
310 if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
312 div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
316 div = __raw_readl(&anatop->pll_enet);
317 if (div & BM_ANADIG_PLL_ENET_BYPASS)
319 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
321 return 25000000 * (div + (div >> 1) + 1);
323 div = __raw_readl(&anatop->usb2_pll_480_ctrl);
324 if (div & BM_ANADIG_USB_PLL_480_CTRL_BYPASS)
326 div &= BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT;
328 return infreq * (20 + div * 2);
330 div = __raw_readl(&anatop->pll_mlb);
331 if (div & BM_ANADIG_PLL_MLB_BYPASS)
333 /* unknown external clock provided on MLB_CLK pin */
338 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
342 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
347 /* No PFD3 on PLL2 */
350 div = __raw_readl(&anatop->pfd_528);
351 freq = (u64)decode_pll(PLL_528, MXC_HCLK);
354 div = __raw_readl(&anatop->pfd_480);
355 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
358 /* No PFD on other PLL */
362 return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
363 ANATOP_PFD_FRAC_SHIFT(pfd_num));
366 static u32 get_mcu_main_clk(void)
370 reg = __raw_readl(&imx_ccm->cacrr);
371 reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
372 reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
373 freq = decode_pll(PLL_ARM, MXC_HCLK);
375 return freq / (reg + 1);
378 u32 get_periph_clk(void)
382 reg = __raw_readl(&imx_ccm->cbcdr);
383 if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
384 reg = __raw_readl(&imx_ccm->cbcmr);
385 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
386 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
390 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
398 reg = __raw_readl(&imx_ccm->cbcmr);
399 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
400 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
404 freq = decode_pll(PLL_528, MXC_HCLK);
407 freq = mxc_get_pll_pfd(PLL_528, 2);
410 freq = mxc_get_pll_pfd(PLL_528, 0);
413 /* static / 2 divider */
414 freq = mxc_get_pll_pfd(PLL_528, 2) / 2;
422 static u32 get_ipg_clk(void)
426 reg = __raw_readl(&imx_ccm->cbcdr);
427 reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
428 ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
430 return get_ahb_clk() / (ipg_podf + 1);
433 static u32 get_ipg_per_clk(void)
435 u32 reg, perclk_podf;
437 reg = __raw_readl(&imx_ccm->cscmr1);
438 if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
440 if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
441 return MXC_HCLK; /* OSC 24Mhz */
444 perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
446 return get_ipg_clk() / (perclk_podf + 1);
449 static u32 get_uart_clk(void)
452 u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
453 reg = __raw_readl(&imx_ccm->cscdr1);
455 if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
457 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
461 reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
462 uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
464 return freq / (uart_podf + 1);
467 static u32 get_cspi_clk(void)
471 reg = __raw_readl(&imx_ccm->cscdr2);
472 cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
473 MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
476 if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
477 return MXC_HCLK / (cspi_podf + 1);
480 return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
483 static u32 get_axi_clk(void)
485 u32 root_freq, axi_podf;
486 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
488 axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
489 axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
491 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
492 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
493 root_freq = mxc_get_pll_pfd(PLL_528, 2);
495 root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
497 root_freq = get_periph_clk();
499 return root_freq / (axi_podf + 1);
502 static u32 get_emi_slow_clk(void)
504 u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
506 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
507 emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
508 emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
509 emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
510 emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
512 switch (emi_clk_sel) {
514 root_freq = get_axi_clk();
517 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
520 root_freq = mxc_get_pll_pfd(PLL_528, 2);
523 root_freq = mxc_get_pll_pfd(PLL_528, 0);
527 return root_freq / (emi_slow_podf + 1);
530 static u32 get_nfc_clk(void)
532 u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
533 u32 podf = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK) >> MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
534 u32 pred = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK) >> MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
535 int nfc_clk_sel = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK) >>
536 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
539 switch (nfc_clk_sel) {
541 root_freq = mxc_get_pll_pfd(PLL_528, 0);
544 root_freq = decode_pll(PLL_528, MXC_HCLK);
547 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
550 root_freq = mxc_get_pll_pfd(PLL_528, 2);
554 return root_freq / (pred + 1) / (podf + 1);
557 #define CS2CDR_ENFC_MASK (MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | \
558 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | \
559 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK)
561 static int set_nfc_clk(u32 ref, u32 freq_khz)
563 u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
570 u32 freq = freq_khz * 1000;
572 for (nfc_clk_sel = 0; nfc_clk_sel < 4; nfc_clk_sel++) {
576 if (ref < 4 && ref != nfc_clk_sel)
579 switch (nfc_clk_sel) {
581 root_freq = mxc_get_pll_pfd(PLL_528, 0);
584 root_freq = decode_pll(PLL_528, MXC_HCLK);
587 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
590 root_freq = mxc_get_pll_pfd(PLL_528, 2);
593 if (root_freq < freq)
596 podf = min(DIV_ROUND_UP(root_freq, freq), 1U << 6);
597 pred = min(DIV_ROUND_UP(root_freq / podf, freq), 8U);
598 act_freq = root_freq / pred / podf;
599 err = (freq - act_freq) * 100 / freq;
600 debug("root=%d[%u] freq=%u pred=%u podf=%u act=%u err=%d\n",
601 nfc_clk_sel, root_freq, freq, pred, podf, act_freq, err);
605 nfc_val = (podf - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
606 nfc_val |= (pred - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
607 nfc_val |= nfc_clk_sel << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
614 if (nfc_val == ~0 || min_err > 10)
617 if ((cs2cdr & CS2CDR_ENFC_MASK) != nfc_val) {
618 debug("changing cs2cdr from %08x to %08x\n", cs2cdr,
619 (cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val);
620 __raw_writel((cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val,
623 debug("Leaving cs2cdr unchanged [%08x]\n", cs2cdr);
628 #if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
629 static u32 get_mmdc_ch0_clk(void)
631 u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
632 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
635 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
636 >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
638 switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
639 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
641 freq = decode_pll(PLL_528, MXC_HCLK);
644 freq = mxc_get_pll_pfd(PLL_528, 2);
647 freq = mxc_get_pll_pfd(PLL_528, 0);
650 /* static / 2 divider */
651 freq = mxc_get_pll_pfd(PLL_528, 2) / 2;
654 return freq / (podf + 1);
658 static u32 get_mmdc_ch0_clk(void)
660 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
661 u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
662 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
664 return get_periph_clk() / (mmdc_ch0_podf + 1);
668 #ifdef CONFIG_SOC_MX6SX
669 /* qspi_num can be from 0 - 1 */
670 void enable_qspi_clk(int qspi_num)
673 /* Enable QuadSPI clock */
676 /* disable the clock gate */
677 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
679 /* set 50M : (50 = 396 / 2 / 4) */
680 reg = readl(&imx_ccm->cscmr1);
681 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
682 MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
683 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
684 (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
685 writel(reg, &imx_ccm->cscmr1);
687 /* enable the clock gate */
688 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
692 * disable the clock gate
693 * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
694 * disable both of them.
696 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
697 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
699 /* set 50M : (50 = 396 / 2 / 4) */
700 reg = readl(&imx_ccm->cs2cdr);
701 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
702 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
703 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
704 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
705 MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
706 writel(reg, &imx_ccm->cs2cdr);
708 /*enable the clock gate*/
709 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
710 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
718 #ifdef CONFIG_FEC_MXC
719 int enable_fec_anatop_clock(enum enet_freq freq)
722 s32 timeout = 100000;
724 struct anatop_regs __iomem *anatop =
725 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
727 if (freq < ENET_25MHZ || freq > ENET_125MHZ)
730 reg = readl(&anatop->pll_enet);
731 reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
734 if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
735 (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
736 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
737 writel(reg, &anatop->pll_enet);
739 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
746 /* Enable FEC clock */
747 reg |= BM_ANADIG_PLL_ENET_ENABLE;
748 reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
749 writel(reg, &anatop->pll_enet);
751 #ifdef CONFIG_SOC_MX6SX
753 * Set enet ahb clock to 200MHz
754 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
756 reg = readl(&imx_ccm->chsccdr);
757 reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
758 | MXC_CCM_CHSCCDR_ENET_PODF_MASK
759 | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
761 reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
763 reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
764 reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
765 writel(reg, &imx_ccm->chsccdr);
767 /* Enable enet system clock */
768 reg = readl(&imx_ccm->CCGR3);
769 reg |= MXC_CCM_CCGR3_ENET_MASK;
770 writel(reg, &imx_ccm->CCGR3);
776 static u32 get_usdhc_clk(u32 port)
778 u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
779 u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
780 u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
784 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
785 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
786 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
790 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
791 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
792 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
796 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
797 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
798 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
802 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
803 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
804 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
812 root_freq = mxc_get_pll_pfd(PLL_528, 0);
814 root_freq = mxc_get_pll_pfd(PLL_528, 2);
816 return root_freq / (usdhc_podf + 1);
819 u32 imx_get_uartclk(void)
821 return get_uart_clk();
824 u32 imx_get_fecclk(void)
826 return mxc_get_clock(MXC_IPG_CLK);
829 static int enable_enet_pll(uint32_t en)
832 s32 timeout = 100000;
835 reg = readl(&anatop->pll_enet);
836 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
837 writel(reg, &anatop->pll_enet);
838 reg |= BM_ANADIG_PLL_ENET_ENABLE;
840 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
845 reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
846 writel(reg, &anatop->pll_enet);
848 writel(reg, &anatop->pll_enet);
852 #ifndef CONFIG_SOC_MX6SX
853 static void ungate_sata_clock(void)
855 struct mxc_ccm_reg *const imx_ccm =
856 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
858 /* Enable SATA clock. */
859 setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
863 static void ungate_pcie_clock(void)
865 struct mxc_ccm_reg *const imx_ccm =
866 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
868 /* Enable PCIe clock. */
869 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
872 #ifndef CONFIG_SOC_MX6SX
873 int enable_sata_clock(void)
876 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
879 void disable_sata_clock(void)
881 struct mxc_ccm_reg *const imx_ccm =
882 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
884 clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
888 int enable_pcie_clock(void)
890 struct anatop_regs *anatop_regs =
891 (struct anatop_regs *)ANATOP_BASE_ADDR;
892 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
898 * The register ANATOP_MISC1 is not documented in the Freescale
899 * MX6RM. The register that is mapped in the ANATOP space and
900 * marked as ANATOP_MISC1 is actually documented in the PMU section
901 * of the datasheet as PMU_MISC1.
903 * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
904 * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
905 * for PCI express link that is clocked from the i.MX6.
907 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
908 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
909 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
910 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
911 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
913 if (is_cpu_type(MXC_CPU_MX6SX))
914 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
916 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
918 clrsetbits_le32(&anatop_regs->ana_misc1,
919 ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
920 ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
921 ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
923 /* PCIe reference clock sourced from AXI. */
924 clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
926 /* Party time! Ungate the clock to the PCIe. */
927 #ifndef CONFIG_SOC_MX6SX
932 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
933 BM_ANADIG_PLL_ENET_ENABLE_PCIE);
936 #ifdef CONFIG_SECURE_BOOT
937 void hab_caam_clock_enable(unsigned char enable)
941 /* CG4 ~ CG6, CAAM clocks */
942 reg = __raw_readl(&imx_ccm->CCGR0);
944 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
945 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
946 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
948 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
949 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
950 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
951 __raw_writel(reg, &imx_ccm->CCGR0);
954 reg = __raw_readl(&imx_ccm->CCGR6);
956 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
958 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
959 __raw_writel(reg, &imx_ccm->CCGR6);
963 static void enable_pll3(void)
965 struct anatop_regs __iomem *anatop =
966 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
968 /* make sure pll3 is enabled */
969 if ((readl(&anatop->usb1_pll_480_ctrl) &
970 BM_ANADIG_USB_PLL_480_CTRL_LOCK) == 0) {
971 /* enable pll's power */
972 writel(BM_ANADIG_USB_PLL_480_CTRL_POWER,
973 &anatop->usb1_pll_480_ctrl_set);
974 writel(0x80, &anatop->ana_misc2_clr);
975 /* wait for pll lock */
976 while ((readl(&anatop->usb1_pll_480_ctrl) &
977 BM_ANADIG_USB_PLL_480_CTRL_LOCK) == 0)
980 writel(BM_ANADIG_USB_PLL_480_CTRL_BYPASS,
981 &anatop->usb1_pll_480_ctrl_clr);
982 /* enable pll output */
983 writel(BM_ANADIG_USB_PLL_480_CTRL_ENABLE,
984 &anatop->usb1_pll_480_ctrl_set);
988 void enable_thermal_clk(void)
993 void ipu_clk_enable(void)
995 u32 reg = readl(&imx_ccm->CCGR3);
996 reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
997 writel(reg, &imx_ccm->CCGR3);
1000 void ipu_clk_disable(void)
1002 u32 reg = readl(&imx_ccm->CCGR3);
1003 reg &= ~MXC_CCM_CCGR3_IPU1_IPU_MASK;
1004 writel(reg, &imx_ccm->CCGR3);
1007 void ipu_di_clk_enable(int di)
1011 setbits_le32(&imx_ccm->CCGR3,
1012 MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1015 setbits_le32(&imx_ccm->CCGR3,
1016 MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1019 printf("%s: Invalid DI index %d\n", __func__, di);
1023 void ipu_di_clk_disable(int di)
1027 clrbits_le32(&imx_ccm->CCGR3,
1028 MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1031 clrbits_le32(&imx_ccm->CCGR3,
1032 MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1035 printf("%s: Invalid DI index %d\n", __func__, di);
1039 void ldb_clk_enable(int ldb)
1043 setbits_le32(&imx_ccm->CCGR3,
1044 MXC_CCM_CCGR3_LDB_DI0_MASK);
1047 setbits_le32(&imx_ccm->CCGR3,
1048 MXC_CCM_CCGR3_LDB_DI1_MASK);
1051 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1055 void ldb_clk_disable(int ldb)
1059 clrbits_le32(&imx_ccm->CCGR3,
1060 MXC_CCM_CCGR3_LDB_DI0_MASK);
1063 clrbits_le32(&imx_ccm->CCGR3,
1064 MXC_CCM_CCGR3_LDB_DI1_MASK);
1067 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1071 void ocotp_clk_enable(void)
1073 u32 reg = readl(&imx_ccm->CCGR2);
1074 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
1075 writel(reg, &imx_ccm->CCGR2);
1078 void ocotp_clk_disable(void)
1080 u32 reg = readl(&imx_ccm->CCGR2);
1081 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
1082 writel(reg, &imx_ccm->CCGR2);
1085 unsigned int mxc_get_clock(enum mxc_clock clk)
1089 return get_mcu_main_clk();
1091 return get_periph_clk();
1093 return get_ahb_clk();
1095 return get_ipg_clk();
1096 case MXC_IPG_PERCLK:
1098 return get_ipg_per_clk();
1100 return get_uart_clk();
1102 return get_cspi_clk();
1104 return get_axi_clk();
1105 case MXC_EMI_SLOW_CLK:
1106 return get_emi_slow_clk();
1108 return get_mmdc_ch0_clk();
1110 return get_usdhc_clk(0);
1111 case MXC_ESDHC2_CLK:
1112 return get_usdhc_clk(1);
1113 case MXC_ESDHC3_CLK:
1114 return get_usdhc_clk(2);
1115 case MXC_ESDHC4_CLK:
1116 return get_usdhc_clk(3);
1118 return get_ahb_clk();
1120 return get_nfc_clk();
1122 printf("Unsupported MXC CLK: %d\n", clk);
1128 static inline int gcd(int m, int n)
1142 /* Config CPU clock */
1143 static int set_arm_clk(u32 ref, u32 freq_khz)
1151 if (freq_khz > ref / 1000 * 108 / 2 || freq_khz < ref / 1000 * 54 / 8 / 2) {
1152 printf("Frequency %u.%03uMHz is out of range: %u.%03u..%u.%03u\n",
1153 freq_khz / 1000, freq_khz % 1000,
1154 54 * ref / 1000000 / 8 / 2, 54 * ref / 1000 / 8 / 2 % 1000,
1155 108 * ref / 1000000 / 2, 108 * ref / 1000 / 2 % 1000);
1159 for (d = DIV_ROUND_UP(648000, freq_khz); d <= 8; d++) {
1160 int m = freq_khz * 2 * d / (ref / 1000);
1165 debug("%s@%d: d=%d m=%d\n", __func__, __LINE__,
1170 f = ref * m / d / 2;
1171 if (f > freq_khz * 1000) {
1172 debug("%s@%d: d=%d m=%d f=%u freq=%u\n", __func__, __LINE__,
1176 f = ref * m / d / 2;
1178 err = freq_khz * 1000 - f;
1179 debug("%s@%d: d=%d m=%d f=%u freq=%u err=%d\n", __func__, __LINE__,
1180 d, m, f, freq_khz, err);
1181 if (err < min_err) {
1191 debug("Setting M=%3u D=%2u for %u.%03uMHz (actual: %u.%03uMHz)\n",
1192 mul, div, freq_khz / 1000, freq_khz % 1000,
1193 ref * mul / 2 / div / 1000000, ref * mul / 2 / div / 1000 % 1000);
1195 reg = readl(&anatop->pll_arm);
1196 debug("anadig_pll_arm=%08x -> %08x\n",
1197 reg, (reg & ~0x7f) | mul);
1200 writel(reg, &anatop->pll_arm); /* bypass PLL */
1202 reg = (reg & ~0x7f) | mul;
1203 writel(reg, &anatop->pll_arm);
1205 writel(div - 1, &imx_ccm->cacrr);
1208 writel(reg, &anatop->pll_arm); /* disable PLL bypass */
1214 * This function assumes the expected core clock has to be changed by
1215 * modifying the PLL. This is NOT true always but for most of the times,
1216 * it is. So it assumes the PLL output freq is the same as the expected
1217 * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
1218 * In the latter case, it will try to increase the presc value until
1219 * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
1220 * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
1221 * on the targeted PLL and reference input clock to the PLL. Lastly,
1222 * it sets the register based on these values along with the dividers.
1223 * Note 1) There is no value checking for the passed-in divider values
1224 * so the caller has to make sure those values are sensible.
1225 * 2) Also adjust the NFC divider such that the NFC clock doesn't
1226 * exceed NFC_CLK_MAX.
1227 * 3) IPU HSP clock is independent of AHB clock. Even it can go up to
1228 * 177MHz for higher voltage, this function fixes the max to 133MHz.
1229 * 4) This function should not have allowed diag_printf() calls since
1230 * the serial driver has been stoped. But leave then here to allow
1231 * easy debugging by NOT calling the cyg_hal_plf_serial_stop().
1233 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
1241 ret = set_arm_clk(ref, freq);
1245 ret = set_nfc_clk(ref, freq);
1249 printf("Warning: Unsupported or invalid clock type: %d\n",
1258 * Dump some core clocks.
1260 #define print_pll(pll) { \
1261 u32 __pll = decode_pll(pll, MXC_HCLK); \
1262 printf("%-12s %4d.%03d MHz\n", #pll, \
1263 __pll / 1000000, __pll / 1000 % 1000); \
1266 #define MXC_IPG_PER_CLK MXC_IPG_PERCLK
1268 #define print_clk(clk) { \
1269 u32 __clk = mxc_get_clock(MXC_##clk##_CLK); \
1270 printf("%-12s %4d.%03d MHz\n", #clk, \
1271 __clk / 1000000, __clk / 1000 % 1000); \
1274 #define print_pfd(pll, pfd) { \
1275 u32 __pfd = readl(&anatop->pfd_##pll); \
1276 if (__pfd & (0x80 << 8 * pfd)) { \
1277 printf("PFD_%s[%d] OFF\n", #pll, pfd); \
1279 __pfd = (__pfd >> 8 * pfd) & 0x3f; \
1280 printf("PFD_%s[%d] %4d.%03d MHz\n", #pll, pfd, \
1282 pll * 18 * 1000 / __pfd % 1000); \
1286 static void do_mx6_showclocks(void)
1290 print_pll(PLL_USBOTG);
1291 print_pll(PLL_AUDIO);
1292 print_pll(PLL_VIDEO);
1293 print_pll(PLL_ENET);
1294 print_pll(PLL_USB2);
1316 print_clk(EMI_SLOW);
1322 static struct clk_lookup {
1325 } mx6_clk_lookup[] = {
1326 { "arm", MXC_ARM_CLK, },
1327 { "nfc", MXC_NFC_CLK, },
1330 int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1334 unsigned long ref = ~0UL;
1337 do_mx6_showclocks();
1338 return CMD_RET_SUCCESS;
1339 } else if (argc == 2 || argc > 4) {
1340 return CMD_RET_USAGE;
1343 freq = simple_strtoul(argv[2], NULL, 0);
1345 printf("Invalid clock frequency %lu\n", freq);
1346 return CMD_RET_FAILURE;
1349 ref = simple_strtoul(argv[3], NULL, 0);
1351 for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1352 if (strcasecmp(argv[1], mx6_clk_lookup[i].name) == 0) {
1353 switch (mx6_clk_lookup[i].index) {
1356 return CMD_RET_USAGE;
1361 if (argc > 3 && ref > 3) {
1362 printf("Invalid clock selector value: %lu\n", ref);
1363 return CMD_RET_FAILURE;
1367 printf("Setting %s clock to %lu MHz\n",
1368 mx6_clk_lookup[i].name, freq);
1369 if (mxc_set_clock(ref, freq, mx6_clk_lookup[i].index))
1371 freq = mxc_get_clock(mx6_clk_lookup[i].index);
1372 printf("%s clock set to %lu.%03lu MHz\n",
1373 mx6_clk_lookup[i].name,
1374 freq / 1000000, freq / 1000 % 1000);
1375 return CMD_RET_SUCCESS;
1378 if (i == ARRAY_SIZE(mx6_clk_lookup)) {
1379 printf("clock %s not found; supported clocks are:\n", argv[1]);
1380 for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1381 printf("\t%s\n", mx6_clk_lookup[i].name);
1384 printf("Failed to set clock %s to %s MHz\n",
1387 return CMD_RET_FAILURE;
1390 #ifndef CONFIG_SOC_MX6SX
1391 void enable_ipu_clock(void)
1393 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1395 reg = readl(&mxc_ccm->CCGR3);
1396 reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1397 writel(reg, &mxc_ccm->CCGR3);
1400 setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
1401 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
1405 /***************************************************/
1408 clocks, 4, 0, do_clocks,
1409 "display/set clocks",
1410 " - display clock settings\n"
1411 "clocks <clkname> <freq> - set clock <clkname> to <freq> MHz"