2 * Copyright (C) 2014 Gateworks Corporation
3 * Author: Tim Harvey <tharvey@gateworks.com>
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <linux/types.h>
10 #include <asm/arch/mx6-ddr.h>
11 #include <asm/arch/sys_proto.h>
13 #include <asm/types.h>
15 #if defined(CONFIG_SOC_MX6SX)
16 /* Configure MX6SX mmdc iomux */
17 void mx6sx_dram_iocfg(unsigned width,
18 const struct mx6sx_iomux_ddr_regs *ddr,
19 const struct mx6sx_iomux_grp_regs *grp)
21 struct mx6sx_iomux_ddr_regs *mx6_ddr_iomux;
22 struct mx6sx_iomux_grp_regs *mx6_grp_iomux;
24 mx6_ddr_iomux = (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
25 mx6_grp_iomux = (struct mx6sx_iomux_grp_regs *)MX6SX_IOM_GRP_BASE;
28 writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
29 writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
32 writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
35 writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
36 writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
37 writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
40 writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
41 writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
42 writel(ddr->dram_sdcke0, &mx6_ddr_iomux->dram_sdcke0);
43 writel(ddr->dram_sdcke1, &mx6_ddr_iomux->dram_sdcke1);
44 writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
45 writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
46 writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
49 writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
50 writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
51 writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
53 writel(ddr->dram_sdqs2, &mx6_ddr_iomux->dram_sdqs2);
54 writel(ddr->dram_sdqs3, &mx6_ddr_iomux->dram_sdqs3);
58 writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
59 writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
60 writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
62 writel(grp->grp_b2ds, &mx6_grp_iomux->grp_b2ds);
63 writel(grp->grp_b3ds, &mx6_grp_iomux->grp_b3ds);
65 writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
66 writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
68 writel(ddr->dram_dqm2, &mx6_ddr_iomux->dram_dqm2);
69 writel(ddr->dram_dqm3, &mx6_ddr_iomux->dram_dqm3);
74 #ifdef CONFIG_SOC_MX6UL
75 void mx6ul_dram_iocfg(unsigned width,
76 const struct mx6ul_iomux_ddr_regs *ddr,
77 const struct mx6ul_iomux_grp_regs *grp)
79 struct mx6ul_iomux_ddr_regs *mx6_ddr_iomux;
80 struct mx6ul_iomux_grp_regs *mx6_grp_iomux;
82 mx6_ddr_iomux = (struct mx6ul_iomux_ddr_regs *)MX6UL_IOM_DDR_BASE;
83 mx6_grp_iomux = (struct mx6ul_iomux_grp_regs *)MX6UL_IOM_GRP_BASE;
86 writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
87 writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
90 writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
93 writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
94 writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
95 writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
98 writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
99 writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
100 writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
101 writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
102 writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
105 writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
106 writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
107 writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
110 writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
111 writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
112 writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
113 writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
114 writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
118 #if defined(CONFIG_SOC_MX6QDL) || defined(CONFIG_SOC_MX6Q) || defined(CONFIG_SOC_MX6D)
119 /* Configure MX6DQ mmdc iomux */
120 void mx6dq_dram_iocfg(unsigned width,
121 const struct mx6dq_iomux_ddr_regs *ddr,
122 const struct mx6dq_iomux_grp_regs *grp)
124 volatile struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux;
125 volatile struct mx6dq_iomux_grp_regs *mx6_grp_iomux;
127 mx6_ddr_iomux = (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
128 mx6_grp_iomux = (struct mx6dq_iomux_grp_regs *)MX6DQ_IOM_GRP_BASE;
131 mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
132 mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
135 mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
136 mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
139 mx6_ddr_iomux->dram_cas = ddr->dram_cas;
140 mx6_ddr_iomux->dram_ras = ddr->dram_ras;
141 mx6_grp_iomux->grp_addds = grp->grp_addds;
144 mx6_ddr_iomux->dram_reset = ddr->dram_reset;
145 mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
146 mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
147 mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
148 mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
149 mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
150 mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
153 mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
154 mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
155 mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
157 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
158 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
161 mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
162 mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
163 mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
164 mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
168 mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
169 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
170 mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
172 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
173 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
176 mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
177 mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
178 mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
179 mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
181 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
182 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
184 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
185 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
188 mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
189 mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
190 mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
191 mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
196 #if defined(CONFIG_SOC_MX6QDL) || defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
197 /* Configure MX6SDL mmdc iomux */
198 void mx6sdl_dram_iocfg(unsigned width,
199 const struct mx6sdl_iomux_ddr_regs *ddr,
200 const struct mx6sdl_iomux_grp_regs *grp)
202 volatile struct mx6sdl_iomux_ddr_regs *mx6_ddr_iomux;
203 volatile struct mx6sdl_iomux_grp_regs *mx6_grp_iomux;
205 mx6_ddr_iomux = (struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE;
206 mx6_grp_iomux = (struct mx6sdl_iomux_grp_regs *)MX6SDL_IOM_GRP_BASE;
209 mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
210 mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
213 mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
214 mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
217 mx6_ddr_iomux->dram_cas = ddr->dram_cas;
218 mx6_ddr_iomux->dram_ras = ddr->dram_ras;
219 mx6_grp_iomux->grp_addds = grp->grp_addds;
222 mx6_ddr_iomux->dram_reset = ddr->dram_reset;
223 mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
224 mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
225 mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
226 mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
227 mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
228 mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
231 mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
232 mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
233 mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
235 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
236 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
239 mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
240 mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
241 mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
242 mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
246 mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
247 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
248 mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
250 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
251 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
254 mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
255 mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
256 mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
257 mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
259 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
260 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
262 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
263 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
266 mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
267 mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
268 mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
269 mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
275 * Configure mx6 mmdc registers based on:
276 * - board-specific memory configuration
277 * - board-specific calibration data
278 * - ddr3 chip details
280 * The various calculations here are derived from the Freescale
281 * i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate MMDC
282 * configuration registers based on memory system and memory chip parameters.
284 * The defaults here are those which were specified in the spreadsheet.
285 * For details on each register, refer to the IMX6DQRM and/or IMX6SDLRM
286 * section titled MMDC initialization
288 #define MR(val, ba, cmd, cs1) \
289 ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
290 #define MMDC1(entry, value) do { \
291 if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL)) \
292 mmdc1->entry = value; \
295 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
296 const struct mx6_mmdc_calibration *calib,
297 const struct mx6_ddr3_cfg *ddr3_cfg)
299 volatile struct mmdc_p_regs *mmdc0;
300 volatile struct mmdc_p_regs *mmdc1;
302 u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
303 u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
304 u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
305 u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
307 u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
309 int clkper; /* clock period in picoseconds */
310 int clock; /* clock freq in MHz */
312 u16 mem_speed = ddr3_cfg->mem_speed;
314 mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
315 if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL))
316 mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
318 /* Limit mem_speed for MX6D/MX6Q */
319 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
320 if (mem_speed > 1066)
321 mem_speed = 1066; /* 1066 MT/s */
325 /* Limit mem_speed for MX6S/MX6DL */
328 mem_speed = 800; /* 800 MT/s */
333 clock = mem_speed / 2;
335 * Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but MX6D/Q supports
336 * up to 528 MHz, so reduce the clock to fit chip specs
338 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
340 clock = 528; /* 528 MHz */
343 clkper = (1000 * 1000) / clock; /* pico seconds */
348 switch (ddr3_cfg->density) {
349 case 1: /* 1Gb per chip */
350 trfc = DIV_ROUND_UP(110000, clkper) - 1;
351 txs = DIV_ROUND_UP(120000, clkper) - 1;
353 case 2: /* 2Gb per chip */
354 trfc = DIV_ROUND_UP(160000, clkper) - 1;
355 txs = DIV_ROUND_UP(170000, clkper) - 1;
357 case 4: /* 4Gb per chip */
358 trfc = DIV_ROUND_UP(260000, clkper) - 1;
359 txs = DIV_ROUND_UP(270000, clkper) - 1;
361 case 8: /* 8Gb per chip */
362 trfc = DIV_ROUND_UP(350000, clkper) - 1;
363 txs = DIV_ROUND_UP(360000, clkper) - 1;
366 /* invalid density */
367 puts("invalid chip density\n");
375 txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
376 tcke = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
377 if (ddr3_cfg->pagesz == 1) {
378 tfaw = DIV_ROUND_UP(40000, clkper) - 1;
379 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
381 tfaw = DIV_ROUND_UP(50000, clkper) - 1;
382 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
386 txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
387 tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1;
388 if (ddr3_cfg->pagesz == 1) {
389 tfaw = DIV_ROUND_UP(37500, clkper) - 1;
390 trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
392 tfaw = DIV_ROUND_UP(50000, clkper) - 1;
393 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
397 puts("invalid memory speed\n");
401 txpdll = DIV_ROUND_UP(max(10 * clkper, 24000), clkper) - 1;
402 tcksre = DIV_ROUND_UP(max(5 * clkper, 10000), clkper);
403 taonpd = DIV_ROUND_UP(2000, clkper) - 1;
406 twr = DIV_ROUND_UP(15000, clkper) - 1;
407 tmrd = DIV_ROUND_UP(max(12 * clkper, 15000), clkper) - 1;
408 trc = DIV_ROUND_UP(ddr3_cfg->trcmin, clkper / 10) - 1;
409 tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1;
410 tcl = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3;
411 trp = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1;
412 twtr = ROUND(max(4 * clkper, 7500) / clkper, 1) - 1;
415 cs0_end = 4 * sysinfo->cs_density - 1;
417 debug("density:%d Gb (%d Gb per chip)\n",
418 sysinfo->cs_density, ddr3_cfg->density);
419 debug("clock: %dMHz (%d ps)\n", clock, clkper);
420 debug("memspd:%d\n", mem_speed);
421 debug("tcke=%d\n", tcke);
422 debug("tcksrx=%d\n", tcksrx);
423 debug("tcksre=%d\n", tcksre);
424 debug("taofpd=%d\n", taofpd);
425 debug("taonpd=%d\n", taonpd);
426 debug("todtlon=%d\n", todtlon);
427 debug("tanpd=%d\n", tanpd);
428 debug("taxpd=%d\n", taxpd);
429 debug("trfc=%d\n", trfc);
430 debug("txs=%d\n", txs);
431 debug("txp=%d\n", txp);
432 debug("txpdll=%d\n", txpdll);
433 debug("tfaw=%d\n", tfaw);
434 debug("tcl=%d\n", tcl);
435 debug("trcd=%d\n", trcd);
436 debug("trp=%d\n", trp);
437 debug("trc=%d\n", trc);
438 debug("tras=%d\n", tras);
439 debug("twr=%d\n", twr);
440 debug("tmrd=%d\n", tmrd);
441 debug("tcwl=%d\n", tcwl);
442 debug("tdllk=%d\n", tdllk);
443 debug("trtp=%d\n", trtp);
444 debug("twtr=%d\n", twtr);
445 debug("trrd=%d\n", trrd);
446 debug("txpr=%d\n", txpr);
447 debug("cs0_end=%d\n", cs0_end);
448 debug("ncs=%d\n", sysinfo->ncs);
449 debug("Rtt_wr=%d\n", sysinfo->rtt_wr);
450 debug("Rtt_nom=%d\n", sysinfo->rtt_nom);
451 debug("SRT=%d\n", ddr3_cfg->SRT);
452 debug("tcl=%d\n", tcl);
453 debug("twr=%d\n", twr);
456 * board-specific configuration:
457 * These values are determined empirically and vary per board layout
459 * appnote, ddr3 spreadsheet
461 mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
462 mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
463 mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
464 mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
465 mmdc0->mprddlctl = calib->p0_mprddlctl;
466 mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
467 if (sysinfo->dsize > 1) {
468 MMDC1(mpwldectrl0, calib->p1_mpwldectrl0);
469 MMDC1(mpwldectrl1, calib->p1_mpwldectrl1);
470 MMDC1(mpdgctrl0, calib->p1_mpdgctrl0);
471 MMDC1(mpdgctrl1, calib->p1_mpdgctrl1);
472 MMDC1(mprddlctl, calib->p1_mprddlctl);
473 MMDC1(mpwrdlctl, calib->p1_mpwrdlctl);
476 /* Read data DQ Byte0-3 delay */
477 mmdc0->mprddqby0dl = 0x33333333;
478 mmdc0->mprddqby1dl = 0x33333333;
479 if (sysinfo->dsize > 0) {
480 mmdc0->mprddqby2dl = 0x33333333;
481 mmdc0->mprddqby3dl = 0x33333333;
484 if (sysinfo->dsize > 1) {
485 MMDC1(mprddqby0dl, 0x33333333);
486 MMDC1(mprddqby1dl, 0x33333333);
487 MMDC1(mprddqby2dl, 0x33333333);
488 MMDC1(mprddqby3dl, 0x33333333);
491 /* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
492 val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227;
493 mmdc0->mpodtctrl = val;
494 if (sysinfo->dsize > 1)
495 MMDC1(mpodtctrl, val);
497 /* complete calibration */
498 val = (1 << 11); /* Force measurement on delay-lines */
500 if (sysinfo->dsize > 1)
503 /* Step 1: configuration request */
504 mmdc0->mdscr = (u32)(1 << 15); /* config request */
506 /* Step 2: Timing configuration */
507 mmdc0->mdcfg0 = (trfc << 24) | (txs << 16) | (txp << 13) |
508 (txpdll << 9) | (tfaw << 4) | tcl;
509 mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) |
510 (tras << 16) | (1 << 15) /* trpa */ |
511 (twr << 9) | (tmrd << 5) | tcwl;
512 mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
513 mmdc0->mdotc = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) |
514 (taxpd << 16) | (todtlon << 12) | (todt_idle_off << 4);
515 mmdc0->mdasp = cs0_end; /* CS addressing */
517 /* Step 3: Configure DDR type */
518 mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
519 (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
520 (sysinfo->ralat << 6);
522 /* Step 4: Configure delay while leaving reset */
523 mmdc0->mdor = (txpr << 16) | (sysinfo->sde_to_rst << 8) |
524 (sysinfo->rst_to_cke << 0);
526 /* Step 5: Configure DDR physical parameters (density and burst len) */
527 coladdr = ddr3_cfg->coladdr;
528 if (ddr3_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
530 else if (ddr3_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
532 mmdc0->mdctl = (ddr3_cfg->rowaddr - 11) << 24 | /* ROW */
533 (coladdr - 9) << 20 | /* COL */
534 (1 << 19) | /* Burst Length = 8 for DDR3 */
535 (sysinfo->dsize << 16); /* DDR data bus size */
537 /* Step 6: Perform ZQ calibration */
538 val = 0xa1390001; /* one-time HW ZQ calib */
539 mmdc0->mpzqhwctrl = val;
540 if (sysinfo->dsize > 1)
541 MMDC1(mpzqhwctrl, val);
543 /* Step 7: Enable MMDC with desired chip select */
544 mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
545 ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
547 /* Step 8: Write Mode Registers to Init DDR3 devices */
548 for (cs = 0; cs < sysinfo->ncs; cs++) {
550 val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 |
551 ((tcwl - 3) & 3) << 3;
552 debug("MR2 CS%d: 0x%08x\n", cs, (u32)MR(val, 2, 3, cs));
553 mmdc0->mdscr = MR(val, 2, 3, cs);
555 debug("MR3 CS%d: 0x%08x\n", cs, (u32)MR(0, 3, 3, cs));
556 mmdc0->mdscr = MR(0, 3, 3, cs);
558 val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 |
559 ((sysinfo->rtt_nom & 2) ? 1 : 0) << 6;
560 debug("MR1 CS%d: 0x%08x\n", cs, (u32)MR(val, 1, 3, cs));
561 mmdc0->mdscr = MR(val, 1, 3, cs);
563 val = ((tcl - 1) << 4) | /* CAS */
564 (1 << 8) | /* DLL Reset */
565 ((twr - 3) << 9) | /* Write Recovery */
566 (sysinfo->pd_fast_exit << 12); /* Precharge PD PLL on */
567 debug("MR0 CS%d: 0x%08x\n", cs, (u32)MR(val, 0, 3, cs));
568 mmdc0->mdscr = MR(val, 0, 3, cs);
571 mmdc0->mdscr = MR(val, 0, 4, cs);
574 /* Step 10: Power down control and self-refresh */
575 mmdc0->mdpdc = (tcke & 0x7) << 16 |
576 5 << 12 | /* PWDT_1: 256 cycles */
577 5 << 8 | /* PWDT_0: 256 cycles */
578 1 << 6 | /* BOTH_CS_PD */
579 (tcksrx & 0x7) << 3 |
581 if (!sysinfo->pd_fast_exit)
582 mmdc0->mdpdc |= (1 << 7); /* SLOW_PD */
583 mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
585 /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
587 mmdc0->mpzqhwctrl = val;
588 if (sysinfo->dsize > 1)
589 MMDC1(mpzqhwctrl, val);
591 /* Step 12: Configure and activate periodic refresh */
592 mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */
593 (7 << 11); /* REFR: Refresh Rate - 8 refreshes */
595 /* Step 13: Deassert config request - init complete */
596 mmdc0->mdscr = 0x00000000;
598 /* wait for auto-ZQ calibration to complete */