3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
15 #include <imx_thermal.h>
16 #include <asm/armv7.h>
17 #include <asm/bootm.h>
18 #include <asm/pl310.h>
19 #include <asm/errno.h>
21 #include <asm/arch/imx-regs.h>
22 #include <asm/arch/crm_regs.h>
23 #include <asm/arch/regs-ocotp.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/mxc_hdmi.h>
26 #include <asm/arch/sys_proto.h>
27 #include <asm/imx-common/boot_mode.h>
28 #include <asm/imx-common/dma.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 #define __data __attribute__((section(".data")))
34 #ifdef CONFIG_MX6_TEMPERATURE_MIN
35 #define TEMPERATURE_MIN CONFIG_MX6_TEMPERATURE_MIN
37 #define TEMPERATURE_MIN (-40)
39 #ifdef CONFIG_MX6_TEMPERATURE_HOT
40 #define TEMPERATURE_HOT CONFIG_MX6_TEMPERATURE_HOT
42 #define TEMPERATURE_HOT 80
44 #ifdef CONFIG_MX6_TEMPERATURE_MAX
45 #define TEMPERATURE_MAX CONFIG_MX6_TEMPERATURE_MAX
47 #define TEMPERATURE_MAX 125
49 #define TEMP_AVG_COUNT 5
50 #define TEMP_WARN_THRESHOLD 5
66 #if defined(CONFIG_IMX6_THERMAL)
67 static const struct imx_thermal_plat imx6_thermal_plat = {
68 .regs = (void *)ANATOP_BASE_ADDR,
73 U_BOOT_DEVICE(imx6_thermal) = {
74 .name = "imx_thermal",
75 .platdata = &imx6_thermal_plat,
81 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
82 return readl(&scu->config) & 3;
87 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
88 u32 reg = readl(&anatop->digprog_sololite);
89 u32 type = ((reg >> 16) & 0xff);
91 if (type != MXC_CPU_MX6SL) {
92 reg = readl(&anatop->digprog);
93 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
94 u32 cfg = readl(&scu->config) & 3;
95 type = ((reg >> 16) & 0xff);
96 if (type == MXC_CPU_MX6DL) {
98 type = MXC_CPU_MX6SOLO;
101 if (type == MXC_CPU_MX6Q) {
107 reg &= 0xff; /* mx6 silicon revision */
108 return (type << 12) | (reg + 0x10);
111 #ifdef CONFIG_REVISION_TAG
112 u32 __weak get_board_rev(void)
114 u32 cpurev = get_cpu_rev();
115 u32 type = ((cpurev >> 12) & 0xff);
116 if (type == MXC_CPU_MX6SOLO)
117 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
119 if (type == MXC_CPU_MX6D)
120 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
128 struct aipstz_regs *aips1, *aips2;
129 #ifdef CONFIG_SOC_MX6SX
130 struct aipstz_regs *aips3;
133 aips1 = (struct aipstz_regs *)AIPS1_ARB_BASE_ADDR;
134 aips2 = (struct aipstz_regs *)AIPS2_ARB_BASE_ADDR;
135 #ifdef CONFIG_SOC_MX6SX
136 aips3 = (struct aipstz_regs *)AIPS3_ARB_BASE_ADDR;
140 * Set all MPROTx to be non-bufferable, trusted for R/W,
141 * not forced to user-mode.
143 writel(0x77777777, &aips1->mprot0);
144 writel(0x77777777, &aips1->mprot1);
145 writel(0x77777777, &aips2->mprot0);
146 writel(0x77777777, &aips2->mprot1);
149 * Set all OPACRx to be non-bufferable, not require
150 * supervisor privilege level for access,allow for
151 * write access and untrusted master access.
153 writel(0x00000000, &aips1->opacr0);
154 writel(0x00000000, &aips1->opacr1);
155 writel(0x00000000, &aips1->opacr2);
156 writel(0x00000000, &aips1->opacr3);
157 writel(0x00000000, &aips1->opacr4);
158 writel(0x00000000, &aips2->opacr0);
159 writel(0x00000000, &aips2->opacr1);
160 writel(0x00000000, &aips2->opacr2);
161 writel(0x00000000, &aips2->opacr3);
162 writel(0x00000000, &aips2->opacr4);
164 #ifdef CONFIG_SOC_MX6SX
166 * Set all MPROTx to be non-bufferable, trusted for R/W,
167 * not forced to user-mode.
169 writel(0x77777777, &aips3->mprot0);
170 writel(0x77777777, &aips3->mprot1);
173 * Set all OPACRx to be non-bufferable, not require
174 * supervisor privilege level for access,allow for
175 * write access and untrusted master access.
177 writel(0x00000000, &aips3->opacr0);
178 writel(0x00000000, &aips3->opacr1);
179 writel(0x00000000, &aips3->opacr2);
180 writel(0x00000000, &aips3->opacr3);
181 writel(0x00000000, &aips3->opacr4);
185 static void clear_ldo_ramp(void)
187 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
190 /* ROM may modify LDO ramp up time according to fuse setting, so in
191 * order to be in the safe side we neeed to reset these settings to
192 * match the reset value: 0'b00
194 reg = readl(&anatop->ana_misc2);
195 reg &= ~(0x3f << 24);
196 writel(reg, &anatop->ana_misc2);
200 * Set the PMU_REG_CORE register
202 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
203 * Possible values are from 0.725V to 1.450V in steps of
206 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
208 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
209 u32 val, step, old, reg = readl(&anatop->reg_core);
213 val = 0x00; /* Power gated off */
215 val = 0x1F; /* Power FET switched full on. No regulation */
217 val = (mv - 700) / 25;
235 old = (reg & (0x1F << shift)) >> shift;
236 step = abs(val - old);
240 reg = (reg & ~(0x1F << shift)) | (val << shift);
241 writel(reg, &anatop->reg_core);
244 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
252 static u32 __data thermal_calib;
254 #define FACTOR0 10000000
255 #define FACTOR1 15976
256 #define FACTOR2 4297157
258 int raw_to_celsius(unsigned int raw, unsigned int raw_25c, unsigned int raw_hot,
259 unsigned int hot_temp)
263 if (raw_hot != 0 && hot_temp != 0) {
264 unsigned int raw_n40c, ratio;
266 ratio = ((raw_25c - raw_hot) * 100) / (hot_temp - 25);
267 raw_n40c = raw_25c + (13 * ratio) / 20;
269 temperature = (raw_n40c - raw) * 100 / ratio - 40;
271 temperature = TEMPERATURE_MIN;
273 u64 temp64 = FACTOR0;
276 * Derived from linear interpolation:
277 * slope = 0.4297157 - (0.0015976 * 25C fuse)
278 * slope = (FACTOR2 - FACTOR1 * n1) / FACTOR0
279 * (Nmeas - n1) / (Tmeas - t1) = slope
280 * We want to reduce this down to the minimum computation necessary
281 * for each temperature read. Also, we want Tmeas in millicelsius
282 * and we don't want to lose precision from integer division. So...
283 * Tmeas = (Nmeas - n1) / slope + t1
284 * milli_Tmeas = 1000 * (Nmeas - n1) / slope + 1000 * t1
285 * milli_Tmeas = -1000 * (n1 - Nmeas) / slope + 1000 * t1
286 * Let constant c1 = (-1000 / slope)
287 * milli_Tmeas = (n1 - Nmeas) * c1 + 1000 * t1
288 * Let constant c2 = n1 *c1 + 1000 * t1
289 * milli_Tmeas = c2 - Nmeas * c1
292 do_div(temp64, FACTOR1 * raw_25c - FACTOR2);
294 c2 = raw_25c * c1 + 1000 * 25;
295 temperature = (c2 - raw * c1) / 1000;
300 int read_cpu_temperature(void)
302 unsigned int reg, tmp, i;
303 unsigned int raw_25c, raw_hot, hot_temp;
305 struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
306 struct mx6_ocotp_regs *const ocotp_regs = (void *)OCOTP_BASE_ADDR;
308 if (!thermal_calib) {
310 writel(1, &ocotp_regs->hw_ocotp_read_ctrl);
311 thermal_calib = readl(&ocotp_regs->hw_ocotp_ana1);
312 writel(0, &ocotp_regs->hw_ocotp_read_ctrl);
316 if (thermal_calib == 0 || thermal_calib == 0xffffffff)
317 return TEMPERATURE_MIN;
320 * [31:20] sensor value @ 25C
321 * [19:8] sensor value of hot
322 * [7:0] hot temperature value */
323 raw_25c = thermal_calib >> 20;
324 raw_hot = (thermal_calib & 0xfff00) >> 8;
325 hot_temp = thermal_calib & 0xff;
327 /* now we only using single measure, every time we measure
328 * the temperature, we will power on/off the anadig module
330 writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_clr);
331 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
333 /* write measure freq */
334 writel(327, &anatop->tempsense1);
335 writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_clr);
336 writel(BM_ANADIG_TEMPSENSE0_FINISHED, &anatop->tempsense0_clr);
337 writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_set);
339 /* average the temperature value over multiple readings */
340 for (i = 0; i < TEMP_AVG_COUNT; i++) {
344 while ((readl(&anatop->tempsense0) &
345 BM_ANADIG_TEMPSENSE0_FINISHED) == 0) {
350 if ((readl(&anatop->tempsense0) &
351 BM_ANADIG_TEMPSENSE0_FINISHED) == 0) {
353 printf("Failed to read temp sensor\n");
359 reg = (readl(&anatop->tempsense0) &
360 BM_ANADIG_TEMPSENSE0_TEMP_VALUE) >>
361 BP_ANADIG_TEMPSENSE0_TEMP_VALUE;
365 tmp = (tmp * i + reg) / (i + 1);
366 writel(BM_ANADIG_TEMPSENSE0_FINISHED,
367 &anatop->tempsense0_clr);
370 temperature = raw_to_celsius(tmp, raw_25c, raw_hot, hot_temp);
372 /* power down anatop thermal sensor */
373 writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_set);
374 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_clr);
379 int check_cpu_temperature(int boot)
381 static int __data max_temp;
382 int boot_limit = getenv_ulong("max_boot_temp", 10, TEMPERATURE_HOT);
383 int tmp = read_cpu_temperature();
386 if (tmp < TEMPERATURE_MIN || tmp > TEMPERATURE_MAX) {
387 printf("Temperature: can't get valid data!\n");
392 if (tmp > boot_limit) {
393 printf("CPU is %d C, too hot, resetting...\n", tmp);
397 if (tmp > max_temp) {
398 if (tmp > boot_limit - TEMP_WARN_THRESHOLD)
399 printf("WARNING: CPU temperature %d C\n", tmp);
403 printf("Temperature: %d C, calibration data 0x%x\n",
405 while (tmp >= boot_limit) {
407 printf("CPU is %d C, too hot to boot, waiting...\n",
414 tmp = read_cpu_temperature();
415 if (tmp > boot_limit - TEMP_WARN_THRESHOLD && tmp != max_temp)
416 printf("WARNING: CPU temperature %d C\n", tmp);
423 static void imx_set_wdog_powerdown(bool enable)
425 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
426 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
429 struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
430 writew(enable, &wdog3->wmcr);
433 /* Write to the PDE (Power Down Enable) bit */
434 writew(enable, &wdog1->wmcr);
435 writew(enable, &wdog2->wmcr);
438 static void set_ahb_rate(u32 val)
440 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
443 div = get_periph_clk() / val - 1;
444 reg = readl(&mxc_ccm->cbcdr);
446 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
447 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
450 static void clear_mmdc_ch_mask(void)
452 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
454 /* Clear MMDC channel mask */
455 writel(0, &mxc_ccm->ccdr);
458 static void init_bandgap(void)
460 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
462 * Ensure the bandgap has stabilized.
464 while (!(readl(&anatop->ana_misc0) & 0x80))
467 * For best noise performance of the analog blocks using the
468 * outputs of the bandgap, the reftop_selfbiasoff bit should
471 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
474 #ifdef CONFIG_SOC_MX6SL
475 static void set_preclk_from_osc(void)
477 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
480 reg = readl(&mxc_ccm->cscmr1);
481 reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
482 writel(reg, &mxc_ccm->cscmr1);
486 #define SRC_SCR_WARM_RESET_ENABLE 0
488 static void init_src(void)
490 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
494 * force warm reset sources to generate cold reset
495 * for a more reliable restart
497 val = readl(&src_regs->scr);
498 val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE);
499 writel(val, &src_regs->scr);
502 int arch_cpu_init(void)
506 /* Need to clear MMDC_CHx_MASK to make warm reset work. */
507 clear_mmdc_ch_mask();
510 * Disable self-bias circuit in the analog bandap.
511 * The self-bias circuit is used by the bandgap during startup.
512 * This bit should be set after the bandgap has initialized.
517 * When low freq boot is enabled, ROM will not set AHB
518 * freq, so we need to ensure AHB freq is 132MHz in such
521 if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
522 set_ahb_rate(132000000);
524 /* Set perclk to source from OSC 24MHz */
525 #if defined(CONFIG_SOC_MX6SL)
526 set_preclk_from_osc();
529 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
531 #ifdef CONFIG_VIDEO_IPUV3
532 gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3H;
534 #ifdef CONFIG_APBH_DMA
535 /* Timer is required for Initializing APBH DMA */
545 int board_postclk_init(void)
547 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
552 #ifndef CONFIG_SYS_DCACHE_OFF
553 void enable_caches(void)
555 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
556 enum dcache_option option = DCACHE_WRITETHROUGH;
558 enum dcache_option option = DCACHE_WRITEBACK;
561 /* Avoid random hang when download by usb */
562 invalidate_dcache_all();
564 /* Enable D-cache. I-cache is already enabled in start.S */
567 /* Enable caching on OCRAM and ROM */
568 mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
571 mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
577 #if defined(CONFIG_FEC_MXC)
578 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
580 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
581 struct fuse_bank *bank = &ocotp->bank[4];
582 struct fuse_bank4_regs *fuse =
583 (struct fuse_bank4_regs *)bank->fuse_regs;
585 u32 value = readl(&fuse->mac_addr_high);
586 mac[0] = (value >> 8);
589 value = readl(&fuse->mac_addr_low);
590 mac[2] = value >> 24;
591 mac[3] = value >> 16;
597 void boot_mode_apply(unsigned cfg_val)
600 struct src *psrc = (struct src *)SRC_BASE_ADDR;
601 writel(cfg_val, &psrc->gpr9);
602 reg = readl(&psrc->gpr10);
607 writel(reg, &psrc->gpr10);
610 * cfg_val will be used for
611 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
612 * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
613 * instead of SBMR1 to determine the boot device.
615 const struct boot_mode soc_boot_modes[] = {
616 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
617 /* reserved value should start rom usb */
618 {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
619 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
620 {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
621 {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
622 {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
623 {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
624 /* 4 bit bus width */
625 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
626 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
627 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
628 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
634 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
635 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
638 u32 reg, periph1, periph2;
640 if (is_cpu_type(MXC_CPU_MX6SX))
643 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
644 * to make sure PFD is working right, otherwise, PFDs may
645 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
646 * workaround in ROM code, as bus clock need it
649 mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
650 ANATOP_PFD_CLKGATE_MASK(1) |
651 ANATOP_PFD_CLKGATE_MASK(2) |
652 ANATOP_PFD_CLKGATE_MASK(3);
653 mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
654 ANATOP_PFD_CLKGATE_MASK(3);
656 reg = readl(&ccm->cbcmr);
657 periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
658 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
659 periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
660 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
662 /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
663 if ((periph2 != 0x2) && (periph1 != 0x2))
664 mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
666 if ((periph2 != 0x1) && (periph1 != 0x1) &&
667 (periph2 != 0x3) && (periph1 != 0x3))
668 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
670 writel(mask480, &anatop->pfd_480_set);
671 writel(mask528, &anatop->pfd_528_set);
672 writel(mask480, &anatop->pfd_480_clr);
673 writel(mask528, &anatop->pfd_528_clr);
676 #ifdef CONFIG_IMX_HDMI
677 void imx_enable_hdmi_phy(void)
679 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
681 reg = readb(&hdmi->phy_conf0);
682 reg |= HDMI_PHY_CONF0_PDZ_MASK;
683 writeb(reg, &hdmi->phy_conf0);
685 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
686 writeb(reg, &hdmi->phy_conf0);
688 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
689 writeb(reg, &hdmi->phy_conf0);
690 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
693 void imx_setup_hdmi(void)
695 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
696 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
699 /* Turn on HDMI PHY clock */
700 reg = readl(&mxc_ccm->CCGR2);
701 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
702 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
703 writel(reg, &mxc_ccm->CCGR2);
704 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
705 reg = readl(&mxc_ccm->chsccdr);
706 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
707 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
708 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
709 reg |= (CHSCCDR_PODF_DIVIDE_BY_3
710 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
711 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
712 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
713 writel(reg, &mxc_ccm->chsccdr);
717 #ifndef CONFIG_SYS_L2CACHE_OFF
718 #define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
719 void v7_outer_cache_enable(void)
721 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
726 * Set bit 22 in the auxiliary control register. If this bit
727 * is cleared, PL310 treats Normal Shared Non-cacheable
728 * accesses as Cacheable no-allocate.
730 setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
732 #if defined CONFIG_SOC_MX6SL
733 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
734 val = readl(&iomux->gpr[11]);
735 if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
736 /* L2 cache configured as OCRAM, reset it */
737 val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
738 writel(val, &iomux->gpr[11]);
742 /* Must disable the L2 before changing the latency parameters */
743 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
745 writel(0x132, &pl310->pl310_tag_latency_ctrl);
746 writel(0x132, &pl310->pl310_data_latency_ctrl);
748 val = readl(&pl310->pl310_prefetch_ctrl);
750 /* Turn on the L2 I/D prefetch */
754 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
755 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
756 * But according to ARM PL310 errata: 752271
757 * ID: 752271: Double linefill feature can cause data corruption
758 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
759 * Workaround: The only workaround to this erratum is to disable the
760 * double linefill feature. This is the default behavior.
763 #ifndef CONFIG_SOC_MX6Q
766 writel(val, &pl310->pl310_prefetch_ctrl);
768 val = readl(&pl310->pl310_power_ctrl);
769 val |= L2X0_DYNAMIC_CLK_GATING_EN;
770 val |= L2X0_STNDBY_MODE_EN;
771 writel(val, &pl310->pl310_power_ctrl);
773 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
776 void v7_outer_cache_disable(void)
778 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
780 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
782 #endif /* !CONFIG_SYS_L2CACHE_OFF */