3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
15 #include <imx_thermal.h>
16 #include <asm/armv7.h>
17 #include <asm/bootm.h>
18 #include <asm/pl310.h>
19 #include <asm/errno.h>
21 #include <asm/arch/imx-regs.h>
22 #include <asm/arch/crm_regs.h>
23 #include <asm/arch/regs-ocotp.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/mxc_hdmi.h>
26 #include <asm/arch/sys_proto.h>
27 #include <asm/imx-common/boot_mode.h>
28 #include <asm/imx-common/dma.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 #define __data __attribute__((section(".data")))
34 #ifdef CONFIG_MX6_TEMPERATURE_MIN
35 #define TEMPERATURE_MIN CONFIG_MX6_TEMPERATURE_MIN
37 #define TEMPERATURE_MIN (-40)
39 #ifdef CONFIG_MX6_TEMPERATURE_HOT
40 #define TEMPERATURE_HOT CONFIG_MX6_TEMPERATURE_HOT
42 #define TEMPERATURE_HOT 80
44 #ifdef CONFIG_MX6_TEMPERATURE_MAX
45 #define TEMPERATURE_MAX CONFIG_MX6_TEMPERATURE_MAX
47 #define TEMPERATURE_MAX 125
49 #define TEMP_AVG_COUNT 5
50 #define TEMP_WARN_THRESHOLD 5
66 #if defined(CONFIG_IMX6_THERMAL)
67 static const struct imx_thermal_plat imx6_thermal_plat = {
68 .regs = (void *)ANATOP_BASE_ADDR,
73 U_BOOT_DEVICE(imx6_thermal) = {
74 .name = "imx_thermal",
75 .platdata = &imx6_thermal_plat,
81 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
82 return readl(&scu->config) & 3;
87 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
88 u32 reg = readl(&anatop->digprog_sololite);
89 u32 type = ((reg >> 16) & 0xff);
91 if (type != MXC_CPU_MX6SL) {
92 reg = readl(&anatop->digprog);
93 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
94 u32 cfg = readl(&scu->config) & 3;
95 type = ((reg >> 16) & 0xff);
96 if (type == MXC_CPU_MX6DL) {
98 type = MXC_CPU_MX6SOLO;
101 if (type == MXC_CPU_MX6Q) {
107 reg &= 0xff; /* mx6 silicon revision */
108 return (type << 12) | (reg + 0x10);
111 #ifdef CONFIG_REVISION_TAG
112 u32 __weak get_board_rev(void)
114 u32 cpurev = get_cpu_rev();
115 u32 type = ((cpurev >> 12) & 0xff);
116 if (type == MXC_CPU_MX6SOLO)
117 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
119 if (type == MXC_CPU_MX6D)
120 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
128 struct aipstz_regs *aips1, *aips2;
129 #ifdef CONFIG_SOC_MX6SX
130 struct aipstz_regs *aips3;
133 aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
134 aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
135 #ifdef CONFIG_SOC_MX6SX
136 aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
140 * Set all MPROTx to be non-bufferable, trusted for R/W,
141 * not forced to user-mode.
143 writel(0x77777777, &aips1->mprot0);
144 writel(0x77777777, &aips1->mprot1);
145 writel(0x77777777, &aips2->mprot0);
146 writel(0x77777777, &aips2->mprot1);
149 * Set all OPACRx to be non-bufferable, not require
150 * supervisor privilege level for access,allow for
151 * write access and untrusted master access.
153 writel(0x00000000, &aips1->opacr0);
154 writel(0x00000000, &aips1->opacr1);
155 writel(0x00000000, &aips1->opacr2);
156 writel(0x00000000, &aips1->opacr3);
157 writel(0x00000000, &aips1->opacr4);
158 writel(0x00000000, &aips2->opacr0);
159 writel(0x00000000, &aips2->opacr1);
160 writel(0x00000000, &aips2->opacr2);
161 writel(0x00000000, &aips2->opacr3);
162 writel(0x00000000, &aips2->opacr4);
164 #ifdef CONFIG_SOC_MX6SX
166 * Set all MPROTx to be non-bufferable, trusted for R/W,
167 * not forced to user-mode.
169 writel(0x77777777, &aips3->mprot0);
170 writel(0x77777777, &aips3->mprot1);
173 * Set all OPACRx to be non-bufferable, not require
174 * supervisor privilege level for access,allow for
175 * write access and untrusted master access.
177 writel(0x00000000, &aips3->opacr0);
178 writel(0x00000000, &aips3->opacr1);
179 writel(0x00000000, &aips3->opacr2);
180 writel(0x00000000, &aips3->opacr3);
181 writel(0x00000000, &aips3->opacr4);
185 static void clear_ldo_ramp(void)
187 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
190 /* ROM may modify LDO ramp up time according to fuse setting, so in
191 * order to be in the safe side we neeed to reset these settings to
192 * match the reset value: 0'b00
194 reg = readl(&anatop->ana_misc2);
195 reg &= ~(0x3f << 24);
196 writel(reg, &anatop->ana_misc2);
200 * Set the PMU_REG_CORE register
202 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
203 * Possible values are from 0.725V to 1.450V in steps of
206 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
208 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
209 u32 val, step, old, reg = readl(&anatop->reg_core);
213 val = 0x00; /* Power gated off */
215 val = 0x1F; /* Power FET switched full on. No regulation */
217 val = (mv - 700) / 25;
235 old = (reg & (0x1F << shift)) >> shift;
236 step = abs(val - old);
240 reg = (reg & ~(0x1F << shift)) | (val << shift);
241 writel(reg, &anatop->reg_core);
244 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
252 static u32 __data thermal_calib;
254 #define FACTOR0 10000000
255 #define FACTOR1 15976
256 #define FACTOR2 4297157
258 int raw_to_celsius(unsigned int raw, unsigned int raw_25c, unsigned int raw_hot,
259 unsigned int hot_temp)
263 if (raw_hot != 0 && hot_temp != 0) {
264 unsigned int raw_n40c, ratio;
266 ratio = ((raw_25c - raw_hot) * 100) / (hot_temp - 25);
267 raw_n40c = raw_25c + (13 * ratio) / 20;
269 temperature = (raw_n40c - raw) * 100 / ratio - 40;
271 temperature = TEMPERATURE_MIN;
273 u64 temp64 = FACTOR0;
276 * Derived from linear interpolation:
277 * slope = 0.4297157 - (0.0015976 * 25C fuse)
278 * slope = (FACTOR2 - FACTOR1 * n1) / FACTOR0
279 * (Nmeas - n1) / (Tmeas - t1) = slope
280 * We want to reduce this down to the minimum computation necessary
281 * for each temperature read. Also, we want Tmeas in millicelsius
282 * and we don't want to lose precision from integer division. So...
283 * Tmeas = (Nmeas - n1) / slope + t1
284 * milli_Tmeas = 1000 * (Nmeas - n1) / slope + 1000 * t1
285 * milli_Tmeas = -1000 * (n1 - Nmeas) / slope + 1000 * t1
286 * Let constant c1 = (-1000 / slope)
287 * milli_Tmeas = (n1 - Nmeas) * c1 + 1000 * t1
288 * Let constant c2 = n1 *c1 + 1000 * t1
289 * milli_Tmeas = c2 - Nmeas * c1
292 do_div(temp64, FACTOR1 * raw_25c - FACTOR2);
294 c2 = raw_25c * c1 + 1000 * 25;
295 temperature = (c2 - raw * c1) / 1000;
300 int read_cpu_temperature(void)
302 unsigned int reg, tmp, i;
303 unsigned int raw_25c, raw_hot, hot_temp;
305 struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
306 struct mx6_ocotp_regs *const ocotp_regs = (void *)OCOTP_BASE_ADDR;
308 if (!thermal_calib) {
310 writel(1, &ocotp_regs->hw_ocotp_read_ctrl);
311 thermal_calib = readl(&ocotp_regs->hw_ocotp_ana1);
312 writel(0, &ocotp_regs->hw_ocotp_read_ctrl);
316 if (thermal_calib == 0 || thermal_calib == 0xffffffff)
317 return TEMPERATURE_MIN;
320 * [31:20] sensor value @ 25C
321 * [19:8] sensor value of hot
322 * [7:0] hot temperature value */
323 raw_25c = thermal_calib >> 20;
324 raw_hot = (thermal_calib & 0xfff00) >> 8;
325 hot_temp = thermal_calib & 0xff;
327 /* now we only using single measure, every time we measure
328 * the temperature, we will power on/off the anadig module
330 writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_clr);
331 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
333 /* write measure freq */
334 writel(327, &anatop->tempsense1);
335 writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_clr);
336 writel(BM_ANADIG_TEMPSENSE0_FINISHED, &anatop->tempsense0_clr);
337 writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_set);
339 /* average the temperature value over multiple readings */
340 for (i = 0; i < TEMP_AVG_COUNT; i++) {
344 while ((readl(&anatop->tempsense0) &
345 BM_ANADIG_TEMPSENSE0_FINISHED) == 0) {
350 if ((readl(&anatop->tempsense0) &
351 BM_ANADIG_TEMPSENSE0_FINISHED) == 0) {
353 printf("Failed to read temp sensor\n");
359 reg = (readl(&anatop->tempsense0) &
360 BM_ANADIG_TEMPSENSE0_TEMP_VALUE) >>
361 BP_ANADIG_TEMPSENSE0_TEMP_VALUE;
365 tmp = (tmp * i + reg) / (i + 1);
366 writel(BM_ANADIG_TEMPSENSE0_FINISHED,
367 &anatop->tempsense0_clr);
370 temperature = raw_to_celsius(tmp, raw_25c, raw_hot, hot_temp);
372 /* power down anatop thermal sensor */
373 writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_set);
374 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_clr);
379 int check_cpu_temperature(int boot)
381 static int __data max_temp;
382 int boot_limit = getenv_ulong("max_boot_temp", 10, TEMPERATURE_HOT);
383 int tmp = read_cpu_temperature();
386 if (tmp < TEMPERATURE_MIN || tmp > TEMPERATURE_MAX) {
387 printf("Temperature: can't get valid data!\n");
392 if (tmp > boot_limit) {
393 printf("CPU is %d C, too hot, resetting...\n", tmp);
397 if (tmp > max_temp) {
398 if (tmp > boot_limit - TEMP_WARN_THRESHOLD)
399 printf("WARNING: CPU temperature %d C\n", tmp);
403 printf("Temperature: %d C, calibration data 0x%x\n",
405 while (tmp >= boot_limit) {
407 printf("CPU is %d C, too hot to boot, waiting...\n",
414 tmp = read_cpu_temperature();
415 if (tmp > boot_limit - TEMP_WARN_THRESHOLD && tmp != max_temp)
416 printf("WARNING: CPU temperature %d C\n", tmp);
423 static void imx_set_wdog_powerdown(bool enable)
425 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
426 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
428 /* Write to the PDE (Power Down Enable) bit */
429 writew(enable, &wdog1->wmcr);
430 writew(enable, &wdog2->wmcr);
433 static void set_ahb_rate(u32 val)
435 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
438 div = get_periph_clk() / val - 1;
439 reg = readl(&mxc_ccm->cbcdr);
441 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
442 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
445 static void clear_mmdc_ch_mask(void)
447 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
449 /* Clear MMDC channel mask */
450 writel(0, &mxc_ccm->ccdr);
453 #ifdef CONFIG_SOC_MX6SL
454 static void set_preclk_from_osc(void)
456 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
459 reg = readl(&mxc_ccm->cscmr1);
460 reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
461 writel(reg, &mxc_ccm->cscmr1);
465 int arch_cpu_init(void)
469 /* Need to clear MMDC_CHx_MASK to make warm reset work. */
470 clear_mmdc_ch_mask();
473 * When low freq boot is enabled, ROM will not set AHB
474 * freq, so we need to ensure AHB freq is 132MHz in such
477 if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
478 set_ahb_rate(132000000);
480 /* Set perclk to source from OSC 24MHz */
481 #if defined(CONFIG_SOC_MX6SL)
482 set_preclk_from_osc();
485 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
487 #ifdef CONFIG_VIDEO_IPUV3
488 gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3H;
490 #ifdef CONFIG_APBH_DMA
491 /* Timer is required for Initializing APBH DMA */
499 int board_postclk_init(void)
501 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
506 #ifndef CONFIG_SYS_DCACHE_OFF
507 void enable_caches(void)
509 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
510 enum dcache_option option = DCACHE_WRITETHROUGH;
512 enum dcache_option option = DCACHE_WRITEBACK;
515 /* Avoid random hang when download by usb */
516 invalidate_dcache_all();
518 /* Enable D-cache. I-cache is already enabled in start.S */
521 /* Enable caching on OCRAM and ROM */
522 mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
525 mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
531 #if defined(CONFIG_FEC_MXC)
532 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
534 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
535 struct fuse_bank *bank = &ocotp->bank[4];
536 struct fuse_bank4_regs *fuse =
537 (struct fuse_bank4_regs *)bank->fuse_regs;
539 u32 value = readl(&fuse->mac_addr_high);
540 mac[0] = (value >> 8);
543 value = readl(&fuse->mac_addr_low);
544 mac[2] = value >> 24;
545 mac[3] = value >> 16;
551 void boot_mode_apply(unsigned cfg_val)
554 struct src *psrc = (struct src *)SRC_BASE_ADDR;
555 writel(cfg_val, &psrc->gpr9);
556 reg = readl(&psrc->gpr10);
561 writel(reg, &psrc->gpr10);
564 * cfg_val will be used for
565 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
566 * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
567 * instead of SBMR1 to determine the boot device.
569 const struct boot_mode soc_boot_modes[] = {
570 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
571 /* reserved value should start rom usb */
572 {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
573 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
574 {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
575 {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
576 {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
577 {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
578 /* 4 bit bus width */
579 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
580 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
581 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
582 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
588 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
589 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
592 u32 reg, periph1, periph2;
594 if (is_cpu_type(MXC_CPU_MX6SX))
597 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
598 * to make sure PFD is working right, otherwise, PFDs may
599 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
600 * workaround in ROM code, as bus clock need it
603 mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
604 ANATOP_PFD_CLKGATE_MASK(1) |
605 ANATOP_PFD_CLKGATE_MASK(2) |
606 ANATOP_PFD_CLKGATE_MASK(3);
607 mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
608 ANATOP_PFD_CLKGATE_MASK(3);
610 reg = readl(&ccm->cbcmr);
611 periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
612 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
613 periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
614 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
616 /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
617 if ((periph2 != 0x2) && (periph1 != 0x2))
618 mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
620 if ((periph2 != 0x1) && (periph1 != 0x1) &&
621 (periph2 != 0x3) && (periph1 != 0x3))
622 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
624 writel(mask480, &anatop->pfd_480_set);
625 writel(mask528, &anatop->pfd_528_set);
626 writel(mask480, &anatop->pfd_480_clr);
627 writel(mask528, &anatop->pfd_528_clr);
630 #ifdef CONFIG_IMX_HDMI
631 void imx_enable_hdmi_phy(void)
633 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
635 reg = readb(&hdmi->phy_conf0);
636 reg |= HDMI_PHY_CONF0_PDZ_MASK;
637 writeb(reg, &hdmi->phy_conf0);
639 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
640 writeb(reg, &hdmi->phy_conf0);
642 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
643 writeb(reg, &hdmi->phy_conf0);
644 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
647 void imx_setup_hdmi(void)
649 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
650 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
653 /* Turn on HDMI PHY clock */
654 reg = readl(&mxc_ccm->CCGR2);
655 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
656 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
657 writel(reg, &mxc_ccm->CCGR2);
658 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
659 reg = readl(&mxc_ccm->chsccdr);
660 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
661 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
662 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
663 reg |= (CHSCCDR_PODF_DIVIDE_BY_3
664 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
665 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
666 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
667 writel(reg, &mxc_ccm->chsccdr);
671 #ifndef CONFIG_SYS_L2CACHE_OFF
672 #define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
673 void v7_outer_cache_enable(void)
675 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
678 #if defined CONFIG_SOC_MX6SL
679 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
680 val = readl(&iomux->gpr[11]);
681 if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
682 /* L2 cache configured as OCRAM, reset it */
683 val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
684 writel(val, &iomux->gpr[11]);
688 /* Must disable the L2 before changing the latency parameters */
689 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
691 writel(0x132, &pl310->pl310_tag_latency_ctrl);
692 writel(0x132, &pl310->pl310_data_latency_ctrl);
694 val = readl(&pl310->pl310_prefetch_ctrl);
696 /* Turn on the L2 I/D prefetch */
700 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
701 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
702 * But according to ARM PL310 errata: 752271
703 * ID: 752271: Double linefill feature can cause data corruption
704 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
705 * Workaround: The only workaround to this erratum is to disable the
706 * double linefill feature. This is the default behavior.
709 #ifndef CONFIG_SOC_MX6Q
712 writel(val, &pl310->pl310_prefetch_ctrl);
714 val = readl(&pl310->pl310_power_ctrl);
715 val |= L2X0_DYNAMIC_CLK_GATING_EN;
716 val |= L2X0_STNDBY_MODE_EN;
717 writel(val, &pl310->pl310_power_ctrl);
719 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
722 void v7_outer_cache_disable(void)
724 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
726 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
728 #endif /* !CONFIG_SYS_L2CACHE_OFF */