3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/armv7.h>
16 #include <asm/bootm.h>
17 #include <asm/pl310.h>
18 #include <asm/errno.h>
20 #include <asm/arch/imx-regs.h>
21 #include <asm/arch/clock.h>
22 #include <asm/arch/regs-ocotp.h>
23 #include <asm/arch/sys_proto.h>
24 #include <asm/imx-common/boot_mode.h>
25 #include <asm/imx-common/dma.h>
27 #include <asm/arch/mxc_hdmi.h>
28 #include <asm/arch/crm_regs.h>
30 #include <imx_thermal.h>
32 DECLARE_GLOBAL_DATA_PTR;
34 #define __data __attribute__((section(".data")))
36 #ifdef CONFIG_MX6_TEMPERATURE_MIN
37 #define TEMPERATURE_MIN CONFIG_MX6_TEMPERATURE_MIN
39 #define TEMPERATURE_MIN (-40)
41 #ifdef CONFIG_MX6_TEMPERATURE_HOT
42 #define TEMPERATURE_HOT CONFIG_MX6_TEMPERATURE_HOT
44 #define TEMPERATURE_HOT 80
46 #ifdef CONFIG_MX6_TEMPERATURE_MAX
47 #define TEMPERATURE_MAX CONFIG_MX6_TEMPERATURE_MAX
49 #define TEMPERATURE_MAX 125
51 #define TEMP_AVG_COUNT 5
52 #define TEMP_WARN_THRESHOLD 5
68 #if defined(CONFIG_IMX6_THERMAL)
69 static const struct imx_thermal_plat imx6_thermal_plat = {
70 .regs = (void *)ANATOP_BASE_ADDR,
75 U_BOOT_DEVICE(imx6_thermal) = {
76 .name = "imx_thermal",
77 .platdata = &imx6_thermal_plat,
83 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
84 return readl(&scu->config) & 3;
89 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
90 u32 reg = readl(&anatop->digprog_sololite);
91 u32 type = ((reg >> 16) & 0xff);
94 if (type != MXC_CPU_MX6SL) {
95 reg = readl(&anatop->digprog);
96 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
97 cfg = readl(&scu->config) & 3;
98 type = ((reg >> 16) & 0xff);
99 if (type == MXC_CPU_MX6DL) {
101 type = MXC_CPU_MX6SOLO;
104 if (type == MXC_CPU_MX6Q) {
110 major = ((reg >> 8) & 0xff);
112 ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) {
114 type = MXC_CPU_MX6QP;
116 type = MXC_CPU_MX6DP;
118 reg &= 0xff; /* mx6 silicon revision */
119 if (type == MXC_CPU_MX6Q) {
130 printf("Unknown CPU Rev.: 0x%02x\n", reg);
133 return (type << 12) | (reg + (0x10 * (major + 1)));
137 * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
138 * defines a 2-bit SPEED_GRADING
140 #define OCOTP_CFG3_SPEED_SHIFT 16
141 #define OCOTP_CFG3_SPEED_800MHZ 0
142 #define OCOTP_CFG3_SPEED_850MHZ 1
143 #define OCOTP_CFG3_SPEED_1GHZ 2
144 #define OCOTP_CFG3_SPEED_1P2GHZ 3
146 u32 get_cpu_speed_grade_hz(void)
150 if (fuse_read(0, 3, &val)) {
151 printf("Failed to read speed_grade fuse\n");
154 val >>= OCOTP_CFG3_SPEED_SHIFT;
158 /* Valid for IMX6DQ */
159 case OCOTP_CFG3_SPEED_1P2GHZ:
160 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
162 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
163 case OCOTP_CFG3_SPEED_1GHZ:
165 /* Valid for IMX6DQ */
166 case OCOTP_CFG3_SPEED_850MHZ:
167 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
169 /* Valid for IMX6SX/IMX6SDL/IMX6DQ/IMX6ULL */
170 case OCOTP_CFG3_SPEED_800MHZ:
177 * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
178 * defines a 2-bit Temperature Grade
180 * return temperature grade and min/max temperature in celcius
182 #define OCOTP_MEM0_TEMP_SHIFT 6
184 u32 get_cpu_temp_grade(int *minc, int *maxc)
188 if (fuse_read(1, 0, &val)) {
189 printf("Failed to read temp_grade fuse\n");
192 val >>= OCOTP_MEM0_TEMP_SHIFT;
196 if (val == TEMP_AUTOMOTIVE) {
199 } else if (val == TEMP_INDUSTRIAL) {
202 } else if (val == TEMP_EXTCOMMERCIAL) {
213 #ifdef CONFIG_REVISION_TAG
214 u32 __weak get_board_rev(void)
216 u32 cpurev = get_cpu_rev();
217 u32 type = ((cpurev >> 12) & 0xff);
218 if (type == MXC_CPU_MX6SOLO)
219 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
221 if (type == MXC_CPU_MX6D)
222 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
230 struct aipstz_regs *aips1, *aips2;
231 #ifdef AIPS3_CONFIG_BASE_ADDR
232 struct aipstz_regs *aips3;
234 aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
235 aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
236 #ifdef AIPS3_CONFIG_BASE_ADDR
237 aips3 = (struct aipstz_regs *)AIPS3_CONFIG_BASE_ADDR;
241 * Set all MPROTx to be non-bufferable, trusted for R/W,
242 * not forced to user-mode.
244 writel(0x77777777, &aips1->mprot0);
245 writel(0x77777777, &aips1->mprot1);
246 writel(0x77777777, &aips2->mprot0);
247 writel(0x77777777, &aips2->mprot1);
250 * Set all OPACRx to be non-bufferable, not require
251 * supervisor privilege level for access,allow for
252 * write access and untrusted master access.
254 writel(0x00000000, &aips1->opacr0);
255 writel(0x00000000, &aips1->opacr1);
256 writel(0x00000000, &aips1->opacr2);
257 writel(0x00000000, &aips1->opacr3);
258 writel(0x00000000, &aips1->opacr4);
259 writel(0x00000000, &aips2->opacr0);
260 writel(0x00000000, &aips2->opacr1);
261 writel(0x00000000, &aips2->opacr2);
262 writel(0x00000000, &aips2->opacr3);
263 writel(0x00000000, &aips2->opacr4);
265 #ifdef AIPS3_CONFIG_BASE_ADDR
267 * Set all MPROTx to be non-bufferable, trusted for R/W,
268 * not forced to user-mode.
270 writel(0x77777777, &aips3->mprot0);
271 writel(0x77777777, &aips3->mprot1);
274 * Set all OPACRx to be non-bufferable, not require
275 * supervisor privilege level for access,allow for
276 * write access and untrusted master access.
278 writel(0x00000000, &aips3->opacr0);
279 writel(0x00000000, &aips3->opacr1);
280 writel(0x00000000, &aips3->opacr2);
281 writel(0x00000000, &aips3->opacr3);
282 writel(0x00000000, &aips3->opacr4);
286 static void clear_ldo_ramp(void)
288 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
291 /* ROM may modify LDO ramp up time according to fuse setting, so in
292 * order to be in the safe side we neeed to reset these settings to
293 * match the reset value: 0'b00
295 reg = readl(&anatop->ana_misc2);
296 reg &= ~(0x3f << 24);
297 writel(reg, &anatop->ana_misc2);
301 * Set the PMU_REG_CORE register
303 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
304 * Possible values are from 0.725V to 1.450V in steps of
307 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
309 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
310 u32 val, step, old, reg = readl(&anatop->reg_core);
314 val = 0x00; /* Power gated off */
316 val = 0x1F; /* Power FET switched full on. No regulation */
318 val = (mv - 700) / 25;
336 old = (reg & (0x1F << shift)) >> shift;
337 step = abs(val - old);
341 reg = (reg & ~(0x1F << shift)) | (val << shift);
342 writel(reg, &anatop->reg_core);
345 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
353 int check_cpu_temperature(int boot)
356 static int __data max_temp;
357 int boot_limit = getenv_ulong("max_boot_temp", 10, TEMPERATURE_HOT);
362 if (uclass_get_device_by_name(UCLASS_THERMAL, "imx_thermal", &dev)) {
364 printf("No thermal device found; cannot read CPU temperature\n");
370 ret = thermal_get_temp(dev, &tmp);
372 printf("Failed to read temperature: %d\n", ret);
373 return TEMPERATURE_MAX;
375 if (tmp < TEMPERATURE_MIN || tmp > TEMPERATURE_MAX) {
376 printf("Temperature: can't get valid data!\n");
381 if (tmp > boot_limit) {
382 printf("CPU is %d C; too hot, resetting...\n", tmp);
386 if (tmp > max_temp) {
387 if (tmp > boot_limit - TEMP_WARN_THRESHOLD)
388 printf("WARNING: CPU temperature %d C\n", tmp);
392 while (tmp >= boot_limit) {
394 printf("CPU is %d C; too hot to boot, waiting...\n",
401 ret = thermal_get_temp(dev, &tmp);
403 printf("Failed to read temperature: %d\n", ret);
404 return TEMPERATURE_MAX;
406 if (tmp > boot_limit - TEMP_WARN_THRESHOLD && tmp != max_temp)
407 printf("WARNING: CPU temperature %d C\n", tmp);
414 static void imx_set_wdog_powerdown(bool enable)
416 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
417 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
418 struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
420 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
421 is_cpu_type(MXC_CPU_MX6ULL))
422 writew(enable, &wdog3->wmcr);
424 /* Write to the PDE (Power Down Enable) bit */
425 writew(enable, &wdog1->wmcr);
426 writew(enable, &wdog2->wmcr);
429 static void set_ahb_rate(u32 val)
431 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
434 div = get_periph_clk() / val - 1;
435 reg = readl(&mxc_ccm->cbcdr);
437 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
438 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
441 static void clear_mmdc_ch_mask(void)
443 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
445 reg = readl(&mxc_ccm->ccdr);
447 /* Clear MMDC channel mask */
448 reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
449 writel(reg, &mxc_ccm->ccdr);
452 static void init_bandgap(void)
454 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
456 * Ensure the bandgap has stabilized.
458 while (!(readl(&anatop->ana_misc0) & 0x80))
461 * For best noise performance of the analog blocks using the
462 * outputs of the bandgap, the reftop_selfbiasoff bit should
465 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
468 #ifdef CONFIG_SOC_MX6SL
469 static void set_preclk_from_osc(void)
471 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
474 reg = readl(&mxc_ccm->cscmr1);
475 reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
476 writel(reg, &mxc_ccm->cscmr1);
480 #define SRC_SCR_WARM_RESET_ENABLE 0
482 static void init_src(void)
484 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
488 * force warm reset sources to generate cold reset
489 * for a more reliable restart
491 val = readl(&src_regs->scr);
492 val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE);
493 writel(val, &src_regs->scr);
496 int arch_cpu_init(void)
500 /* Need to clear MMDC_CHx_MASK to make warm reset work. */
501 clear_mmdc_ch_mask();
504 * Disable self-bias circuit in the analog bandap.
505 * The self-bias circuit is used by the bandgap during startup.
506 * This bit should be set after the bandgap has initialized.
511 * When low freq boot is enabled, ROM will not set AHB
512 * freq, so we need to ensure AHB freq is 132MHz in such
515 if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
516 set_ahb_rate(132000000);
518 /* Set perclk to source from OSC 24MHz */
519 #if defined(CONFIG_SOC_MX6SL)
520 set_preclk_from_osc();
523 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
525 #ifdef CONFIG_VIDEO_IPUV3
526 gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3H;
528 #ifdef CONFIG_APBH_DMA
529 /* Timer is required for Initializing APBH DMA */
539 int board_postclk_init(void)
541 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
546 #ifndef CONFIG_SYS_DCACHE_OFF
547 void enable_caches(void)
549 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
550 enum dcache_option option = DCACHE_WRITETHROUGH;
552 enum dcache_option option = DCACHE_WRITEBACK;
555 /* Avoid random hang when download by usb */
556 invalidate_dcache_all();
558 /* Enable D-cache. I-cache is already enabled in start.S */
561 /* Enable caching on OCRAM and ROM */
562 mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
565 mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
571 #if defined(CONFIG_FEC_MXC)
572 __weak void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
574 unsigned int mac0, mac1;
577 if (dev_id < 0 || dev_id > 2)
580 if (fuse_read(4, 2, &mac0)) {
581 printf("Failed to read MAC0 fuse\n");
584 if (fuse_read(4, 3, &mac1)) {
585 printf("Failed to read MAC1 fuse\n");
602 void boot_mode_apply(unsigned cfg_val)
605 struct src *psrc = (struct src *)SRC_BASE_ADDR;
606 writel(cfg_val, &psrc->gpr9);
607 reg = readl(&psrc->gpr10);
612 writel(reg, &psrc->gpr10);
615 * cfg_val will be used for
616 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
617 * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
618 * instead of SBMR1 to determine the boot device.
620 const struct boot_mode soc_boot_modes[] = {
621 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
622 /* reserved value should start rom usb */
623 {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
624 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
625 {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
626 {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
627 {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
628 {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
629 /* 4 bit bus width */
630 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
631 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
632 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
633 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
639 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
640 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
643 u32 reg, periph1, periph2;
645 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
646 is_cpu_type(MXC_CPU_MX6ULL))
649 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
650 * to make sure PFD is working right, otherwise, PFDs may
651 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
652 * workaround in ROM code, as bus clock need it
655 mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
656 ANATOP_PFD_CLKGATE_MASK(1) |
657 ANATOP_PFD_CLKGATE_MASK(2) |
658 ANATOP_PFD_CLKGATE_MASK(3);
659 mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
660 ANATOP_PFD_CLKGATE_MASK(3);
662 reg = readl(&ccm->cbcmr);
663 periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
664 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
665 periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
666 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
668 /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
669 if ((periph2 != 0x2) && (periph1 != 0x2))
670 mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
672 if ((periph2 != 0x1) && (periph1 != 0x1) &&
673 (periph2 != 0x3) && (periph1 != 0x3))
674 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
676 writel(mask480, &anatop->pfd_480_set);
677 writel(mask528, &anatop->pfd_528_set);
678 writel(mask480, &anatop->pfd_480_clr);
679 writel(mask528, &anatop->pfd_528_clr);
682 #ifdef CONFIG_IMX_HDMI
683 void imx_enable_hdmi_phy(void)
685 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
687 reg = readb(&hdmi->phy_conf0);
688 reg |= HDMI_PHY_CONF0_PDZ_MASK;
689 writeb(reg, &hdmi->phy_conf0);
691 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
692 writeb(reg, &hdmi->phy_conf0);
694 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
695 writeb(reg, &hdmi->phy_conf0);
696 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
699 void imx_setup_hdmi(void)
701 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
702 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
705 /* Turn on HDMI PHY clock */
706 reg = readl(&mxc_ccm->CCGR2);
707 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
708 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
709 writel(reg, &mxc_ccm->CCGR2);
710 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
711 reg = readl(&mxc_ccm->chsccdr);
712 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
713 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
714 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
715 reg |= (CHSCCDR_PODF_DIVIDE_BY_3
716 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
717 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
718 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
719 writel(reg, &mxc_ccm->chsccdr);
723 #ifndef CONFIG_SYS_L2CACHE_OFF
724 #define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
725 void v7_outer_cache_enable(void)
727 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
732 * Set bit 22 in the auxiliary control register. If this bit
733 * is cleared, PL310 treats Normal Shared Non-cacheable
734 * accesses as Cacheable no-allocate.
736 setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
738 #if defined CONFIG_SOC_MX6SL
739 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
740 val = readl(&iomux->gpr[11]);
741 if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
742 /* L2 cache configured as OCRAM, reset it */
743 val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
744 writel(val, &iomux->gpr[11]);
748 /* Must disable the L2 before changing the latency parameters */
749 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
751 writel(0x132, &pl310->pl310_tag_latency_ctrl);
752 writel(0x132, &pl310->pl310_data_latency_ctrl);
754 val = readl(&pl310->pl310_prefetch_ctrl);
756 /* Turn on the L2 I/D prefetch */
760 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
761 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
762 * But according to ARM PL310 errata: 752271
763 * ID: 752271: Double linefill feature can cause data corruption
764 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
765 * Workaround: The only workaround to this erratum is to disable the
766 * double linefill feature. This is the default behavior.
769 #ifndef CONFIG_SOC_MX6Q
772 writel(val, &pl310->pl310_prefetch_ctrl);
774 val = readl(&pl310->pl310_power_ctrl);
775 val |= L2X0_DYNAMIC_CLK_GATING_EN;
776 val |= L2X0_STNDBY_MODE_EN;
777 writel(val, &pl310->pl310_power_ctrl);
779 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
782 void v7_outer_cache_disable(void)
784 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
786 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
788 #endif /* !CONFIG_SYS_L2CACHE_OFF */