3 * Clock initialization for OMAP4
6 * Texas Instruments, <www.ti.com>
8 * Aneesh V <aneesh@ti.com>
10 * Based on previous work by:
11 * Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * Rajendra Nayak <rnayak@ti.com>
14 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/omap_common.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/utils.h>
23 #include <asm/omap_gpio.h>
26 #ifndef CONFIG_SPL_BUILD
28 * printing to console doesn't work unless
29 * this code is executed from SPL
31 #define printf(fmt, args...)
35 const u32 sys_clk_array[8] = {
36 12000000, /* 12 MHz */
37 20000000, /* 20 MHz */
38 16800000, /* 16.8 MHz */
39 19200000, /* 19.2 MHz */
40 26000000, /* 26 MHz */
41 27000000, /* 27 MHz */
42 38400000, /* 38.4 MHz */
45 static inline u32 __get_sys_clk_index(void)
49 * For ES1 the ROM code calibration of sys clock is not reliable
50 * due to hw issue. So, use hard-coded value. If this value is not
51 * correct for any board over-ride this function in board file
52 * From ES2.0 onwards you will get this information from
55 if (omap_revision() == OMAP4430_ES1_0)
56 ind = OMAP_SYS_CLK_IND_38_4_MHZ;
58 /* SYS_CLKSEL - 1 to match the dpll param array indices */
59 ind = (readl((*prcm)->cm_sys_clksel) &
60 CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
65 u32 get_sys_clk_index(void)
66 __attribute__ ((weak, alias("__get_sys_clk_index")));
68 u32 get_sys_clk_freq(void)
70 u8 index = get_sys_clk_index();
71 return sys_clk_array[index];
74 void setup_post_dividers(u32 const base, const struct dpll_params *params)
76 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
78 /* Setup post-dividers */
80 writel(params->m2, &dpll_regs->cm_div_m2_dpll);
82 writel(params->m3, &dpll_regs->cm_div_m3_dpll);
83 if (params->m4_h11 >= 0)
84 writel(params->m4_h11, &dpll_regs->cm_div_m4_h11_dpll);
85 if (params->m5_h12 >= 0)
86 writel(params->m5_h12, &dpll_regs->cm_div_m5_h12_dpll);
87 if (params->m6_h13 >= 0)
88 writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll);
89 if (params->m7_h14 >= 0)
90 writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll);
92 writel(params->h21, &dpll_regs->cm_div_h21_dpll);
94 writel(params->h22, &dpll_regs->cm_div_h22_dpll);
96 writel(params->h23, &dpll_regs->cm_div_h23_dpll);
98 writel(params->h24, &dpll_regs->cm_div_h24_dpll);
101 static inline void do_bypass_dpll(u32 const base)
103 struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
105 clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
106 CM_CLKMODE_DPLL_DPLL_EN_MASK,
107 DPLL_EN_FAST_RELOCK_BYPASS <<
108 CM_CLKMODE_DPLL_EN_SHIFT);
111 static inline void wait_for_bypass(u32 const base)
113 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
115 if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
117 printf("Bypassing DPLL failed %x\n", base);
121 static inline void do_lock_dpll(u32 const base)
123 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
125 clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
126 CM_CLKMODE_DPLL_DPLL_EN_MASK,
127 DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
130 static inline void wait_for_lock(u32 const base)
132 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
134 if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
135 &dpll_regs->cm_idlest_dpll, LDELAY)) {
136 printf("DPLL locking failed for %x\n", base);
141 inline u32 check_for_lock(u32 const base)
143 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
144 u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK;
149 const struct dpll_params *get_mpu_dpll_params(struct dplls const *dpll_data)
151 u32 sysclk_ind = get_sys_clk_index();
152 return &dpll_data->mpu[sysclk_ind];
155 const struct dpll_params *get_core_dpll_params(struct dplls const *dpll_data)
157 u32 sysclk_ind = get_sys_clk_index();
158 return &dpll_data->core[sysclk_ind];
161 const struct dpll_params *get_per_dpll_params(struct dplls const *dpll_data)
163 u32 sysclk_ind = get_sys_clk_index();
164 return &dpll_data->per[sysclk_ind];
167 const struct dpll_params *get_iva_dpll_params(struct dplls const *dpll_data)
169 u32 sysclk_ind = get_sys_clk_index();
170 return &dpll_data->iva[sysclk_ind];
173 const struct dpll_params *get_usb_dpll_params(struct dplls const *dpll_data)
175 u32 sysclk_ind = get_sys_clk_index();
176 return &dpll_data->usb[sysclk_ind];
179 const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data)
181 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
182 u32 sysclk_ind = get_sys_clk_index();
183 return &dpll_data->abe[sysclk_ind];
185 return dpll_data->abe;
189 static const struct dpll_params *get_ddr_dpll_params
190 (struct dplls const *dpll_data)
192 u32 sysclk_ind = get_sys_clk_index();
196 return &dpll_data->ddr[sysclk_ind];
199 static void do_setup_dpll(u32 const base, const struct dpll_params *params,
203 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
208 temp = readl(&dpll_regs->cm_clksel_dpll);
210 if (check_for_lock(base)) {
212 * The Dpll has already been locked by rom code using CH.
213 * Check if M,N are matching with Ideal nominal opp values.
214 * If matches, skip the rest otherwise relock.
216 M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT;
217 N = (temp & CM_CLKSEL_DPLL_N_MASK) >> CM_CLKSEL_DPLL_N_SHIFT;
218 if ((M != (params->m)) || (N != (params->n))) {
219 debug("\n %s Dpll locked, but not for ideal M = %d,"
220 "N = %d values, current values are M = %d,"
221 "N= %d" , dpll, params->m, params->n,
224 /* Dpll locked with ideal values for nominal opps. */
225 debug("\n %s Dpll already locked with ideal"
226 "nominal opp values", dpll);
227 goto setup_post_dividers;
234 temp &= ~CM_CLKSEL_DPLL_M_MASK;
235 temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
237 temp &= ~CM_CLKSEL_DPLL_N_MASK;
238 temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
240 writel(temp, &dpll_regs->cm_clksel_dpll);
247 setup_post_dividers(base, params);
249 /* Wait till the DPLL locks */
254 u32 omap_ddr_clk(void)
256 u32 ddr_clk, sys_clk_khz, omap_rev, divider;
257 const struct dpll_params *core_dpll_params;
259 omap_rev = omap_revision();
260 sys_clk_khz = get_sys_clk_freq() / 1000;
262 core_dpll_params = get_core_dpll_params(*dplls_data);
264 debug("sys_clk %d\n ", sys_clk_khz * 1000);
266 /* Find Core DPLL locked frequency first */
267 ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
268 (core_dpll_params->n + 1);
270 if (omap_rev < OMAP5430_ES1_0) {
272 * DDR frequency is PHY_ROOT_CLK/2
273 * PHY_ROOT_CLK = Fdpll/2/M2
278 * DDR frequency is PHY_ROOT_CLK
279 * PHY_ROOT_CLK = Fdpll/2/M2
284 ddr_clk = ddr_clk / divider / core_dpll_params->m2;
285 ddr_clk *= 1000; /* convert to Hz */
286 debug("ddr_clk %d\n ", ddr_clk);
294 * Resulting MPU frequencies:
295 * 4430 ES1.0 : 600 MHz
296 * 4430 ES2.x : 792 MHz (OPP Turbo)
297 * 4460 : 920 MHz (OPP Turbo) - DCC disabled
299 void configure_mpu_dpll(void)
301 const struct dpll_params *params;
302 struct dpll_regs *mpu_dpll_regs;
304 omap_rev = omap_revision();
307 * DCC and clock divider settings for 4460.
308 * DCC is required, if more than a certain frequency is required.
312 if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) {
314 (struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu);
315 bypass_dpll((*prcm)->cm_clkmode_dpll_mpu);
316 clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
317 MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
318 setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
319 MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
320 clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
321 CM_CLKSEL_DCC_EN_MASK);
324 params = get_mpu_dpll_params(*dplls_data);
326 do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
327 debug("MPU DPLL locked\n");
330 #ifdef CONFIG_USB_EHCI_OMAP
331 static void setup_usb_dpll(void)
333 const struct dpll_params *params;
334 u32 sys_clk_khz, sd_div, num, den;
336 sys_clk_khz = get_sys_clk_freq() / 1000;
339 * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
340 * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
341 * - where CLKINP is sys_clk in MHz
342 * Use CLKINP in KHz and adjust the denominator accordingly so
343 * that we have enough accuracy and at the same time no overflow
345 params = get_usb_dpll_params(*dplls_data);
346 num = params->m * sys_clk_khz;
347 den = (params->n + 1) * 250 * 1000;
350 clrsetbits_le32((*prcm)->cm_clksel_dpll_usb,
351 CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
352 sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
354 /* Now setup the dpll with the regular function */
355 do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
359 static void setup_dplls(void)
362 const struct dpll_params *params;
364 debug("setup_dplls\n");
367 params = get_core_dpll_params(*dplls_data); /* default - safest */
369 * Do not lock the core DPLL now. Just set it up.
370 * Core DPLL will be locked after setting up EMIF
371 * using the FREQ_UPDATE method(freq_update_core())
373 if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
374 do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
375 DPLL_NO_LOCK, "core");
377 do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
379 /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
380 temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
381 (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
382 (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
383 writel(temp, (*prcm)->cm_clksel_core);
384 debug("Core DPLL configured\n");
387 params = get_per_dpll_params(*dplls_data);
388 do_setup_dpll((*prcm)->cm_clkmode_dpll_per,
389 params, DPLL_LOCK, "per");
390 debug("PER DPLL locked\n");
393 configure_mpu_dpll();
395 #ifdef CONFIG_USB_EHCI_OMAP
398 params = get_ddr_dpll_params(*dplls_data);
399 do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy,
400 params, DPLL_LOCK, "ddr");
403 #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
404 static void setup_non_essential_dplls(void)
407 const struct dpll_params *params;
410 clrsetbits_le32((*prcm)->cm_bypclk_dpll_iva,
411 CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
413 params = get_iva_dpll_params(*dplls_data);
414 do_setup_dpll((*prcm)->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva");
416 /* Configure ABE dpll */
417 params = get_abe_dpll_params(*dplls_data);
418 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
419 abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
421 if (omap_revision() == DRA752_ES1_0)
422 /* Select the sys clk for dpll_abe */
423 clrsetbits_le32((*prcm)->cm_abe_pll_sys_clksel,
424 CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK,
425 CM_ABE_PLL_SYS_CLKSEL_SYSCLK2);
427 abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
429 * We need to enable some additional options to achieve
430 * 196.608MHz from 32768 Hz
432 setbits_le32((*prcm)->cm_clkmode_dpll_abe,
433 CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
434 CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
435 CM_CLKMODE_DPLL_LPMODE_EN_MASK|
436 CM_CLKMODE_DPLL_REGM4XEN_MASK);
437 /* Spend 4 REFCLK cycles at each stage */
438 clrsetbits_le32((*prcm)->cm_clkmode_dpll_abe,
439 CM_CLKMODE_DPLL_RAMP_RATE_MASK,
440 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
443 /* Select the right reference clk */
444 clrsetbits_le32((*prcm)->cm_abe_pll_ref_clksel,
445 CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
446 abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
448 do_setup_dpll((*prcm)->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe");
452 u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic)
456 volt_offset -= pmic->base_offset;
458 offset_code = (volt_offset + pmic->step - 1) / pmic->step;
461 * Offset codes 1-6 all give the base voltage in Palmas
462 * Offset code 0 switches OFF the SMPS
464 return offset_code + pmic->start_code;
467 void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
470 u32 offset = volt_mv;
476 pmic->pmic_bus_init();
477 /* See if we can first get the GPIO if needed */
479 ret = gpio_request(pmic->gpio, "PMIC_GPIO");
482 printf("%s: gpio %d request failed %d\n", __func__,
487 /* Pull the GPIO low to select SET0 register, while we program SET1 */
489 gpio_direction_output(pmic->gpio, 0);
491 /* convert to uV for better accuracy in the calculations */
494 offset_code = get_offset_code(offset, pmic);
496 debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
499 if (pmic->pmic_write(pmic->i2c_slave_addr, vcore_reg, offset_code))
500 printf("Scaling voltage failed for 0x%x\n", vcore_reg);
503 gpio_direction_output(pmic->gpio, 1);
506 static u32 optimize_vcore_voltage(struct volts const *v)
514 switch (v->efuse.reg_bits) {
516 val = readw(v->efuse.reg);
519 val = readl(v->efuse.reg);
522 printf("Error: efuse 0x%08x bits=%d unknown\n",
523 v->efuse.reg, v->efuse.reg_bits);
528 printf("Error: efuse 0x%08x bits=%d val=0, using %d\n",
529 v->efuse.reg, v->efuse.reg_bits, v->value);
533 debug("%s:efuse 0x%08x bits=%d Vnom=%d, using efuse value %d\n",
534 __func__, v->efuse.reg, v->efuse.reg_bits, v->value, val);
539 * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
540 * We set the maximum voltages allowed here because Smart-Reflex is not
541 * enabled in bootloader. Voltage initialization in the kernel will set
542 * these to the nominal values after enabling Smart-Reflex
544 void scale_vcores(struct vcores_data const *vcores)
548 val = optimize_vcore_voltage(&vcores->core);
549 do_scale_vcore(vcores->core.addr, val, vcores->core.pmic);
551 val = optimize_vcore_voltage(&vcores->mpu);
552 do_scale_vcore(vcores->mpu.addr, val, vcores->mpu.pmic);
554 /* Configure MPU ABB LDO after scale */
555 abb_setup((*ctrl)->control_std_fuse_opp_vdd_mpu_2,
556 (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl,
557 (*prcm)->prm_abbldo_mpu_setup,
558 (*prcm)->prm_abbldo_mpu_ctrl,
559 (*prcm)->prm_irqstatus_mpu_2,
560 OMAP_ABB_MPU_TXDONE_MASK,
563 val = optimize_vcore_voltage(&vcores->mm);
564 do_scale_vcore(vcores->mm.addr, val, vcores->mm.pmic);
566 val = optimize_vcore_voltage(&vcores->gpu);
567 do_scale_vcore(vcores->gpu.addr, val, vcores->gpu.pmic);
569 val = optimize_vcore_voltage(&vcores->eve);
570 do_scale_vcore(vcores->eve.addr, val, vcores->eve.pmic);
572 val = optimize_vcore_voltage(&vcores->iva);
573 do_scale_vcore(vcores->iva.addr, val, vcores->iva.pmic);
575 if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
576 /* Configure LDO SRAM "magic" bits */
577 writel(2, (*prcm)->prm_sldo_core_setup);
578 writel(2, (*prcm)->prm_sldo_mpu_setup);
579 writel(2, (*prcm)->prm_sldo_mm_setup);
583 static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
585 clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
586 enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
587 debug("Enable clock domain - %x\n", clkctrl_reg);
590 static inline void wait_for_clk_enable(u32 clkctrl_addr)
592 u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
595 while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
596 (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
598 clkctrl = readl(clkctrl_addr);
599 idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
600 MODULE_CLKCTRL_IDLEST_SHIFT;
602 printf("Clock enable failed for 0x%x idlest 0x%x\n",
603 clkctrl_addr, clkctrl);
609 static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode,
612 clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
613 enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
614 debug("Enable clock module - %x\n", clkctrl_addr);
616 wait_for_clk_enable(clkctrl_addr);
619 void freq_update_core(void)
621 u32 freq_config1 = 0;
622 const struct dpll_params *core_dpll_params;
623 u32 omap_rev = omap_revision();
625 core_dpll_params = get_core_dpll_params(*dplls_data);
626 /* Put EMIF clock domain in sw wakeup mode */
627 enable_clock_domain((*prcm)->cm_memif_clkstctrl,
628 CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
629 wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
630 wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
632 freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
633 SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
635 freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
636 SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
638 freq_config1 |= (core_dpll_params->m2 <<
639 SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
640 SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
642 writel(freq_config1, (*prcm)->cm_shadow_freq_config1);
643 if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
644 (u32 *) (*prcm)->cm_shadow_freq_config1, LDELAY)) {
645 puts("FREQ UPDATE procedure failed!!");
650 * Putting EMIF in HW_AUTO is seen to be causing issues with
651 * EMIF clocks and the master DLL. Keep EMIF in SW_WKUP
652 * in OMAP5430 ES1.0 silicon
654 if (omap_rev != OMAP5430_ES1_0) {
655 /* Put EMIF clock domain back in hw auto mode */
656 enable_clock_domain((*prcm)->cm_memif_clkstctrl,
657 CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
658 wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
659 wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
663 void bypass_dpll(u32 const base)
665 do_bypass_dpll(base);
666 wait_for_bypass(base);
669 void lock_dpll(u32 const base)
675 void setup_clocks_for_console(void)
677 /* Do not add any spl_debug prints in this function */
678 clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
679 CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
680 CD_CLKCTRL_CLKTRCTRL_SHIFT);
682 /* Enable all UARTs - console will be on one of them */
683 clrsetbits_le32((*prcm)->cm_l4per_uart1_clkctrl,
684 MODULE_CLKCTRL_MODULEMODE_MASK,
685 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
686 MODULE_CLKCTRL_MODULEMODE_SHIFT);
688 clrsetbits_le32((*prcm)->cm_l4per_uart2_clkctrl,
689 MODULE_CLKCTRL_MODULEMODE_MASK,
690 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
691 MODULE_CLKCTRL_MODULEMODE_SHIFT);
693 clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
694 MODULE_CLKCTRL_MODULEMODE_MASK,
695 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
696 MODULE_CLKCTRL_MODULEMODE_SHIFT);
698 clrsetbits_le32((*prcm)->cm_l4per_uart4_clkctrl,
699 MODULE_CLKCTRL_MODULEMODE_MASK,
700 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
701 MODULE_CLKCTRL_MODULEMODE_SHIFT);
703 clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
704 CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
705 CD_CLKCTRL_CLKTRCTRL_SHIFT);
708 void do_enable_clocks(u32 const *clk_domains,
709 u32 const *clk_modules_hw_auto,
710 u32 const *clk_modules_explicit_en,
715 /* Put the clock domains in SW_WKUP mode */
716 for (i = 0; (i < max) && clk_domains[i]; i++) {
717 enable_clock_domain(clk_domains[i],
718 CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
721 /* Clock modules that need to be put in HW_AUTO */
722 for (i = 0; (i < max) && clk_modules_hw_auto[i]; i++) {
723 enable_clock_module(clk_modules_hw_auto[i],
724 MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
728 /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
729 for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
730 enable_clock_module(clk_modules_explicit_en[i],
731 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
735 /* Put the clock domains in HW_AUTO mode now */
736 for (i = 0; (i < max) && clk_domains[i]; i++) {
737 enable_clock_domain(clk_domains[i],
738 CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
744 switch (omap_hw_init_context()) {
745 case OMAP_INIT_CONTEXT_SPL:
746 case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
747 case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
748 enable_basic_clocks();
750 scale_vcores(*omap_vcores);
752 #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
753 setup_non_essential_dplls();
754 enable_non_essential_clocks();
756 setup_warmreset_time();
762 if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context())
763 enable_basic_uboot_clocks();
766 void gpi2c_init(void)
768 static int gpi2c = 1;
771 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);